阅读说明：本技术 超低功率的自适应可重新配置的系统 (Ultra-low power adaptive reconfigurable system ) 是由 E·蒂阿加拉詹 A·佩奇 H·库茨 K·卡斯托-佩里 R·辛格 E·汉奇奥格鲁 B·苏拉 于 2019-08-21 设计创作，主要内容包括：所公开的实施方式描述了具有多个可重新配置模拟电路的可编程模拟子系统(PASS)。PASS可以耦合到输入/输出设备,以接收输入信号,并且可以耦合到接口,以与中央处理单元传输数据。在第一PASS配置中,在多个可重新配置模拟电路具有第一配置设置的情况下,PASS可以通过多个可重新配置模拟电路处理输入信号,以基于该输入信号生成第一输出值。响应于第一输出值,PASS可以将多个可重新配置模拟电路重新配置为具有第二配置设置的第二PASS配置,使得第二配置设置不同于第一配置设置。(The disclosed embodiments describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and may be coupled to an interface to communicate data with the central processing unit. In a first PASS configuration, where the plurality of reconfigurable analog circuits have a first configuration setting, the PASS may process an input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. In response to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits to a second PASS configuration having second configuration settings such that the second configuration settings are different from the first configuration settings.)

1. An apparatus, comprising:

an input/output (IO) device to receive a first input signal; and

a programmable analog subsystem (PASS) coupled to the IO device, wherein the PASS comprises:

a plurality of reconfigurable analog circuits; and

an interface for communicating data with a Central Processing Unit (CPU),

wherein the PASS is configured to:

processing, in a first PASS configuration, the first input signal by the plurality of reconfigurable analog circuits to generate a first output value based on the first input signal, the plurality of reconfigurable analog circuits having a first configuration setting in the first PASS configuration; and is

Reconfiguring at least one of the plurality of reconfigurable analog circuits to a second PASS configuration having second configuration settings in response to the first output value, wherein the second configuration settings are different from the first configuration settings.

2. The apparatus of claim 1, wherein the plurality of reconfigurable analog circuits have higher operating power in the second PASS configuration than in the first PASS configuration.

3. The apparatus of claim 1, wherein the PASS is further configured to:

processing a second input signal by the plurality of reconfigurable analog circuits to generate a second output value in the second PASS configuration, the plurality of reconfigurable analog circuits having the second configuration setting in the second PASS configuration; and is

Outputting a wake-up signal to the CPU through the interface in response to the second output value.

4. The apparatus of claim 3, wherein the PASS is further configured to:

receiving, from the CPU, configuration data comprising a third configuration setting in response to outputting the wake-up signal to the CPU, wherein the third configuration setting is different from the second configuration setting; and is

Reconfiguring the plurality of reconfigurable analog circuits to a third PASS configuration having the third configuration setting.

5. The apparatus of claim 1, wherein the PASS is further configured to:

processing a second input signal by the plurality of reconfigurable analog circuits to generate a second output value in the second PASS configuration, the plurality of reconfigurable analog circuits having the second configuration setting in the second PASS configuration; and is

Outputting a mode selection signal to the CPU through the interface in response to the second output value.

6. The apparatus of claim 1, wherein the PASS includes a first set of registers to store the first configuration settings and a second set of registers to store the second configuration settings.

7. The apparatus of claim 1, wherein the PASS includes a set of registers to store the first configuration settings, and wherein reconfiguring the plurality of reconfigurable analog circuits to the second configuration is:

modifying contents of the set of registers to store the second configuration setting; and

reconfiguring at least one of the reconfigurable analog circuits according to the modified contents of the set of registers.

8. The apparatus of claim 1, wherein the reconfigurable analog circuit comprises at least two of:

a Continuous Time Block (CTB) for performing signal processing in a continuous time domain;

an analog-to-digital converter (ADC) circuit to process an output of the CTB;

one or more multiplexers to selectively connect a plurality of pins of the IO device to a plurality of inputs of at least one of the CTB or the ADC circuitry; or

PASS logic circuitry to reconfigure the PASS from the first PASS configuration to the second PASS configuration according to an output of the ADC circuitry.

9. The apparatus of claim 8, wherein the reconfigurable analog circuit further comprises at least one of:

an analog reference block for providing at least one of a voltage reference, a current reference, or a clock signal; or

A finite state machine having a plurality of states selectable according to an output of the PASS logic circuit.

10. A system, comprising:

an input/output (IO) device for receiving a first input signal from a signal source;

a digital subsystem comprising a memory and a Central Processing Unit (CPU) coupled to the memory;

a programmable analog subsystem (PASS) coupled to the IO devices and to the digital subsystem, wherein the PASS comprises:

a plurality of reconfigurable analog circuits; and

an interface for communicating data with the CPU,

wherein the PASS is configured to:

processing, in a first PASS configuration and with the digital subsystem in a sleep mode, the first input signal by the plurality of reconfigurable analog circuits to generate a first output value based on the first input signal, the plurality of reconfigurable analog circuits having first configuration settings in the first PASS configuration; and is

In response to the first output value,

reconfiguring the plurality of reconfigurable analog circuits to a second PASS configuration having second configuration settings without involving a CPU, wherein the second configuration settings are different from the first configuration settings.

11. The system of claim 10, wherein the plurality of reconfigurable analog circuits have a higher operating power in the second PASS configuration than in the first PASS configuration.

12. The system of claim 10, wherein the PASS is further configured to:

processing a second input signal by the plurality of reconfigurable analog circuits to generate a second output value in the second PASS configuration, the plurality of reconfigurable analog circuits having the second configuration setting in the second PASS configuration; and is

Outputting a mode selection signal to the digital subsystem through the interface in response to the second output value.

13. The system of claim 12, wherein the PASS is further configured to:

receiving configuration data from the digital subsystem including a third configuration setting in response to outputting the mode select signal to the digital subsystem, wherein the third configuration setting is different from the second configuration setting; and is

Reconfiguring the plurality of reconfigurable analog circuits to a third PASS configuration having the third configuration setting.

14. The system of claim 10, wherein the PASS includes a first set of registers for storing the first configuration settings and a second set of registers for storing the second configuration settings.

15. The system of claim 10, wherein the PASS includes a set of registers to store the first configuration settings, and wherein reconfiguring the plurality of reconfigurable analog circuits to the second configuration is:

modifying contents of the set of registers to store the second configuration setting; and

reconfiguring at least one of the reconfigurable analog circuits according to the modified contents of the set of registers.

16. A method, comprising:

receiving, by a programmable analog subsystem (PASS) coupled to an input/output (IO) device, a first input signal from the IO device, the PASS comprising a plurality of reconfigurable analog circuits and an interface for communicating data with a Central Processing Unit (CPU);

processing the first input signal by the plurality of reconfigurable analog circuits with the PASS in a first PASS configuration, wherein the plurality of reconfigurable analog circuits have a first configuration setting in the first PASS configuration;

generating a first output value based on the first input signal; and

reconfiguring the functions of the plurality of reconfigurable analog circuits to a second PASS configuration having second configuration settings in response to the first output value, wherein the second configuration settings are different from the first configuration settings.

17. The method of claim 16, wherein the plurality of reconfigurable analog circuits have higher operating power in the second PASS configuration than in the first PASS configuration.

18. The method of claim 16, wherein the plurality of reconfigurable analog circuits are reconfigured to the second PASS configuration in response to determining that the first output value satisfies a first threshold criterion.

19. The method of claim 16, further comprising:

processing a second input signal by the plurality of reconfigurable analog circuits with the PASS in the second PASS configuration, wherein the plurality of reconfigurable analog circuits have the second configuration setting in the second PASS configuration;

generating a second output value; and

responsive to the second output value, outputting a signal to the CPU through the interface.

20. The method of claim 19, wherein the signal is output to the CPU in response to determining that the second output value satisfies a second threshold criterion.

21. The method of claim 19, further comprising:

receiving, from the CPU, configuration data comprising a third configuration setting in response to outputting the signal to the CPU, wherein the third configuration setting is different from the second configuration setting; and

reconfiguring the plurality of reconfigurable analog circuits to a third PASS configuration having the third configuration setting.

22. The method of claim 19, wherein the PASS includes a first set of registers for storing the first configuration settings and a second set of registers for storing the second configuration settings.

23. The method of claim 19, wherein the PASS includes a set of registers for storing the first configuration settings, and wherein reconfiguring the plurality of reconfigurable analog circuits to the second configuration comprises:

modifying contents of the set of registers to store the second configuration setting; and

reconfiguring at least one of the reconfigurable analog circuits according to the modified contents of the set of registers.

Technical Field

The present disclosure relates to Integrated Circuit (IC) devices having programmable analog blocks; and more particularly to optimizing performance and power management of an IC device by reconfiguring programmable simulation blocks in response to changing conditions.

Background

An integrated circuit device may include both analog and digital blocks. The analog blocks are often made reconfigurable to meet the requirements of multitasking and to facilitate optimal power management. The analog block can provide functions that the digital block cannot provide, such as making measurements and performing comparisons of measured quantities. In combination, the analog and digital blocks may combine the flexibility of software instructions executed by the digital blocks with the speed of the analog hardware. While digital blocks are better at handling more computationally burdensome tasks, analog blocks can provide superior performance where speed and power savings are critical. Therefore, to optimize the speed, complexity and energy efficiency of the process, it is important to carefully distribute the execution of the various tasks between the analog and digital blocks. This is particularly critical where the integrated circuit is used in medical electronics, internet of things devices, and a variety of portable electronic devices with limited energy sources, and where the benefits of effective power management may be particularly significant.

Drawings

FIG. 1 is a block diagram of one exemplary embodiment of a reconfigurable low power programmable analog subsystem.

FIG. 2a is a block diagram of one exemplary embodiment of a continuous-time block (or discrete-time block) of an exemplary low-power programmable analog subsystem.

Figure 2b is a block diagram of one exemplary embodiment of a successive approximation register analog-to-digital converter circuit of the exemplary low power programmable analog subsystem.

FIG. 2c is a block diagram of one exemplary embodiment of an analog reference block of an exemplary low power programmable analog subsystem.

FIG. 3 is a block diagram of another exemplary embodiment of a reconfigurable low power programmable analog subsystem integrated with a digital subsystem, an input/output subsystem, system-wide resources, and peripheral resources.

FIG. 4 is a block diagram of one exemplary illustration of processing input signals having various input levels by a reconfigurable low power programmable analog subsystem integrated with a digital subsystem, in one possible implementation.

Figure 5a is a block diagram of one exemplary embodiment of an application of a reconfigurable low power programmable analog subsystem using radio reception and transmission.

FIG. 5b is a block diagram illustrating the application of a reconfigurable low power programmable analog subsystem for speech recognition in an exemplary embodiment.

FIG. 6 is a timing diagram showing relative power levels for various exemplary states of two subsystems, including different states of a reconfigurable low power programmable analog subsystem and a digital subsystem including a Central Processing Unit (CPU), in one illustrative embodiment.

FIG. 7 is a flow diagram of one possible embodiment of a method of reconfiguring a low-power programmable analog subsystem in response to an input signal.

FIG. 8 is a flow diagram of one possible embodiment of a method of reconfiguring a low-power programmable analog subsystem integrated with a digital subsystem in response to an input signal.

Detailed Description

Aspects and embodiments of the present disclosure are directed to optimizing performance and power management of an Integrated Circuit (IC) device by exploiting autonomous reconfigurability of analog circuits independent of a digital processor, which may remain in a sleep state or perform different operations. The processor may be located in the same die/substrate as the analog circuit or may be implemented separately. The analog circuitry may be combined into a programmable analog subsystem (PASS) that may be used in combination with, or in some embodiments separate from, a digital subsystem that may include a Central Processing Unit (CPU) and a memory device. In some embodiments, the digital subsystem may be a large-scale computing device, a General Processing Unit (GPU), or an Application Processing Unit (APU). In other embodiments, the digital subsystem may be a microcontroller unit (MCU) with a CPU and memory, and designed to manage specific operations. The microcontroller unit may be a separate circuit or a circuit embedded in a larger system. PASS may use logic circuitry (in some embodiments, in conjunction with one or more finite state machines) to make decisions regarding reconfiguring one or more analog devices, such as input-output (IO) devices, routing devices, continuous-time blocks (CTBs), discrete-time blocks, analog-to-digital converters (ADCs). For example, upon receiving an input signal and processing it into one or more output data, the PASS may reconfigure one or more of its programmable analog circuits in response to the output data. The PASS may perform such reconfiguration without waking the CPU if the CPU is in a sleep state, or without requesting CPU instructions if the CPU is in an active state. The PASS may continue to receive and process incoming signals and monitor further outgoing data. In response to such further output data, the PASS may transmit a wake-up instruction to the CPU. The CPU may perform the processing and, in some embodiments, may output configuration data to the PASS with additional instructions for how to reconfigure one or more PASS analog circuits.

Modern computing devices (especially automobiles, wearable, handheld, metering, integrated appliances, etc.) require increasingly efficient power management. Many portable devices pack a large amount of computing resources into a small form factor. The compact size may limit the energy storage capability of the portable device. Therefore, optimizing energy consumption during the execution of various tasks will become more and more critical. Generally, performing tasks faster with a minimum number of basic components results in better utilization of energy resources. The IC may be comprised of a digital subsystem (e.g., a microcontroller unit) with a CPU and a reconfigurable analog subsystem. The digital subsystem may remain in a low power sleep mode while the analog subsystem may be in a mode with limited functionality. The analog subsystem may receive an input signal (e.g., a speech signal) through its front end module and provide the signal to an analog-to-digital converter after analog processing (e.g., decoding, filtering, and amplification), and then digital pre-processing. The digital pre-processing output may indicate that the input signal meets some threshold criteria or otherwise indicates an event. In response to such a determination, the analog subsystem may transmit a wake-up instruction to the CPU. The CPU may then execute instructions stored in the memory of the digital subsystem and reconfigure the parameters of the analog subsystem so that the analog circuitry may provide functionality that better adapts to changing conditions.

For example, the analog subsystem may monitor the input signal for one or more conditions, such as the ambient temperature falling below some preset minimum value. In such an event, the simulation block may wake the CPU, which may turn on or adjust the heating system while executing software or firmware. In addition, the CPU may reconfigure the analog blocks. After the heating system is turned on, the simulation block may be reconfigured to monitor the temperature rise above some preset maximum. The CPU and/or other digital blocks may then return to a low power sleep mode while the reconfigured analog blocks may further monitor the ambient temperature. Upon reaching the maximum temperature, the analog block may trigger another processor wake-up for further digital processing (e.g., controlling a heating system) and/or analog block reconfiguration. As a result, power consumption can be greatly reduced.

However, such methods have a number of disadvantages. Which relies on CPU functionality (processing power and instruction execution) to reconfigure the programmable analog circuit. The CPU may consume a significant amount of power even when performing a minimal reconfiguration of the analog subsystem. Furthermore, the CPU may take a significant amount of time to wake up from the sleep mode to the active state, such that power economy in the sleep mode may come at the expense of delayed performance. Thus, this lack of reconfigurability of the analog circuitry while the CPU remains in sleep mode may be a disadvantage if power management and processing speed are necessary. In particular, in situations where the CPU may be invoked to respond to multiple false alarms, the utilization of computing resources may become suboptimal. This problem is further exacerbated when the various analog blocks have fixed functions (e.g., resolution or monitoring parameter ranges) and can only be reconfigured if a CPU is involved. As a result, in dynamic environments, integrated circuits with CPU-only reconfigurable analog blocks become incapable of efficient power management when the typical time interval between monitored events or conditions becomes shorter than the time required for CPU wakeup and data processing.

Aspects and embodiments of the present disclosure address this and other deficiencies of existing ICs by providing dynamic configurability of programmable analog circuits without active CPU involvement or input. Various analog circuits may be combined into a Low Power (LP) programmable analog subsystem (PASS) that is capable of being in one of a plurality of states without CPU input, which may be selected in response to one or more received input signals or external conditions. For example, the LP PASS may reconfigure itself to a different configuration while the CPU remains in a sleep state. In some implementations, the CPU may be in an active state, but the LP PASS may perform the reconfiguration without requesting CPU instructions. This may allow the CPU to perform other functions, such as processing digital tasks that may or may not be related to the tasks being performed by the LP PASS. This may allow the same task to be processed faster if both the LP PASS and the CPU are processing different portions of the same task, or it may allow the LP PASS and the CPU to process different tasks at the same time.

The selection of the state of the LP PASS may be accomplished by a logic circuit that receives a digital signal from an analog-to-digital converter (ADC) circuit or from a comparator. The ADC circuit may receive one or more analog signals that are pre-processed by a front-end analog circuit. The input signal received by the LP PASS may be indicative of various external conditions. In some embodiments, the input signal may be a radio wave, a light signal, a sound wave, a motion indication, a direction, a speed, a temperature, a mechanical contact, a chemical composition, or any other signal that may be generated by an environmental sensor that is indicative of the state of the physical or chemical environment surrounding the LP PASS. In some embodiments, the sensor may detect an environment located at a significant distance from the LP PASS.

FIG. 1 is a block diagram of an exemplary embodiment 100 of a reconfigurable LP PASS. The LP PASS 102 may be connected to one or more input-output (IO) devices to receive input signals from one or more signal sources. The IO devices may include one or more general purpose input output device (GPIO) ports 104 or programmable input output (PRGIO) blocks 106, which may include a plurality of pins, switches, or sensors capable of passing input signals to the LP PASS 102 as described above. In some embodiments, the IO device may include a Radio Frequency (RF) front end to support radio processing of a wireless area network, a personal area network, or a software defined radio system. The RF front end is capable of receiving, transmitting and/or processing RF (or intermediate frequency) signals, which includes other conventional components for amplifying, decoding and/or radio signal processing. In some embodiments, various IO devices (e.g., temperature sensors) may be mounted on the same chip (e.g., the same Si substrate) as the LP PASS 102. In other embodiments, some or all of the IO devices may be external to the LP PASS 102, but communicatively coupled with the LP PASS 102.

Signals input through the IO devices may be routed to the various analog blocks via a plurality of Multiplexers (MUXs). FIG. 1 shows an exemplary system with two MUXs 110 and 112. In other embodiments, additional MUXs may be present to route input data from multiple IO devices to various circuits in the LP PASS. The processing path for the input signal is shown in solid lines in fig. 1, where the arrows indicate the direction of signal propagation. In some embodiments, some input signals may be routed to a Continuous Time Block (CTB)120 for continuous time domain processing. In the CTB 120, various input signals may be decoded, amplified, converted (e.g., from a current signal to a voltage signal, or from a current signal to a time signal, or from a voltage signal to a frequency signal, etc.), compared, buffered, or the like. In some embodiments, a Discrete Time Block (DTB) for signal processing at discrete times may be used instead of or in addition to the CTB. In an exemplary embodiment, the CTB/DTB 120 output may be input to an ADC, such as a Successive Approximation Register (SAR) ADC 130. SAR ADC 130 may convert the input analog signal into a digital signal. The system of multiplexers may route some of the input signals directly to SAR ADC 130, bypassing CTB/DTB 120. For example, in some embodiments, a dedicated SAR MUX 112 may be used to route input signals intended to be provided directly to SAR ADC 130. The analog routing block (AROUTE)114 may provide control data (e.g., configuration of switches) for some or all of the MUXs of the LP PASS 102. The AROUTE 114 may provide signal routing data to facilitate connection between IO devices and a plurality of analog blocks (e.g., CTB/DTB 120 and SAR ADC 130). Different configurations of the LP PASS 102 may have different routing structures. For example, in some configurations intended for coarse speech detection, the acoustic input signal from the microphone input may be passed directly to the SAR ADC 130 through the SAR MUX 112. Conversely, in other configurations, where more accurate speech recognition is intended, voice input from the microphone may be routed first to CTB/DTB 120 for continuous or discrete-time processing. As another example, in the instance of smoke detection, the routing fabric may direct the input signal to SAR ADC 130, but once the presence of smoke has been determined, LP PASS 102 may be reconfigured to a different configuration in which the input signal is routed through CTB/DTB 120 for additional processing intended to determine smoke constituents. By providing control signals to the MUX, the array 114 may facilitate such input signal rerouting. In some embodiments, the LP PASS 102 may include one or more buses. In some embodiments, the LP PASS may comprise a bus architecture. In some embodiments, routing via the bus may be controlled by providing control signals to the MUXs 110 and 112 through the areute 114. In some embodiments, some buses may provide direct signal routing to the various blocks of the LP PASS 102 through the MUXs 110 and 112.

SAR ADC 130 may convert one or more signals (e.g., continuous-time signals) into one or more digital signals. The SAR ADC 130 may use a binary search having a resolution that depends on the particular configuration of the LP PASS 102. For example, in a default configuration of LP PASS, to detect a certain quantity a, SAR ADC 130 may be configured to output only a single bit having a value of 0 or 1 corresponding to the quantity a being below or above a certain predetermined threshold. Once the amount a is above the threshold for some amount of time (e.g., cumulatively over 5 of the last 10 seconds), the SAR ADC 130 may be reconfigured to a state in which the output value is specified in two bits (e.g., states 00, 01, 10, 11), three bits (001, 101, etc.), or more, depending on the resolution desired.

In some implementations, the functionality of the analog circuitry (e.g., MUX, CTB, SAR ADC) may be supported by an analog reference block (AREF) 140. The AREF 140 may provide reference voltages and reference currents to other analog blocks. For example, AREF 140 may provide a bandgap voltage, a low voltage, a high voltage, and the like. In some non-limiting examples, the low voltage may be 1.1V, while the high voltage may be in the range of 2.7-5.5V, or any other value. AREF 140 may similarly provide reference currents to the various analog blocks. In some embodiments, the reference voltage and reference current may be specific to the analog block to which they are provided. In some embodiments, the reference voltage and the reference current may be temperature independent. In some embodiments, the reference voltage and the reference current may be proportional to temperature, or may have some other predetermined temperature dependence. In some implementations, AREF 140 may have repeater capabilities such that multiple reference voltages (and/or currents) may be provided to various analog circuits. AREF 140 may further provide clock signals to the various analog circuits. In some implementations, AREF 140 may provide different clock signals to different analog circuits.

Signals processed by the analog blocks (and circuitry within these blocks) may be input into the digital processing block 150 of the LP PASS 102. For example, as shown by the solid line in fig. 1, the digital signal may be passed from SAR ADC 130 to logic circuit 152 of digital processing block 150. The logic circuit 152 may include a plurality of interconnected logic gates. The logic circuitry 152 is capable of executing instructions stored in a memory device 154, hereinafter the memory device 154 is referred to simply as memory 154. In some embodiments, memory 154 may be Read Only Memory (ROM). In other embodiments, memory 154 may be Random Access Memory (RAM), or flash memory, or any other type of memory, or combination of different types of memory devices.

The logic circuit 152 may process one or more digital input signals provided by the SAR ADC 130 corresponding to various analog inputs of the LP PASS 102. For example, the speech recognition digital input signal may be processed along with temperature, humidity, atmospheric pressure, and other digital input signals. In some embodiments, different digital input signals may be processed by different gates of the logic circuit 152. In other embodiments, different digital input signals may be processed by the same gates of the logic circuit 152, but sequentially in time, e.g., such that processing of the digital input signal s1 may occur over time interval t1, followed by processing of the digital input signal s2 over time interval t2, followed again by processing of the digital input signal s1, and so on. The digital outputs of the processing of the various digital inputs by the logic circuit 152 may be temporarily or permanently stored in the memory 154, or until the next boot up.

The digital output of the logic circuit 152 may be used to reconfigure the various analog blocks and circuits of the LP PASS 102, as indicated schematically by the dashed lines in fig. 1. For example, the dashed lines extending from logic circuit 152 and FSM 158 to AROUTE 114 schematically indicate how reconfiguring AROUTE 114 may be performed. Conversely, the dashed lines from the AROUTE 114 to the MUXs 110 and 112 indicate that the routing of data by the MUXs 110 and 112 may be reconfigured by the AROUTE 114, for example, by reconfiguring one or more MUX switches. For example, the LP PASS 102 may be in a first (e.g., low power) configuration in which the analog blocks (e.g., CTB/DTB 120, SAR ADC 130) may be configured to process the input analog signals at a lower resolution than the maximum capability of the LP PASS. The LP PASS 102 and its logic circuitry 152 may remain in a standby mode capable of monitoring for indications of some events in the input analog signal. For example, the LP PASS 102 may be monitoring the audio noise of a human speech instance. The LP PASS 102 may not conclusively recognize speech at the lowest LP PASS resolution, but the logic 152 is able to detect the signature of human speech. For example, the memory 154 may store human speech criteria (e.g., typical pitch and tempo) at a set low resolution. If the LP PASS 102 is monitoring the input analog signals for an indication of an event, and such an indication is obtained in an ultra-low power configuration (which may also be a low resolution mode), the logic circuitry 152 may reconfigure one or more of the analog circuits to the second configuration of the LP PASS 102 to increase the resolution of the analog signal processing and/or analog-to-digital conversion. Correspondingly, the analog circuitry may have a higher operating power in the second configuration than in the first configuration. In some embodiments, the analog circuit may have a lower operating power in the second configuration than in the first configuration. For example, the first configuration may be used to implement an active state, while the second configuration may be used to implement a sleep state for the LP PASS. As discussed in more detail below, there may be several active states (e.g., active 1, active 2, etc.) that are characterized by different levels of LP PASS functionality and different levels of power consumption. Similarly, there may be different sleep states (e.g., idle, deep sleep, etc.).

Different LP PASS configurations may be characterized by different resolutions of the continuous-time processing of the input signal and different resolutions of the output digital signal. For example, when the LP PASS 102 is reconfigured, the digital resolution may be increased from 8 bits to 12 bits, and from 12 bits to 16 bits. Higher resolution may require longer processing time and/or more power consumption. Since losing the lowest resolution may result in the fastest processing and/or lowest power conversion, the LP PASS 102 may begin processing the lowest resolution configuration, but reconfigure itself (e.g., its SAR ADC 130) in response to detection of the marker of the particular event.

In some implementations, to reconfigure the LP PASS 102 to the second configuration, the logic circuit 152 may reconfigure some or all of the blocks CTB/DTB 120, SAR ADC 130, AREF 140, areute 114, MUX 110, and SAR MUX 112. For example, to increase the resolution of continuous-time processing, the logic circuitry 152 may execute instructions to the AREF 140 to increase the frequency of the clock signal output by the AREF to the CTB/DTB 120. In another example, to increase the resolution of the analog-to-digital conversion, SAR ADC 130 and CTB/DTB 120 may be reconfigured from, for example, a 12-bit 20ksps sampling mode to a 12-bit 1MSPS sampling mode. In some embodiments, the sampling rate may remain the same, but the resolution may be increased. Conversely, the sampling rate may be increased, but the resolution may not be increased.

In some embodiments, the LP PASS 102 may include a finite state machine block (FSM) 158. FSM 158 may be implemented in hardware as a circuit (or set of circuits) separate from logic circuitry 152. In some embodiments, FSM 158 may be implemented on the same circuitry as logic circuit 152. In some embodiments, FSM 158 may be implemented as instructions executed by logic circuitry 152. FSM 158 can receive inputs from either logic circuit 152 directly from SAR ADC 130 or both. In response to the received inputs, FSM 158 can select one or more of the FSM states. The FSM state may correspond to a setting of any one of the analog circuits, a setting of multiple analog circuits, or a setting of the LP PASS 102 as a whole. The states selected by FSM 158 may be used to reconfigure some or all of blocks CTB/DTB 120, SAR ADC 130, AREF 140, AROUTE 114, MUX 110, and SAR MUX 112.

FSM 158 may be one or more of a finite state transformer, an intelligent logic circuit, a programmable logic device, a controller, an inference engine, a receptor, a classifier, or a sequencer type, or any combination thereof. The classifier FSM is able to select a state from a plurality of available states based on an input. For example, the FSM used by the cardiac monitoring device may select whether to perform a cardiac rhythm correction, perform an electrocardiogram measurement, or dispatch a communication to a medical professional based on the patient's heart rate. The acceptor FSM is capable of generating a binary output. In some embodiments, the output of state 0 means that no change to the current configuration of the LP PASS 102 is to be implemented, while the output of state 1 means that the LP PASS 102 must be reconfigured. In some embodiments, the selection of the LP PASS configuration may be performed sequentially: for example, the output of state 1 means that the configuration with the next available resolution (or power consumption) is to be selected. As an illustrative example, the 12-bit 20KSPS sampling configuration of SAR ADC 130 may be followed by a 12-bit 1MSPS configuration, followed by a 16-bit 62.5KSPS configuration. As an example, the FMS may be used as an inference engine in speech recognition, for example, when the LP PASS 102 may be in a standby mode looking for indicia of codewords. The FSM will study the phenomena observed in the digital domain (after the ADC) and match the data with pre-loaded data in memory to make inferences. Such a FSM may also act as an inference engine to make key decisions in image processing as well as speech recognition.

Fig. 2a, 2b and 2c show some possible high-level architectures of a continuous-time block (CTB), a successive approximation register (SAR ADC) and an analog reference block (AREF). Some of the components shown in fig. 2a, 2b and 2c and those in subsequent fig. 3 and 4 may be the same as in fig. 1. Thus, items referenced by three digits (e.g., CTB/DTBs 120, 220, 320, 420) that differ only by the first digit may refer to the same component.

FIG. 2a is a block diagram of one exemplary embodiment of the CTB/DTB 220 of the exemplary low power programmable analog subsystem 102. CTB/DTB 220 may have sufficient bandwidth to support a specified digital sampling rate, e.g., 12-bit sampling at 1MSPS or 16-bit sampling at 62.5 KSPS. In some embodiments, CTB/DTB 220 may have two or more operational amplifiers 221 and a resistor network 222. In some embodiments, CTB/DTB 220 may also include a pump 223, which may be a dual charge pump. A pump 223 may be used to facilitate operation of the operational amplifier 221. In some embodiments, CTB/DTB 220 may include internal logic 224 to control internal routing with firmware controllable switches. The routing matrix 225 may have a plurality of buses, a plurality of switches, and a plurality of latches. The routing matrix 225 may also have a different multiplexer than the MUX 110 inside the CTB/DTB 220. Some or all of the routing switches may be controlled by components external to CTB/DTB 220, such as logic circuit 152, FSM 158, and AROUTE 114. In some embodiments, routing matrix 225 may connect CTB/DTB 220 to multiple IO pins of IO devices such as GPIO 104 and PRGIO 106. The GPIO pins may be grouped into 8 pins that may represent separate analog ports. CTB/DTB 220 may also include a decoder 226 for processing the encoded input. CTB/DTB 220 may also have capacitor circuitry 229 (e.g., a capacitor array) for discrete time processing. The components of CTB/DTB 220 (e.g., operational amplifier 221 and resistor network 222) may be configured to function as one or more buffers 227 or comparators 228. Some of the components of CTB/DTB 220 shown in fig. 2a may be optional and may not be used in some embodiments. For example, capacitor circuit 229 may not be present in a Continuous Time Block (CTB) implementation of CTB/DTB 220. In some embodiments, a more compact CTBm (CTB-mini) may be used that has the same or similar functionality as a typical CTB but with less capacity.

Figure 2b is a block diagram of one exemplary embodiment of a successive approximation register analog-to-digital converter circuit (SAR ADC)230 of the exemplary low power programmable analog subsystem 102. SAR ADC 230 may include a sample/hold circuit 231 to capture an input analog signal (e.g., a signal from SAR MUX 112 and/or CTB/DTB 220) based on a specified sampling frequency. The SAR ADC 230 may also have a reference buffer 232 to store a reference signal (e.g., a reference voltage and current) provided by the AREF 140. SAR ADC 230 may also have a digital-to-analog converter (DAC)233, which may feed analog signals into one or more comparators 234 at discrete time intervals. DAC 233 may also include or be coupled to a capacitor array 235. Comparator(s) 234 may compare the input signal stored in sample/hold circuit 231 with the output of DAC 233, determine a corresponding difference, and send the difference to SAR logic circuit 236. SAR logic circuit 236 may perform a successive approximation algorithm until the analog signal stored in sample/hold circuit 231 is digitized to an accuracy specified by the number of bits (e.g., 8 bits, 12 bits, 16 bits, depending on the configuration) of the digital output of SAR ADC 230. SAR ADC 230 may use clock 237 to digitally sample the input analog signal. The clock may include timing logic that may provide different sampling rates at different stages of the analog-to-digital conversion. In some embodiments, SAR ADC 230 may further deploy level shifter(s) 238 to convert the low voltage digital control signal to a higher voltage analog control signal for improving the signal-to-noise ratio and reducing the power consumption of SAR ADC 230. SAR ADC 230 may also include a power control unit 239. Some of the components of the SAR ADC 230 shown in fig. 2b may be optional and may not be used in some embodiments.

FIG. 2c is a block diagram of one exemplary embodiment of the simulation reference block 240 of the exemplary low power programmable simulation subsystem 102. The AREF 240 may include a clock 241 capable of providing multiple configurable clock references to the analog circuitry of the LP PASS 102. For example, the clock 241 may provide a clock reference to the pump 223 of the CTB/DTB 220, the clock 237 provided to the SAR ADC 230, and so on. The voltage reference block 242 may provide an accurate voltage reference to some or all of the analog blocks (and circuitry within the blocks) of the LP PASS 102. For example, the voltage reference block 242 may provide a bandgap voltage reference, an analog ground voltage reference, an analog supply voltage reference, and the like. Different analog blocks may receive different voltage references. Current reference block 243 may provide an accurate current reference to some or all of the analog blocks. This may include, for example, a proportional to absolute temperature current (IPTAT), an absolute temperature independent current (IZTAT), and a complementary to absolute temperature (i.e., decreasing with absolute temperature) current (ICTAT). In some embodiments, providing multiple voltage and current reference values may be facilitated by a Programmable Reference Block (PRB) 244. The PRB 244 may obtain an input reference voltage (or current) provided by the voltage reference block 242 (current reference block 243), multiply it by a constant, and output multiple divided versions of the obtained voltage (current) value for use in different blocks of the LP PASS. The output reference voltage (current) may be routed through the AROUTE 114 to the corresponding analog block. Similarly, the clock 241 output may also be delivered to the intended destination through the AROUTE 114. The operations performed by AREF 240, i.e., voltage/current multiplication and division, described above, may be facilitated by an internal routing matrix 245. PRB 244 can receive a reconfiguration instruction from logic circuit 152 or FSM 158. In response to receiving such instructions, PRB 244 may adjust the voltage and current references generated and output by AREF 240. Some of the components of AREF 240 shown in fig. 2c may be optional and may not be used in some embodiments.

Fig. 3 is a block diagram of an exemplary implementation 300 of a reconfigurable low power programmable analog subsystem (LP PASS)302 integrated with a digital subsystem 360, an input/output subsystem 303, and peripheral resources 380. The IC system shown in fig. 3 may be used in a variety of applications, such as, but not limited to, internet of things, wearable devices, motion detectors, voice activated control appliances, smart home appliances, portable appliances, battery operated appliances, automotive devices, chemical sensing, medical electronics (e.g., glucose, cardiac monitoring), and many others. In some implementations, the LP PASS 302 may be in one of a variety of configurations that differ from one another in terms of functionality and power consumption and that may be used to implement different states of the LP PASS 302, e.g., deep sleep, active. Additional states may be implemented if advantageous in a particular application. For example, a set of activity states may include a number of different states, e.g., Activity 1, Activity 2, Activity 3, etc., that may differ in the amount and complexity of processing that may be performed by the LP PASS 302. For example, the SAR ADC in the active 1 state may operate in a 12-bit low sampling mode, while the SAR ADC in the active 3 state may operate in a 16-bit high sampling mode. Digital subsystem 360 may similarly be in one of a variety of states. In one of these states, the CPU OFF state, the Central Processing Unit (CPU)362 of the digital subsystem may be inactive. In another state, the CPU 362 may be fully active, i.e., a CPU ON state. In some embodiments, additional intermediate states may also be implemented in which the CPU 362 may be partially active with varying degrees of CPU functionality.

The LP PASS 302 may include the same blocks as the LP PASS 102 shown in FIG. 1. Some blocks may exist in more than one copy. For example, in the embodiment shown in FIG. 3, there are two sets of MUX, CTB, SAR ADC, memory device, register, and FSM. Each group designated with characters (1) and (2) added to the reference numeral can perform separate processing on an analog signal input through the IO subsystem 303. Each group can be reconfigured independently by logic 352 and the group-specific FSMs, e.g., FSM 358(1) for the left group and FSM 358(2) for the right group. In some embodiments, one or more devices indicated as separate in fig. 3 may be shared between two groups. For example, FSM 358(1) and FSM 358(2) may actually be a single FSM serving both groups. In other embodiments, the system shown in fig. 3 may also include a bank with additional CTB and SAR ADCs and other blocks. In other embodiments, there may be additional groups (third, fourth …).

The functionality of the multiple sets of LP PASS 302 may be similar to the functionality of the single set of LP PASS 102. The IO subsystem may include GPIO 304, PRGIO 306, and Programmable Interconnect (PI) 308A. The PI 308A may control what input signals are passed from the GPIO 304 and/or PRGIO 306 to the LP PASS 102. The LP PASS may additionally have a PI 308B as part of the LP PASS 302. In some implementations, the PI 308B can distribute incoming analog signals among different groups of analog circuits. For example, chemical and physical sensing inputs may be directed to MUX 310(1), while audio signals may be directed to MUX 310 (2). Signal routing within the LP PASS 302 may be accomplished by reference values provided by the areoute 314 and AREF 340 to the two sets of analog circuits. The logic 352 may be configured to receive digital inputs from some or all of the CTBs 320 and produce one or more digital output values. Some output values may be binary functions (0 or 1) of the input analog signal. For example, if the input contains a codeword, the input sound signal may result in a binary output of 1, and if the input does not contain a codeword, the input sound signal may result in a binary output of 0. Some output values may be multi-bit numbers, which may represent the input analog signal in a quasi-continuous manner. For example, the detected ambient temperature or the chemical composition of air or water may be represented by a quantity with significant resolution (accuracy). The PI 308B may be controlled by a logic circuit 352, and the logic circuit 352 may control how the input signals are distributed within the LP PASS 302 by reprogramming the PI 308B, as schematically illustrated by the dashed lines in FIG. 3. The LP PASS 302 may also have a power monitor 359 to control the power level of the LP PASS and the timing for powering up/down the various blocks of the LP PASS 302. The timing may include specific instances of power up/down (including full and partial drops in power) and the duration of power up/down transitions. The power monitor 359 may provide monitoring functionality to both the analog block of the LP PASS 302 and the digital processing block 350. The power monitor 359 may be controlled by the logic circuit 352 and/or the FSM 354. In some embodiments, power monitor 359 may have its own internal logic and be able to operate autonomously from logic circuit 352/FSM 354.

Logic circuit 352 or FSM 358 may determine whether one or more output values satisfy a first criterion. In some embodiments, the first criterion may be represented by a first threshold and the first criterion is met if the output value exceeds the first threshold. In some embodiments, the first criterion is met if the output value is below a first threshold. In this disclosure, the plural term "standard" is understood to encompass both its dictionary plural meaning and its associated singular meaning ("standard"). Thus, the term "first criterion" (or "second criterion", etc.) encompasses embodiments in which a single output value may be compared to a single threshold value, as well as embodiments in which multiple output values may be compared to multiple threshold values. Similarly, the singular term "threshold" should be understood to also cover embodiments having multiple thresholds.

The first threshold value may be stored in memory 354(1) or 354 (2). In some embodiments, the first threshold may be stored in register 356(1) or 356 (2). In some embodiments, the first threshold may be stored in the settings of FSM 358(1) or 358 (2). If it is determined that the first criterion is met, logic circuitry 352 and/or corresponding FSM 358 may reconfigure LP PASS 302 from a first PASS configuration to a second PASS configuration having different configuration settings. The configuration settings may include parameters that determine the functionality of the at least one programmable analog circuit, such as the clock rate of the CTB/DTB 320, the resolution and sample rate of the SAR ADC 330, the routing structure of the array 314, the analog reference of the array 340, and so forth. The setting(s) for the second PASS configuration may be stored in memory 354, register 356, or settings of FSM 358. In some embodiments, the registers 356 may be implemented in ROM, and the configuration settings stored therein may not be modified. In some embodiments, registers 356 may be RAM implemented and may be modified by CPU 362 of digital subsystem 360. In some embodiments, some configuration settings may be stored in RAM (memory 354 or registers 356) while other configuration settings may be stored in ROM (memory 354 or registers 356). In some embodiments, the configuration settings may be stored in the registers 356, while the data collected by the LP PASS 302 may be stored in the memory 354. In some implementations, the configuration settings may represent the state of one or more switches of one or more of the CTB/DTB 320, SAR ADC 330, arute 314, AREF 340, and so on.

When the LP PASS 302 is in the first configuration, the CPU 362 of the digital subsystem 360 may be in a CPU off state. The CPU may remain in the CPU OFF state while the LP PASS 302 is reconfigured to the second configuration. The LP PASS 302 may continue to receive and process analog input signals in the second configuration. Logic circuit 352 or FSM 358 may then determine that one or more output values in the second configuration satisfy the second criterion. For example, the output value of the logic circuit 352 may be above (or below) the first second threshold. If this occurs, the logic circuit 352 may output a wake-up signal to the CPU 362 via a digital interface (not shown) and trigger a transition of the CPU to a CPU ON state. In some embodiments, the wake-up signal may be an instruction for the CPU to wake up, e.g., a digital instruction. In other embodiments, the wake-up signal may be a data signal that does not contain instructions to the CPU 362, but causes the CPU 362 to wake-up. In the on state, the CPU 362 may load instructions from the memory 364 of the digital subsystem 360 and execute the digital code. As a result of the code execution, the CPU 362 may send configuration data with instructions to the LP PASS 302 (e.g., to the logic circuit 352 and/or to the FSM 358) to reconfigure the LP PASS to the third PASS configuration. In some embodiments, the settings for the third configuration may be retrieved from the LP PASS memory 354 or the register 356. In some implementations, the CPU 362 may first store the configuration settings into one or more RAM devices of the LP PASS 302 (e.g., to the memory 354 or the registers 356) and instruct the logic 352 to retrieve these stored settings. In some embodiments, the CPU 362 may directly modify the settings of the various analog blocks of the LP PASS 302 without involving the logic 352. In some embodiments, CPU 362 may load new configuration settings into memory 354 or registers 356 when some predetermined condition occurs. For example, when the LP PASS 102 detects smoke in the ambient air, the LP PASS 102 may output a wake-up signal to the CPU 362, and the CPU 362 may load new configuration settings to reconfigure the LP PASS 102 from the detection of smoke to the determination of its chemical composition. In some embodiments, CPU 362 may load new configuration settings into memory 354 or registers 356 independently of the input signals, simply as part of an update, e.g., a scheduled (at a particular time of day) update.

In some implementations, the LP PASS 302 in the second configuration may not receive the second analog input signal. Conversely, upon reconfiguration (and without waking the CPU 362), the LP PASS 302 may reprocess the first analog input signal stored during the initial processing performed in the first PASS configuration. For example, the first analog input signal may be stored in the sample/hold circuit 231 of the SAR ADC 330. After reconfiguring the LP PASS 302 to the second configuration (e.g., with a higher SAR ADC sampling rate), the reconfigured SAR ADC 330 and logic circuit 352 may process the stored input signal at a new (higher) resolution to determine a new output value. This new output value may then be compared to a second threshold value, and a decision may be made whether to wake up CPU 362 from its off state.

In some embodiments, after receiving and processing the analog input signal, the LP PASS 302 may output a signal to the CPU 362 that is different from the wake-up signal. In some embodiments, the signal output to the CPU 362 is a mode select signal. For example, in some embodiments, the CPU 362 may initially be in a CPU-on state and the logic 352 may output a signal to the CPU 362 to cause the CPU 362 to transition to a CPU-off state. In some embodiments, the mode select signal may cause the CPU 362 to transition between different active modes (states).

In some embodiments, the LP PASS 302 may not output a wake instruction to the CPU while undergoing multiple reconfigurations to a configuration with gradually upgraded functionality (e.g., speed, accuracy, and resolution) and power consumption before the CPU 362 eventually wakes up. For example, the sequence of the LP PASS state may be: sleep, active 1, active 2, active 3, followed by a wake-up instruction to CPU 362. In some implementations, if it is determined that active CPU involvement or input is not required, the LP PASS 302 may reverse and downgrade without waking the CPU 362: activity 1, activity 2, activity 3, activity 2, activity 1. In some embodiments, the LP PASS 302 may be demoted to a sleep (or deep sleep) state. In some embodiments, the LP PASS 302 may periodically reconfigure itself to one of the active states at the beginning of the monitoring time period and revert to the sleep (or deep sleep) state at the end of the period.

Digital subsystem 360 may be a general purpose processing system or a special purpose processing system configured to execute a limited number of instructions. In some embodiments, digital subsystem 360 may be a microcontroller unit (MCU). Digital subsystem 360 may include flash memory 366, direct memory access circuitry (DMA)368, and other conventional components such as monitors, IO devices, network adapters, and the like. The digital subsystem 360 may access cloud storage. Some or all of the computing performed by digital subsystem 360 may be remote (e.g., cloud) computing.

The system 300 may have a plurality of system-wide resources 370, such as an internal master oscillator 372 and a reference block 374, to provide voltage and current to components of the digital subsystem and, in some implementations, to the AREF 340. The system-wide resources may also include a phase-locked loop (PLL)376 to generate a phase-locked reference signal. The system 300 may also include a plurality of peripheral resources 380, which may include a capacitance sensing array 382, a watchdog timer 384, a serial communication block 386, a liquid crystal display 388, and a Timer Counter Pulse Width Modulator (TCPWM) 389.

In some embodiments, all components of system 300 may be implemented on the same chip (substrate), as shown by dashed-line rectangular low-power system-on-chip (SoC) 390. In some embodiments, some components of system 300 may be implemented off-chip. For example, some or all of peripheral resources 380 and/or IO subsystem 303 may be implemented off-chip and may be connected to the chip hosting LP PASS 302 and digital subsystem 360 by one or more buses (not shown). In some implementations, the LP PASS 302 and the digital subsystem 360 may be implemented as separate socs on different (e.g., Si) substrates.

Fig. 4 is a block diagram of one exemplary illustration 400 of processing input signals having various input levels by a reconfigurable low power programmable analog subsystem (LP PASS)402 integrated with a digital subsystem 460, in one possible implementation.

The LP PASS 402 may be a single set of devices as shown in FIG. 1, two sets of devices as shown in FIG. 3, or multiple sets of devices. Fig. 4 illustrates the functionality of the LP PASS 402 in two exemplary situations. In the first case, the input signal 401 has an input level above the first threshold criterion for reconfiguration of the LP PASS 402. However, the input level of the signal 401 may be below the second threshold criterion. As a result, the LP PASS 402 reconfigures itself, but does not output a signal to the CPU 462. In some embodiments, the term "input level" may refer to a voltage level, a current level, a level indicating a charge, or any other physical or chemical quantity or change in any physical or chemical quantity. In the second case, the input signal 403 has an input level that is higher than the second threshold criterion for outputting the signal to the CPU 462. Input signals 401 and/or 403 are first received by front-end interface 405. The front-end interface 405 may perform pre-processing of the input signals 401 and/or 403. For example, the front-end interface 405 may include a microphone to convert audio signals into electrical signals that may be recognized by the LP PASS analog circuitry, or may include a number of radio circuits and devices (antennas, amplifiers, filters, etc.) to convert radio waves into electrical signals. The front-end interface 405 may include any components of the IO subsystem 303 and the MUXs 310, 312. The signal pre-processed by front end interface 405 may be input to CTB/DTB 420 for continuous or discrete time processing and then to SAR ADC 430 for conversion to a digital value. The CTB/DTB 420 and/or SAR ADC 430 may initially have settings corresponding to the first LP PASS configuration. The signal digitized by SAR ADC 430 may be input to digital processing block 450, and more specifically may be input to logic circuit 452 and/or FSM 458. In some implementations, the logic 452 and/or FSM 458 may generate one or more output values and determine whether the output values satisfy one or more criteria, such as a first criterion for LP PASS 402 reconfiguration and a second criterion for outputting a signal to the CPU 462. If logic 452 and/or FSM 458 determine that the first criteria are met for input signal 401, but the second criteria are not met, logic 452 and/or FSM 458 may reconfigure LP PASS 402 to the second PASS configuration.

In some embodiments, the first criterion may include a plurality of metrics. The second PASS configuration may be selected from more than one possible configuration based on the application of the plurality of metrics to the one or more output values. In some embodiments, the reconfiguration of LP PASS 402 may be performed with the help of one or more of the preconfigured states of FSM 458 if some subset of the first criteria is met. FSM 458 may be used to facilitate fast reconfiguration of LP PASS 402. If any subset of the first criteria is not met such that the preconfigured state of FSM 458 is not selected, then the reconfiguration of LP PASS 402 may be performed by logic 452. In some implementations, the settings for the second configuration of the LP PASS 402 may be retrieved from the LP PASS storage 454. In some embodiments, the LP PASS memory 454 may include one or more ROM registers, such as the register 356 for storing configuration settings.

The settings for the selected second PASS configuration may be applied to the front-end interface 405, CTB/DTB 420, SAR ADC 430, and other LP PASS blocks (e.g., arote, AREF) not explicitly shown in fig. 4, as indicated by the open arrows. The LP PASS 402 may then process additional inputs. In some embodiments, the LP PASS 402 may first reprocess the original input signal (e.g., input signal 401) at an increased resolution. The input signal may be stored in one or more buffers of the LP PASS 402 (e.g., in the sample/hold buffer 231) for such subsequent processing.

When the super-threshold input 201 is processed by the LP PASS 402, the logic 452 and/or FSM 458 may determine that the output value(s) satisfy a second criterion. In response to determining that the second criterion is satisfied, the digital processing block may output a wake-up instruction to digital subsystem 460 via digital interface 455 to wake-up CPU 462 from its CPU-off state. In response to the signal from the LP PASS 102, the CPU 462 may transition to a CPU ON state. The wake-up instruction may contain an interrupt message describing the reason for the wake-up. CPU 462 may then load and execute the particular code (e.g., from memory 464) in response to the particular cause contained in the interrupt message. In some embodiments, the CPU 462 may output instructions to the LP PASS 402 to transition to the third PASS configuration. In some embodiments, the third PASS configuration may be used to implement one of the active LP PASS states. In other embodiments, the third PASS configuration may be used to implement a sleep or deep sleep state. In some embodiments, the CPU 462 may not output any reconfiguration instructions to the LP PASS 402, but the LP PASS 402 may configure itself to the third configuration according to one of the processes described above.

In some embodiments, the LP PASS 402 and the CPU 462 may be processing the same task, e.g., speech recognition, while the LP PASS 402 is in one of its active states and the CPU 462 is in its CPU on state. In other embodiments, the LP PASS 402 and the CPU 462 may be processing different tasks. For example, the LP PASS 402 may be monitoring air humidity while the CPU 462 is adjusting the heating system. As another example, the LP PASS 402 may be monitoring the brightness of natural light transmitted through a smart window while the CPU 462 is optimizing air conditioning parameters. When the current task has been completed, the CPU 462 may transition to a CPU OFF state and output further configuration instructions to the LP PASS 402. In some embodiments, the LP PASS may receive an indication that the CPU 462 has transitioned to a CPU off state and reconfigure itself to a default state (e.g., sleep or active 1) without CPU involvement or input.

In some embodiments, the signal output by the LP PASS 102 to the CPU 462 may be a wake-up instruction. In response to receiving such an instruction, CPU 462 may wake up from its CPU off state. In some embodiments, the output signal may be an interrupt signal to the CPU 462, and the CPU 462 may be in a CPU on state but processing other tasks (e.g., tasks unrelated to those performed by the LP PASS 402). In response to receiving the interrupt instruction, the CPU 462 may not change its state, but may interrupt the task it is currently executing and switch to a different task, e.g., reconfigure the LP PASS 402, as explained above. In some embodiments, the output signal may be a "sleep" signal to the CPU 462 to switch to a CPU off state. For example, such a signal may be output by the LP PASS 402 in response to the non-occurrence of a certain event within a predetermined time period.

Fig. 5a is a block diagram of an exemplary embodiment 500(a) of an application of a reconfigurable low power programmable analog subsystem (LP PASS) using radio reception and transmission. The illustrated embodiment may be used as part of an internet of things controller. The illustrated embodiments may be used as an interface with a cloud or other digital and/or analog devices using a local area network, a personal area network, or any other network and protocol based on radio reception and/or transmission. One or more antennas 501 may be used for reception and transmission of radio waves by a receiver 502 and a transmitter 504. In some embodiments, receiver 502 may use receiver antenna 501(R) while transmitter 504 may use a separate transmitter antenna 501 (T). In other embodiments, a single antenna may be used for both transmission and reception. For example, the antennas may be multiple-input and multiple-output (MIMO) antennas. The radio signal received through the antenna 501(R) may be fed to a receiver front end module (FEM-R)506 (R). The FEM-R506 (R) may include multiplexers, filters (e.g., bandpass filters), low noise radio frequency amplifiers, down-conversion mixer(s), frequency and/or amplitude shift keying modules, and other circuitry that may be used to process radio signals. In some implementations, the output of the FEM-R506 (R) can be processed by a decoder 508.

The output of the receiver 502 may be provided to the LP PASS 512. The LP PASS 512 may be any of the LP PASSs 102, 302, 402, etc. The LP PASS 512 may be in one of the low power states, as disclosed above. The LP PASS 512 is capable of reconfiguring itself and the FEM-R506 (R) in response to analog and digital processing of signals received by the antenna 501 (R). In some implementations, the LP PASS 512 is capable of transmitting radio signals via the transmitter 504 and the antenna 501 (T). The signal to be transmitted may be stored in the memory of the LP PASS 512 and selected by the FSM of the LP PASS 512 when the digital output of the LP PASS 512 meets one or more predetermined criteria. In some embodiments, the signal to be transmitted may be determined by logic circuitry of the LP PASS 512. The signal may be converted to analog form by a digital-to-analog converter (DAC) module 516. In some embodiments, the signal may be encoded by encoder 518 and provided to transmitter front end module FEM-T506 (T). The FEM-T506 (T) may include a multiplexer, a filter (e.g., a bandpass filter), a low noise radio frequency amplifier, down-conversion mixer(s), a frequency and/or amplitude shift keying module, and other circuitry.

The LP PASS 512 may be fabricated on the same chip (e.g., same Si substrate) with the digital subsystem 514, e.g., as a low power system on a chip (SoC) 516. In some implementations, the SoC 516 can be the SoC 390. Digital subsystem 514 may include a CPU, memory, and a digital interface. In some implementations, the digital subsystem 514 may be an MCU. During the radio signal processing described above, the digital subsystem 514 may be in a CPU off state. In some embodiments, the digital subsystem 514 may take over radio reception and/or radio transmission when the digital output of the LP PASS 512 meets one or more criteria for waking up the CPU. The digital subsystem 514 may also reconfigure the LP PASS 512 as described above with reference to fig. 3 and 4.

In some implementations, the receiver 502 and the transmitter 504 can be mounted on the same chip (e.g., the transceiver SoC 520). In some implementations, the transceiver SoC 520 can be an internet of things (IoT) chip. In some embodiments, the receiver 502, the transmitter 504, and the LP PASS 512 may be mounted on the same chip. In some embodiments, the receiver 502 and the transmitter 504 may share some components. For example, the FEM-R506 (R) and FEM-T506 (T) may share filters, amplifiers, and/or other components, or may be implemented as a single module. In some embodiments, the receiver 502, the transmitter 504, and the LP PASS 512 may be mounted on the same chip. In some embodiments, the receiver 502, the transmitter 504, the LP PASS 512, and the digital subsystem 514 may be mounted on the same chip. In some implementations, one or more network adapters may be used in place of receiver 502 and transmitter 504, and data streams (e.g., to/from a network, cloud) may be used in place of radio reception/transmission.

FIG. 5b is a block diagram of one exemplary implementation 500b of an application of a reconfigurable low-power programmable analog subsystem for speech recognition. Embodiment 500b may be used (including but not limited to) in the context of wearable devices, internet of things, automobiles, or general applications. In the exemplary diagram of fig. 5b, the sound signal may be detected by the microphone 530 and transmitted through the analog interface 540 to the low power adaptive sensing system 550, which may include the LP PASS 552 and a digital subsystem 554. In one exemplary embodiment, the low power adaptive sensing system 550 may be used in noisy environments to help detect and discriminate human speech. Digital subsystem 554 may have a CPU that may be in a CPU off state when active voice is not currently detected. In some embodiments, the LP PASS 552 may be in one of the active states, or in one of the sleep or deep sleep states. For example, the LP PASS 552 in the sleep state may have its logic circuits turned off and its SAR ADC configured with minimum resolution (e.g., 8 bits 1ksps) and lowest sampling rate. The LP PASS 552 may reconfigure itself to one of the active states upon detection of a particular event, for example, upon detection of a signature of human speech. For example, the FSM of the LP PASS 552 may respond to a signature of human speech and transition the LP PASS 552 to one of the active states. In one illustrative, non-limiting embodiment, in the new configuration, the logic of the LP PASS 552 may be awakened and the digital resolution and sample rate of the SAR ADC may be increased to, for example, 16 bits 44.1 ksps. In this new state, the LP PASS 552 may continue to monitor the input audio signal passed through the analog interface 540 for additional signatures of human speech. If no voice is detected, the LP PASS 552 may revert to a default mode (e.g., 8-bit 1ksps) after a predetermined amount of time has elapsed.

However, if more speech is detected, the LP PASS 552 may wake up the CPU of the digital subsystem 554. The CPU may further reconfigure the LP PASS 552 and/or the analog interface 540 and begin outputting detected speech to the speech recognition system 570 via the digital interface 560. In some implementations, the digital subsystem 554 may be absent, and when a positive determination has been made that speech is detected, the LP PASS 552 may wake the speech recognition system 570 and output an (digitized) audio signal through the interface 560.

In some embodiments, microphone 530 may be replaced with a radio front end or network adapter or any other device capable of communicating audio signals. In some embodiments, the analog interface 540 and the digital interface 560 may be mounted on the same chip as the LP PASS 552.

FIG. 6 is a timing diagram 600 showing relative power levels for various exemplary states of two subsystems, including different states of a reconfigurable low-power programmable analog subsystem and a digital subsystem including a Central Processing Unit (CPU), in one illustrative embodiment. Fig. 6 may qualitatively illustrate the power level of any of the systems shown in fig. 3, 4, 5a and 5b, as applicable. The above figure shows the power level of a digital subsystem in a conceptual form, but not in a limiting manner, which power level depends on its CPU state. The following diagram illustrates, in conceptual form and not by way of limitation, the power level of the LP PASS, which depends on the state of the LP PASS, which may depend on the configuration of its blocks. Time T1 qualitatively illustrates the time for the CPU wake 612 for the CPU (or the entire digital subsystem) to transition from the CPU off state to the CPU on state. Time T2 qualitatively illustrates the time of LP PASS wake-up 622 for the LP PASS to transition from LP PASS sleep to one of the LP PASS active states. As shown in fig. 6, time T2 may be significantly shorter than time T1. Furthermore, the power consumption of the digital subsystem in the CPU on state may be significantly greater than the power consumption in one of the LP PASS active states (or configuration modes), as highly schematically depicted in the two figures.

The LP PASS may be reconfigured into one of the active states, e.g., active 1, active 2, active 3, etc., based on a triggering event that wakes up the LP PASS. Without a triggering event, the LP PASS may transition to one of the active states at specified intervals (by changing the configuration of one or more blocks) according to a wake-up schedule. For example, the LP PASS may transition from the LP PASS sleep state to the LP PASS active 1 state every 1 second, and the LP PASS may transition from the LP PASS sleep state to the LP PASS active 2 state every 10 seconds. The various LP PASS states may differ in LP PASS function and power consumption. In some instances, waking up the LP PASS may follow (and be caused by) waking up the digital subsystem.

In other embodiments, the length of the time interval may be much shorter. For example, in one embodiment, the period of the duty cycle of the LP PASS may be 50 μ s, with the first 44 μ s of each cycle spent in the LP PASS sleep state and the next 6 μ s spent in the LP PASS active 1 state. In the sleep state, the LP PASS may be in an ultra-low power state waiting for a wake-up interrupt. In the active 1 state, the LP PASS may activate an analog front end (e.g., CTB), where the SAR ADC is configured to perform a single conversion, store the result in the LP PASS memory, and compare it to either the LP PASS reconfiguration criteria or the CPU wake-up criteria. Once every N cycles (e.g., N-10), the LP PASS may be reconfigured to an active 2 (or active 3) state with the higher (or final) functionality of the LP PASS circuit. The LP PASS may remain in this state for 20 mus (or any other predetermined time) and then revert to the sleep state.

Fig. 6 shows a number of different possibilities by way of example. Before the timeline begins, the CPU (or the entire digital subsystem) is in the OFF state, and the LP PASS is in the sleep state. At the beginning of the indicated timeline, the CPU wakes up and undergoes a transition to the ON state 614. This transition 612 may be caused by a user, by an external event (e.g., a wake up call received over a network), or may occur according to a wake up schedule. After the CPU wakes 612, the CPU may send a wake call 622 to the LP PASS and reconfigure the LP PASS to one of its active states 624 (active 2), as shown. Upon completion of the processing task, the CPU may reconfigure the LP PASS back to the LP PASS sleep state 626. Subsequently, the CPU itself undergoes a transition to the CPU off state 616. With the CPU in the off state, the LP PASS may undergo a series of transitions to one or more of its active states. They are shown in fig. 6 as the LP PASS active 1628 state. Some of these states may be performed as disclosed above. For example, the LP PASS may monitor external analog inputs, generate digital outputs, and compare the digital outputs to one or more criteria (e.g., thresholds) to determine whether to reconfigure the LP PASS. Some reconfiguration may occur after a predetermined time interval has elapsed in the event that the output value does not meet the reconfiguration criteria. After the LP PASS has completed the necessary tasks (e.g., voice monitoring or adjusting heating/air conditioning settings) during its throttling 628, the LP PASS may return to the LP PASS sleep state 626. In some instances, the output value may cause a criterion for reconfiguring the LP PASS to a third state (e.g., LP PASS activity 3630) to be satisfied. In addition to reconfiguring itself to active 3, the LP PASS may also send a wake-up instruction to the CPU (as shown in FIG. 6) and cause it to transition to the CPU ON state 614. The examples shown in fig. 6 are not exhaustive, as many other combinations and scenarios are possible. For example, in addition to the two CPU states (CPU on and PCU off), other additional states of the digital subsystem are possible, which may differ in terms of the level of CPU functionality and power consumption. The drawings of fig. 6 are illustrative and not to be construed as limiting. For example, although the power consumption in the three LP PASS states are shown at the same level, this is not generally necessary and the various LP PASS states may be characterized by different power consumption levels.

FIG. 7 is a flow diagram of one possible embodiment of a method 700 of reconfiguring a low-power programmable analog subsystem in response to an input signal. Method 700 may be performed by logic circuitry and/or a FSM of the LP PASS that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software, firmware, or a combination thereof. The LP PASS may be one of the LP PASS 102, 302, 402, 512, or 552. The logic circuit may be one of the logic circuits 152, 352, or 452. The FSM may be one of FSMs 158, 358, or 458. Method 700 may include receiving, by a PASS coupled to an IO device, a first input signal from the IO device, the PASS having a plurality of reconfigurable analog circuits and an interface for communicating data with a CPU (710). The IO device may be any device capable of inputting analog signals, including one or more pins, switches, or sensors. In some embodiments, the IO devices may include radio front end processing, coaxial cable, fiber optic, and the like.

The method 700 may continue with processing the first input signal with the PASS in the first PASS configuration with the plurality of reconfigurable analog circuits having the first configuration setting in the first PASS configuration (720). The reconfigurable PASS circuit may include some or all of the circuits shown in fig. 1-4, such as CTB, SAR ADC, areute, AREF, multiple multiplexers, and the like. Method 700 may continue with generating a first output value based on the first input signal (730). For example, the SAR ADC may provide a digital input to the logic circuit and/or FSM of the PASS. The logic circuit and/or FSM may generate a first digital output value that may represent an analog input to the PASS. The method 700 may continue with reconfiguring the plurality of reconfigurable analog circuits to a second PASS configuration having second configuration settings, wherein the second configuration settings are different from the first configuration settings (740). Reconfiguration of the second PASS configuration may be performed in response to the first output value. PASS may maintain a correspondence between various output values and PASS configurations selected in response to particular output values. In some implementations, the correspondence may be an index stored in one or more registers (e.g., ROM-based registers) of the PASS and/or stored in one or more memory devices (e.g., RAM) of the PASS. In some embodiments, the correspondence may reference one or more thresholds stored by the PASS. In some embodiments, if the first output value is greater than the threshold, the PASS configuration will be selected. In some embodiments, if the first output value is less than the threshold, the PASS configuration will be selected. In some embodiments, the correspondence is encoded in the circuitry of the FSM.

In some embodiments, reconfiguring the plurality of reconfigurable analog circuits to the second PASS configuration may be performed by selecting one of the FSM states. In some embodiments, the settings for some or all of the analog circuits of the PASS may be obtained based on the selected FSM state. In some embodiments, the provision of some or all of the analog circuitry for the PASS may be provided by logic circuitry of the PASS. In some embodiments, settings for some of the analog circuits of the PASS may be provided by the FSM, while settings for other analog circuits may be provided by the logic circuit. In some embodiments, the settings for some analog circuits may remain the same between two or more different PASS configurations.

FIG. 8 is a flow diagram of one possible embodiment of a method 800 of reconfiguring a low-power programmable analog subsystem integrated with a digital subsystem in response to an input signal. Method 800 may be performed by the same devices and circuits described above with respect to method 700. Method 800 may include receiving, by a PASS coupled to an IO device, a first input signal from the IO device (810). The PASS may have a plurality of reconfigurable analog circuits and an interface for communicating data with the CPU. The method 800 may continue with processing the first input signal with the plurality of reconfigurable analog circuits with the PASS in the first PASS configuration (820). The method 800 may continue with generating a first output value based on the first input signal (830). In some embodiments, blocks 810-830 may be the same as blocks 710-730 of method 700.

The method 800 may continue with a decision block in which it may be determined whether the first output value satisfies a first threshold criterion (835). For example, whether the carbon monoxide concentration has reached a detectable level may be determined by the logic circuit and/or the FSM. If the first threshold criteria is not met, the PASS may remain in the first PASS configuration (840). However, if it is determined that the first threshold criteria are met, the method 800 may continue with determining whether the second threshold criteria are met (845). For example, at block 845, it may be determined whether the carbon monoxide concentration has reached a dangerous level. If the second threshold criteria is not met, the method 800 may continue with reconfiguring the plurality of reconfigurable analog circuits to a second PASS configuration having a second configuration setting (850). In some embodiments, block 850 may be performed similarly to block 740 of method 700. For example, the first configuration may be used to implement the LP PASS sleep state and the second configuration may be used to implement the LP PASS active 1 state. In other examples, the first configuration may be used to implement the LP PASS active 1 state and the second configuration may be used to implement the LP PASS active 2 state. The method 800 may continue with the LP PASS receiving a subsequent (e.g., second) input signal from the IO device. In some embodiments, the second input signal may be the same as the first input signal, but stored by one or more analog circuits for subsequent reprocessing by the PASS in the second configuration (which may have higher resolution and/or processing accuracy).

The method 800 may continue processing the second input signal with the plurality of reconfigurable analog circuits with the PASS in the second PASS configuration (870) and continue generating a second output value based on the second input signal (880). The actions in blocks 870-880 may be performed similar to the actions in blocks 810-830. The method may then loop back to decision block 845 and compare the second output again to the second threshold criteria. In the event that the second threshold criteria has not been met, the method may continue to maintain PASS in the second configuration and repeat blocks 850-880 and 845 as needed. In the event that the second threshold criteria have been met, method 800 may continue with outputting a signal (e.g., a wake-up or interrupt instruction in some embodiments) (890) to the CPU via an interface (e.g., digital interface 455). If it is determined that both the first criteria (block 835) and the second criteria (block 845) are satisfied while the PASS is still in the first PASS configuration, the method 800 may continue to wake the CPU (890) and also (as shown by the dashed line) reconfigure the PASS to the second PASS configuration. In some embodiments, this action may be optional, and method 800 may end when the CPU takes over processing of the input signal.

It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. Although the present disclosure describes specific examples, it will be appreciated that the systems and methods of the present disclosure are not limited to the examples described herein, but may be practiced with modification within the scope of the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. The scope of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

The embodiments of methods, hardware, software, firmware, or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium which are executable by a processing element. "memory" includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine (e.g., a computer or electronic system). For example, "memory" includes Random Access Memory (RAM), such as static RAM (sram) or dynamic RAM (dram); a ROM; a magnetic or optical storage medium; a flash memory device; an electrical storage device; an optical storage device; acoustic storage devices, and any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

In the foregoing specification, specific embodiments have been given with reference to specific exemplary embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. Moreover, the foregoing use of embodiment, embodiment and/or other exemplarily language does not necessarily refer to the same embodiment or the same example, but may refer to different and distinct embodiments, as well as potentially the same embodiment.

The word "example" or "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the word "example" or "exemplary" is intended to present concepts in a concrete fashion. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X comprises a or B" is intended to mean any of the natural inclusive permutations. That is, if X comprises A; x comprises B; or X includes both A and B, then "X includes A or B" is satisfied under any of the foregoing circumstances. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Furthermore, unless so described, the use of the term "implementation" or "one implementation" or "an implementation" or "one implementation" throughout is not intended to mean the same implementation or implementation. Furthermore, the terms "first," "second," "third," "fourth," and the like as used herein are intended as labels to distinguish between different elements and may not necessarily have the ordinal meaning specified by their numbers.