阅读说明：本技术 一种提高逻辑输入端口耐压的保护电路 (Protection circuit for improving withstand voltage of logic input port ) 是由 王欢 于翔 谢程益 其他发明人请求不公开姓名 于 2019-10-21 设计创作，主要内容包括：一种提高逻辑输入端口耐压的保护电路,通过围绕被保护逻辑端口电路设置源端电压提高电路和高电压检测电路以及电压转换逻辑电路的组合,能够在输入端口电压高于端口器件耐压时提高被保护逻辑端口电路的源端电压,以使所述输入端口电压与所述源端电压的电压差小于端口器件耐压值,从而实现对逻辑输入端口的保护,防止因端口输入电压超过器件耐压引起的端口损伤。(A source end voltage of the protected logic port circuit can be increased when the voltage of the input port is higher than the withstand voltage of a port device, so that the voltage difference between the voltage of the input port and the source end voltage is smaller than the withstand voltage value of the port device, the protection circuit for the logic input port is protected, and port damage caused by the fact that the input voltage of the port exceeds the withstand voltage of the device is prevented.)

1. A protection circuit for improving the withstand voltage of a logic input port is characterized by comprising a high-voltage detection circuit, wherein the input end of the high-voltage detection circuit is connected with the input port of a protected logic port circuit, the output end of the high-voltage detection circuit is connected with a source end voltage improving circuit through a first node, the source end voltage improving circuit is connected with the protected logic port circuit through a third node, the protected logic port circuit is connected with a voltage conversion logic circuit through a second node, and the voltage conversion logic circuit is respectively connected with an internal output port and the source end voltage improving circuit.

2. The protection circuit of claim 1, wherein the high voltage detection circuit comprises a first PMOS transistor and a second PMOS transistor interconnected by gates, the source of the first PMOS transistor is connected to a power voltage terminal, the gate-drain of the first PMOS transistor is connected to a ground terminal through a fourth current source, the source of the second PMOS transistor is connected to the input port, the drain of the second PMOS transistor is connected to the source of the third PMOS transistor, the gate-drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the gate-drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor, the gate-drain of the fifth PMOS transistor is connected to the drain of the ninth NMOS transistor, the gate of the ninth NMOS transistor is connected to the gate of the eighth NMOS transistor, the gate-drain of the eighth NMOS transistor is connected to the power voltage terminal through the third current source, the source of the eighth NMOS transistor and the source of the ninth NMOS are both connected to the ground terminal, the drain electrode of the ninth NMOS tube is respectively connected with the grid electrode of the first NMOS tube and the grid electrode of the ninth PMOS tube, the source electrode of the ninth PMOS tube is connected with the power supply voltage end through the second current source, the source electrode of the first NMOS tube is connected with the grounding end, and the drain electrode of the first NMOS tube and the drain electrode of the ninth PMOS tube are both connected with the first node.

3. The protection circuit for improving the withstand voltage of the logic input port according to claim 1, wherein the protected logic port circuit comprises an eleventh PMOS transistor and an eleventh NMOS transistor, the gate electrode of the eleventh PMOS transistor and the drain electrode of the eleventh NMOS transistor are interconnected, the source electrode of the eleventh PMOS transistor is connected to the supply voltage terminal, the source electrode of the eleventh NMOS transistor is connected to the third node, the gate electrode of the eleventh NMOS transistor is connected to the input port, and the drain electrode of the eleventh PMOS transistor is connected to the second node.

4. The protection circuit of claim 1, wherein the source end voltage boosting circuit comprises a second NMOS transistor, a gate of the second NMOS transistor is connected to the first node, a drain of the second NMOS transistor is connected to the third node, a gate and a drain of a fourth NMOS transistor, respectively, a source of the fourth NMOS transistor is connected to a gate and a drain of a third NMOS transistor, respectively, and a source of the second NMOS transistor and a source of the third NMOS transistor are both connected to a ground terminal.

5. The protection circuit for improving the withstand voltage of the logic input port according to claim 1, the voltage conversion logic circuit comprises an eighth PMOS tube and a seventh NMOS tube which are interconnected by a grid electrode and a drain electrode, the source electrode of the eighth PMOS tube is connected with a power supply voltage end, the drain electrode of the eighth PMOS tube is connected with the internal output port, the source electrode of the seventh NMOS tube is connected with the ground terminal, the grid electrode of the eighth PMOS tube is respectively connected with the drain electrode of the seventh PMOS tube, the drain electrode of the sixth NMOS tube and the drain electrode of the sixth PMOS tube, the source electrode of the sixth PMOS tube and the source electrode of the seventh PMOS tube are both connected with a power supply voltage end, the seventh PMOS tube and the sixth NMOS tube are connected with the first node after being interconnected, the source electrode of the sixth NMOS transistor is connected with the drain electrode of the fifth NMOS transistor, the source electrode of the fifth NMOS transistor is connected with the ground terminal, and the grid electrodes of the sixth PMOS tube and the fifth NMOS tube are connected with the second node after being interconnected.

6. The protection circuit for improving the withstand voltage of the logic input port according to claim 1, wherein when the high voltage detection circuit detects that the voltage of the input port is not higher than the withstand voltage of the port device in the protected logic port circuit, the first node is a power supply voltage value, the source end voltage improvement circuit is inactive, that is, the third node is at the ground potential, and the internal output port and the input port have a preset corresponding logic high-low level relationship.

7. The protection circuit of claim 1, wherein when the high voltage detection circuit detects that the voltage of the input port is higher than a voltage withstanding value of a port device in the protected logic port circuit, a first node is at ground potential, the source end voltage boosting circuit boosts the voltage of the third node so that a voltage difference between the input port and the third node is smaller than the voltage withstanding value of the port device to protect the logic input port, a second node and the third node have the same potential, the voltage conversion logic circuit performs voltage conversion according to the input terminal as a power voltage value, and the internal output port and the input port have a preset corresponding logic high-low level relationship.

Technical Field

The invention relates to a voltage withstanding technology of a logic input port, in particular to a protection circuit for improving the voltage withstanding of the logic input port.

Background

In the application of a chip circuit, a front-stage chip circuit and a rear-stage chip circuit are connected through a port, and due to the influence of factors such as different power domains, the input voltage input from the output end of the front-stage chip circuit to the input port of the rear-stage chip circuit may be higher than the withstand voltage value which can be borne by a chip process, so that the chip port is damaged. For this reason, there is a solution to use high-withstand-voltage devices, such as a high-withstand-voltage input port PMOS device and a high-withstand-voltage input port NMOS device, which increases the process cost. Some methods adopt a pair of port voltage clamping, for example, a resistor is connected between an input port VIN and an interconnection grid (grid interconnection of an input port PMOS device and an input port NMOS device), a voltage stabilizing diode is connected between the interconnection grid and a source end of a protected logic port circuit, the interconnection grid is connected with a cathode of the voltage stabilizing diode, the source end, namely a source electrode of an input port NMOS device, is connected with an anode of the voltage stabilizing diode, a drain electrode of the input port PMOS device and a drain electrode of the input port NMOS device are interconnected to form an internal logic output end VOUT, and the source electrode of the input port NMOS device is connected with a ground end GND. However, this method requires a sufficiently high driving capability of the front-end chip circuit and increases the power consumption of the entire system (a large current flows from the front-end chip circuit to the ground via the input port, the resistor, and the zener diode). The inventor believes that if a combination of a source end voltage boosting circuit, a high voltage detection circuit and a voltage conversion logic circuit is arranged around a protected logic port circuit, the source end voltage of the protected logic port circuit can be boosted when the input port voltage is higher than the withstand voltage of a port device, so that the voltage difference between the input port voltage and the source end voltage is smaller than the withstand voltage value of the port device, the protection of a logic input port is realized, and port damage caused by the fact that the input port voltage exceeds the withstand voltage of the device is prevented. In view of the above, the present inventors have completed the present invention.

Disclosure of Invention

Aiming at the defects or shortcomings in the prior art, the invention provides a protection circuit for improving the withstand voltage of a logic input port, and the combination of a source end voltage improving circuit, a high voltage detection circuit and a voltage conversion logic circuit is arranged around a protected logic port circuit, so that the source end voltage of the protected logic port circuit can be improved when the voltage of the input port is higher than the withstand voltage of a port device, and the voltage difference between the voltage of the input port and the source end voltage is smaller than the withstand voltage value of the port device, thereby realizing the protection of the logic input port and preventing the port damage caused by the port input voltage exceeding the withstand voltage of the device.

The technical scheme of the invention is as follows:

a protection circuit for improving the withstand voltage of a logic input port is characterized by comprising a high-voltage detection circuit, wherein the input end of the high-voltage detection circuit is connected with the input port of a protected logic port circuit, the output end of the high-voltage detection circuit is connected with a source end voltage improving circuit through a first node, the source end voltage improving circuit is connected with the protected logic port circuit through a third node, the protected logic port circuit is connected with a voltage conversion logic circuit through a second node, and the voltage conversion logic circuit is respectively connected with an internal output port and the source end voltage improving circuit.

The high voltage detection circuit comprises a first PMOS tube and a second PMOS tube, the grid electrodes of which are interconnected, the source electrode of the first PMOS tube is connected with a power supply voltage end, the grid drains of the first PMOS tube are interconnected and then connected with a grounding end through a fourth current source, the source electrode of the second PMOS tube is connected with the input port, the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube, the grid drains of the third PMOS tube are interconnected and then connected with the source electrode of the fourth PMOS tube, the grid drains of the fourth PMOS tube are interconnected and then connected with the source electrode of the fifth PMOS tube, the grid drains of the fifth PMOS tube are interconnected and then connected with the drain electrode of a ninth NMOS tube, the grid electrode of the ninth NMOS tube is connected with the grid electrode of an eighth NMOS tube, the grid electrodes of the eighth NMOS tube and the fourth NMOS tube are interconnected and then connected with the power supply voltage end through a third current source, the source electrode of the eighth NMOS tube and the source electrode of the ninth NMOS tube are both connected with the grounding end, and the drain electrode of the ninth, the source electrode of the ninth PMOS tube is connected with a power supply voltage end through a second current source, the source electrode of the first NMOS tube is connected with a grounding end, and the drain electrode of the first NMOS tube and the drain electrode of the ninth PMOS tube are both connected with the first node.

The protected logic port circuit comprises an eleventh PMOS tube and an eleventh NMOS tube, wherein the grid electrode of the eleventh PMOS tube and the drain electrode of the eleventh NMOS tube are interconnected, the source electrode of the eleventh PMOS tube is connected with a power supply voltage end, the source electrode of the eleventh NMOS tube is connected with the third node, the grid electrode of the eleventh NMOS tube is connected with the input port, and the drain electrode of the eleventh PMOS tube is connected with the second node.

The source end voltage improving circuit comprises a second NMOS tube, a grid electrode of the second NMOS tube is connected with the first node, a drain electrode of the second NMOS tube is respectively connected with the third node, a grid electrode and a drain electrode of a fourth NMOS tube, a source electrode of the fourth NMOS tube is respectively connected with a grid electrode and a drain electrode of a third NMOS tube, and the source electrode of the second NMOS tube and the source electrode of the third NMOS tube are both connected with a grounding end.

The voltage conversion logic circuit comprises an eighth PMOS tube and a seventh NMOS tube, wherein the grid electrode of the eighth PMOS tube is connected with the drain electrode of the seventh PMOS tube, the drain electrode of the eighth PMOS tube is connected with the internal output port, the source electrode of the seventh NMOS tube is connected with the grounding terminal, the grid electrode of the eighth PMOS tube is respectively connected with the drain electrode of the seventh PMOS tube, the drain electrode of the sixth NMOS tube and the drain electrode of the sixth PMOS tube, the source electrode of the sixth PMOS tube and the source electrode of the seventh PMOS tube are both connected with the power voltage terminal, the seventh PMOS tube is connected with the first node after being interconnected with the grid electrode of the sixth NMOS tube, the source electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is connected with the grounding terminal, and the sixth PMOS tube is connected with the second node after being interconnected with the grid electrode of the fifth NMOS tube.

When the high-voltage detection circuit detects that the voltage of the input port is not higher than the withstand voltage value of a port device in the protected logic port circuit, the first node is a power supply voltage value, the source-end voltage raising circuit does not work, namely the third node is at the ground potential, and the internal output port and the input port are in a preset corresponding logic high-low level relation.

When the high-voltage detection circuit detects that the voltage of the input port is higher than the withstand voltage value of a port device in the protected logic port circuit, the first node is at the ground potential, the source-end voltage boosting circuit boosts the voltage of the third node to enable the voltage difference between the input port and the third node to be smaller than the withstand voltage value of the port device so as to protect the logic input port, the potentials of the second node and the third node are the same, the voltage conversion logic circuit performs voltage conversion according to the input end as the voltage value of the power supply, and the internal output port and the input port are in a preset corresponding logic high-low level relation.

The invention has the following technical effects: the invention relates to a protection circuit for improving the withstand voltage of a logic input port, which is characterized in that a source end voltage improving circuit, a high voltage detection circuit and a voltage conversion logic circuit are arranged around a protected logic port circuit, when the voltage of the input port is higher than the withstand voltage of a port device, the protection circuit is started to improve the source end voltage of the protected logic port circuit, so that the VGS of an NMOS (input port NMOS device, namely MN11) in the protected logic port circuit is not more than the withstand voltage of the device, then the voltage conversion logic circuit is utilized to carry out logic voltage conversion, the signal finally output to other circuits in the protected logic port circuit is ensured to be 0 or the chip voltage VDD, the port damage caused by the fact that the input voltage of the port exceeds the withstand voltage of the device is effectively prevented, and meanwhile, the working voltage of each logic device in a chip is also.

Drawings

Fig. 1 is a schematic diagram of a protection circuit for improving the withstand voltage of a logic input port according to the present invention.

Fig. 2 is a schematic diagram of the specific circuit structure of fig. 1.

The reference numbers are listed below: VIN — input voltage or input port (the input port of the post-chip circuit receiving the output voltage of the pre-chip circuit or the input port of the protected logic port circuit, VIN may exceed the withstand voltage of the port devices MP11 and MN11 to cause damage to the chip port, i.e. the input port); VOUT-output voltage or internal output port; 101-protected logical port circuitry; 102-high voltage detection circuit; 103-source end voltage raising circuit; 104-voltage conversion logic; VDD-supply voltage or supply voltage terminal; GND-ground; a-a first node; b-second node (protected logical port circuit output node); s-third node (source end of protected logical port circuit); i1 — first bias current; i2 — a second limiting current or second current source; i3 — a third current source; MP 0-MP 8-the first PMOS tube to the ninth PMOS tube; MN 1-MN 9-the first NMOS transistor to the ninth NMOS transistor; MP 11-eleventh PMOS transistor (input port PMOS device); MN11 — eleventh NMOS transistor (input port NMOS device).

Detailed Description

The invention is described below with reference to the accompanying drawings (fig. 1-2).

Fig. 1 is a schematic diagram of a protection circuit for improving the withstand voltage of a logic input port according to the present invention. Fig. 2 is a schematic diagram of the specific circuit structure of fig. 1. As shown in fig. 1 to fig. 2, a protection circuit for improving withstand voltage of a logic input port includes a high voltage detection circuit 102, an input end of the high voltage detection circuit 102 is connected to an input port VIN of a protected logic port circuit 101, an output end of the high voltage detection circuit 102 is connected to a source terminal voltage boosting circuit 103 through a first node a, the source terminal voltage boosting circuit 103 is connected to the protected logic port circuit 101 through a third node S, the protected logic port circuit 101 is connected to a voltage conversion logic circuit 104 through a second node B, and the voltage conversion logic circuit 104 is respectively connected to an internal output port VOUT and the source terminal voltage boosting circuit 103. The high voltage detection circuit 102 includes a first PMOS transistor MP0 and a second PMOS transistor MP1 whose gates are interconnected, a source of the first PMOS transistor MP0 is connected to a power supply voltage terminal VDD, a gate-drain of the first PMOS transistor MP0 is connected to a ground terminal GND through a fourth current source I4 after being interconnected, a source of the second PMOS transistor MP1 is connected to the input port VIN, a drain of the second PMOS transistor MP1 is connected to a source of a third PMOS transistor MP2, a gate-drain of the third PMOS transistor MP2 is connected to a source of a fourth PMOS transistor MP3 after being interconnected, a gate-drain of the fourth PMOS transistor MP3 is connected to a source of a fifth PMOS transistor 4 after being interconnected, a gate-drain of the fifth PMOS transistor MP4 is connected to a drain of a ninth NMOS transistor MN9 after being interconnected, a gate of the ninth NMOS transistor MN9 is connected to a gate of an eighth NMOS transistor MN8, a gate-drain of the eighth NMOS transistor MN 366 is connected to a power supply voltage terminal MN3 after being interconnected, and a source terminal of the eighth NMOS transistor MN8 and a source of the ninth NMOS 8, the drain electrode of the ninth NMOS transistor MN9 is connected to the gate electrode of the first NMOS transistor MN1 and the gate electrode of the ninth PMOS transistor MN9, the source electrode of the ninth PMOS transistor MN9 is connected to the power supply voltage terminal VDD through the second current source I2, the source electrode of the first NMOS transistor MN1 is connected to the ground terminal GND, and the drain electrode of the first NMOS transistor MN1 and the drain electrode of the ninth PMOS transistor MN9 are both connected to the first node a. The protected logic port circuit 101 includes an eleventh PMOS transistor MP11 and an eleventh NMOS transistor MN11, where the gate and the drain of the eleventh PMOS transistor MP11 are interconnected, the source of the eleventh PMOS transistor MP11 is connected to the power supply voltage terminal VDD, the source of the eleventh NMOS transistor MN11 is connected to the third node S, the gate of the eleventh NMOS transistor MN11 is connected to the input port VIN, and the drain of the eleventh PMOS transistor MP11 is connected to the second node B.

The source end voltage boosting circuit 103 comprises a second NMOS transistor MN2, a gate of the second NMOS transistor MN2 is connected to the first node a, a drain of the second NMOS transistor MN2 is connected to the third node S and a gate and a drain of a fourth NMOS transistor MN4, a source of the fourth NMOS transistor MN4 is connected to a gate and a drain of a third NMOS transistor MN3, and a source of the second NMOS transistor MN2 and a source of the third NMOS transistor MN3 are both connected to a ground GND. The voltage conversion logic circuit 104 comprises an eighth PMOS transistor MP7 and a seventh NMOS transistor MN7 with gate interconnection and drain interconnection, the source of the eighth PMOS transistor MP7 is connected to the supply voltage terminal VDD, the drain of the eighth PMOS transistor MP7 is connected to the internal output port VOUT, the source of the seventh NMOS transistor MN7 is connected to the ground GND, the gate of the eighth PMOS transistor MP7 is connected to the drain of the seventh PMOS transistor MP6, the drain of the sixth NMOS transistor MN6 and the drain of the sixth PMOS transistor MP5, the source electrode of the sixth PMOS transistor MP5 and the source electrode of the seventh PMOS transistor MP6 are both connected to a power supply voltage terminal VDD, the seventh PMOS transistor MP6 and the sixth NMOS transistor MN6 are connected to the first node a after being interconnected, the source electrode of the sixth NMOS transistor MN6 is connected to the drain electrode of the fifth NMOS transistor MN5, the source of the fifth NMOS transistor MN5 is connected to the ground GND, and the gates of the sixth PMOS transistor MP5 and the fifth NMOS transistor MN5 are connected to the second node B. When the high voltage detection circuit 102 detects that the voltage of the input port VIN is not higher than the withstand voltage of the port device in the protected logic port circuit 101, the first node a is the power voltage value VDD, the source-side voltage boosting circuit 103 does not function, that is, the third node S is at the ground potential, and the internal output port VOUT and the input port VIN have a preset corresponding logic high-low level relationship. When the high voltage detection circuit 102 detects that the voltage of the input port VIN is higher than the withstand voltage value of the port device in the protected logic port circuit 101, the first node a is a ground potential, the source-end voltage increasing circuit 103 increases the voltage of the third node S, so that the voltage difference between the input port VIN and the third node S is smaller than the withstand voltage value of the port device to protect the logic input port, the second node B is the same as the potential of the third node S, the voltage conversion logic circuit 104 performs voltage conversion according to the input terminal as the power voltage value VDD, and the internal output port VOUT and the input port VIN have a preset corresponding logic high-low level relationship.

It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalents, modifications and/or omissions as may be made without departing from the spirit and scope of the invention may be resorted to.