阅读说明：本技术 处理NVMe完成队列（CQ）阻塞的方法与存储设备 (Method for processing NVMe Completion Queue (CQ) blocking and storage device ) 是由 王朋 张泽 于 2019-11-04 设计创作，主要内容包括：本申请提供了处理NVMe完成队列(CQ)组合的方法与存储设备,该方法包括：从第一缓存区获取命令的处理结果；若完成队列不可用,将命令的处理结果存放至CQM寄存器；将CQM寄存器的内容搬移到第二缓存区；在完成队列可用时,将第一缓存区中的命令的处理结果和/或第二缓存区中的命令的处理结果填充到完成队列。通过执行NVMe队列管理方法,使得队列填满时,处理结果不需要一直排队等待,从而改善NVMeSSD控制器的数据处理能力。(The application provides a method and a storage device for processing NVMe Completion Queue (CQ) combination, wherein the method comprises the following steps: acquiring a processing result of the command from the first cache region; if the completion queue is unavailable, storing the processing result of the command to a CQM register; moving the content of the CQM register to a second cache region; when the completion queue is available, the processing results of the commands in the first buffer and/or the processing results of the commands in the second buffer are populated into the completion queue. By executing the NVMe queue management method, when the queue is full, the processing result does not need to be queued all the time, so that the data processing capacity of the NVMeSSD controller is improved.)

1. An NVMe queue management method, the method comprising:

acquiring a processing result of the command from the first cache region;

if the completion queue is unavailable, storing the processing result of the command to a CQM register;

moving the content of the CQM register to a second cache region;

and when the completion queue is available, filling the processing result of the command in the first buffer area and/or the processing result of the command in the second buffer area into the completion queue.

2. The method of claim 1, wherein prior to depositing the results of processing of the command to a CQM register, the method further comprises:

and judging whether the completion queue is available, wherein the completion queue is judged to be available when the completion queue has a storage space in which data can be written, and the completion queue is judged to be unavailable when the completion queue does not have a storage space in which data can be written.

3. The method of claim 1 or 2 wherein the CQM register is located in the second cache, the location of the CQM register within the second cache being updated in response to the depositing of the processing result of the command to the CQM register such that the CQM register is enabled to receive the processing result of the new command.

4. The method of any of claims 1-3, wherein the moving the contents of the CQM register to the second cache comprises:

moving contents of a CQM register to the second cache area in response to the CQM register being filled with data; alternatively, the first and second electrodes may be,

an interrupt is sent to a processor to cause the processor to move the contents of the CQM register to the second cache area.

5. The method of any of claims 1-4, wherein the populating the completion queue with processing results of commands in the first buffer and/or processing results of commands in the second buffer when the completion queue is available, comprises:

after the contents of the CQM register are moved to a second cache region, moving the processing result of the command in the second cache region to the first cache region; populating a completion queue with processing results of commands in the first cache in response to the completion queue being available; alternatively, the first and second electrodes may be,

after the moving the contents of the CQM registers to the second cache, the completion queue is populated with the results of the processing of the commands in the second cache in response to the completion queue being available.

6. The method of claim 5, wherein said moving the results of processing of commands in the second cache to the first cache comprises:

when the first buffer stores the processing results of the other commands except the processing results of the commands in the second buffer, the processing results of the commands in the second buffer are transferred to the first buffer so that the processing results of the commands transferred from the second buffer are first filled in the completion queue when the processing results of the commands in the first buffer are filled in the completion queue.

7. The method of claim 5, wherein in response to the completion queue being available, the method further comprises:

determining whether a processing result of the command exists in the second cache region;

if the second cache region does not have the processing result of the command, filling the processing result of the command in the first cache region into the completion queue;

if the second cache region has the processing result of the command, the processing result of the command in the second cache region is filled into the completion queue, and then the processing result of the command in the first cache region is filled into the completion queue.

8. The method of any of claims 2-7, wherein the determining whether the completion queue is available comprises:

detecting a capacity of a storage space already used by the completion queue; comparing the total capacity of the pre-stored storage space of the completion queue with the capacity of the used storage space; when the capacity of the used storage space is smaller than the total capacity, judging that the completion queue is available; alternatively, the first and second electrodes may be,

if the completion queue is in the host, sending a query request to the host, wherein the query request is used for inquiring whether the completion queue is available or not; and judging that the completion queue is available when the host returns the indication that the completion queue is available.

9. An NVMe queue manager, comprising an acquisition module, a data processing module, a CQM register and a queue filling module, wherein,

the obtaining module obtains a processing result of the command from the first cache region;

if the completion queue is unavailable, the data processing module stores the processing result of the command to the CQM register, and the data processing module moves the content of the CQM register to a second cache region;

when the completion queue is available, the queue filling module fills the processing result of the command in the first buffer area and/or the processing result of the command in the second buffer area into the completion queue.

10. The NVMe queue manager of claim 9, wherein the queue populating module populates the completion queue with processing results of commands in the first buffer and/or processing results of commands in the second buffer when the completion queue is available, comprising:

after the contents of the CQM register are moved to a second cache region, the queue filling module moves the processing result of the command in the second cache region to the first cache region; in response to the completion queue being available, the queue fill module fills the completion queue with processing results of commands in the first buffer; alternatively, the first and second electrodes may be,

after the moving the contents of the CQM registers to the second cache, the queue fill module fills the completion queue with processing results of commands in the second cache in response to the completion queue being available.

Technical Field

The present application relates to storage technology, and in particular, to a method and a storage device for handling NVMe Completion Queue (CQ) blocking in an NVMe storage device.

Background

FIG. 1 illustrates a block diagram of a solid-state storage device. The solid-state storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the solid-state storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the solid-state storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high-speed Peripheral Component Interconnect), NVMe (NVM Express, high-speed nonvolatile storage), ethernet, fiber channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The Memory device 102 includes an interface 103, a control section 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

NAND flash Memory, phase change Memory, FeRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), XPoint Memory, and the like are common NVM.

The commit queue (SQ) and Completion Queue (CQ) are dedicated to servicing NVMe commands in the NVMe protocol. Information interaction between the host and the storage device is realized based on SQ (submissionQueue) and CQ (completionQueue) in the NVMe queue, the host issues a command through the SQ, and the NVMe storage device returns a command response through the CQ. When the NVMe storage device processes commands fast and the host obtains the results of command processing from the CQ slowly, it is likely that the CQ queue overflows due to the limited depth of the CQ. NVMe devices need to prevent CQ queue overflow from occurring and handle situations where the CQ queue is full and cannot receive command processing results.

Disclosure of Invention

According to a first aspect of the present application, there is provided a first NVMe queue management method according to the first aspect of the present application, comprising: acquiring a processing result of the command from the first cache region; if the completion queue is unavailable, storing the processing result of the command to a CQM register; moving the content of the CQM register to a second cache region; when the completion queue is available, the processing results of the commands in the first buffer and/or the processing results of the commands in the second buffer are populated into the completion queue.

According to the embodiment of the application, when the completion queue is unavailable, the command processing result is firstly stored in the second buffer area, and after the completion queue is available, the command processing result in the second buffer area is filled into the completion queue, so that after the completion queue is full, the command processing result does not need to be inquired and the completion queue is not required to be available all the time for submitting the command processing result, the processing result flexibly flows to the buffer area, the occupied resource for data processing is reduced, and the data processing capacity of a control part of the storage device is improved.

Further, it is common that a completion queue is available, the hardware of the control component populating the completion queue with command processing results; and the completion queue is unavailable in an abnormal condition, so that the complexity of hardware design is not increased due to the fact that a few abnormal conditions are processed, when the completion queue is unavailable, the hardware only fills the command processing result into a second buffer area or a CQM register, and the subsequent processing such as checking that the completion queue is available is delivered to the processor or the CPU core for execution. Therefore, tasks are reasonably divided between hardware and firmware (software), the hardware efficiently processes common tasks, and the CPU processes complex abnormal tasks.

According to a first NVMe queue management method of the present application, there is provided a second NVMe queue management method according to the first aspect of the present application, wherein it is determined whether a completion queue is available before storing a processing result of a command in a CQM register, wherein the completion queue is determined to be available when there is a storage space in which data can be written in the completion queue, and the completion queue is determined to be unavailable when there is no storage space in which data can be written in the completion queue.

In the embodiment, whether the completion queue is available is judged in advance, so that the subsequent destination of the processing result can be timely and quickly determined according to the judgment result, and the data processing capacity of the NVMeSSD controller is further improved.

According to the first or second NVMe queue management method of the present application, there is provided a third NVMe queue management method according to the first aspect of the present application, wherein after the processing result of the command is acquired from the first buffer area, the processing result of the command is sent to the NVMe controller.

According to a third NVMe queue management method of the present application, there is provided a fourth NVMe queue management method according to the first aspect of the present application, storing a processing result of a command to a CQM register, including: the NVMe controller moves the processing result of the command to a CQM register; alternatively, the NVMe controls the transfer of the processing result of the command from the first cache area to the CQM register.

In the two embodiments, the NVMe controller is used for carrying data, and the NVMe controller is used as hardware, so that the speed of processing data can be accelerated, and the execution speed of the method can be improved.

According to one of the first to fourth NVMe queue management methods of the present application, there is provided the fifth NVMe queue management method according to the first aspect of the present application, wherein the CQM register is located in the second cache area, and the position of the CQM register in the second cache area is updated in response to storing the processing result of the command to the CQM register, so that the CQM register can receive the processing result of the new command.

In the embodiment, the CQM register is arranged in the second cache area, so that the processing result of the command is directly moved to the second cache area when the processing result is moved to the CQM register, the data moving process is simplified, and the method is easier to implement.

According to one of the first to fifth NVMe queue management methods of the present application, there is provided a sixth NVMe queue management method according to the first aspect of the present application, moving the contents of the CQM register to the second cache area, including: moving contents of the CQM register to a second cache area in response to the CQM register being filled with data; alternatively, an interrupt is sent to the processor to cause the processor to move the contents of the CQM register to the second cache area.

In the embodiment, various modes for moving the content of the CQM register to the second cache area are provided, so that flexible selection can be performed according to actual requirements, and the flexibility of the method is improved.

According to a second NVMe queue management method of the present application, there is provided a seventh NVMe queue management method according to the first aspect of the present application, wherein when a completion queue is available, a processing result of a command in the first buffer area is filled in the completion queue.

According to one of the first to sixth NVMe queue management methods of the present application, there is provided an eighth NVMe queue management method according to the first aspect of the present application, wherein when a completion queue is available, populating the completion queue with a processing result of a command in the first buffer and/or a processing result of a command in the second buffer, the method including: after the content of the CQM register is moved to the second cache region, moving the processing result of the command in the second cache region to the first cache region; filling a processing result of the command in the first cache region to a completion queue in response to the completion queue being available; alternatively, after moving the contents of the CQM register to the second cache, the completion queue is populated with the results of processing of the commands in the second cache in response to the completion queue being available.

In this embodiment, a plurality of ways of filling the processing result of the command into the completion queue are provided, and correspond to a plurality of scenes, respectively, so that the required ways can be determined directly and quickly according to the scenes, and the effect of accelerating the execution speed is achieved.

According to an eighth NVMe queue management method of the present application, there is provided the ninth NVMe queue management method according to the first aspect of the present application, wherein the moving the processing result of the command in the second cache area to the first cache area includes: when the first buffer area stores the processing results of other commands except the processing results of the commands in the second buffer area, the processing results of the commands in the second buffer area are moved to the first buffer area, so that when the processing results of the commands in the first buffer area are filled into the completion queue, the processing results of the commands moved from the second buffer area are first filled into the completion queue.

According to an eighth NVMe queue management method of the present application, there is provided the tenth NVMe queue management method according to the first aspect of the present application, in response to a completion queue being available, the method further comprising: determining whether a processing result of the command exists in the second cache region; if the second cache region does not have the processing result of the command, filling the processing result of the command in the first cache region into a completion queue; if the second cache region has the processing result of the command, the processing result of the command in the second cache region is filled into the completion queue, and then the processing result of the command in the first cache region is filled into the completion queue.

In the two embodiments, after the completion queue is available, a plurality of modes for filling the processing result of the command into the completion queue are provided, so that flexible selection can be performed according to actual requirements, and the flexibility of the method is improved.

According to one of the second to tenth NVMe queue management methods of the present application, there is provided an eleventh NVMe queue management method according to the first aspect of the present application, the determining whether the completion queue is available, including: detecting the capacity of the used storage space of the completion queue; comparing the total capacity of the pre-stored storage space of the completion queue with the capacity of the used storage space; when the capacity of the used storage space is smaller than the total capacity, judging that the completion queue is available; or if the completion queue is in the host, sending a query request to the host, wherein the query request is used for inquiring whether the completion queue of the host is available; if the host returns an indication that the completion queue is available, the completion queue is determined to be available.

In the embodiment, various modes for judging whether the completion is available are provided, so that the selection can be flexibly performed according to actual requirements, and the flexibility of the method is improved.

According to one of the first to eleventh NVMe queue management methods of the present application, there is provided the twelfth NVMe queue management method according to the first aspect of the present application, the first buffer area and/or the second buffer area being a queue.

In this embodiment, the data storage manner of the queue is adopted in the first buffer area and/or the second buffer area, which is simple and easy to implement, and the queue is also matched with the data storage manner of the completion queue, so that when data in the buffer area is written into the completion queue, the data can be written into the completion queue according to the original sequence without adjustment, thereby achieving the effect of simplifying the operation.

According to a second aspect of the present application, there is provided a first NVMe queue manager according to the second aspect of the present application, including an obtaining module, a data processing module, a CQM register, and a queue filling module, wherein the obtaining module obtains a processing result of a command from a first cache region; if the completion queue is unavailable, the data processing module stores the processing result of the command to the CQM register, and the data processing module moves the content of the CQM register to a second cache region; when the completion queue is available, the queue filling module fills the completion queue with processing results of the commands in the first buffer and/or processing results of the commands in the second buffer.

According to the first NVMe queue manager of the present application, there is provided the second NVMe queue manager according to the second aspect of the present application, the NVMe queue manager further comprising a determination module that determines whether the completion queue is available before storing a processing result of the command in the CQM register, wherein when the completion queue has a storage space in which data can be written, the completion queue is determined to be available, and when the completion queue does not have a storage space in which data can be written, the completion queue is determined to be unavailable.

According to the first or second NVMe queue manager of the present application, there is provided a third NVMe queue manager according to the second aspect of the present application, wherein the data processing module stores the processing result of the command to the NVMe controller after acquiring the processing result of the command from the first cache region; the NVMe controller is coupled with or includes the NVMe queue manager.

According to a third NVMe queue manager of the present application, there is provided a fourth NVMe queue manager according to the second aspect of the present application, the data processing module depositing the processing result of the command to the CQM register, including: the NVMe controller moves the processing result of the command to the CQM register; or, the NVMe controls to move the processing result of the command from the first cache area to the CQM register.

According to one of the first to fourth NVMe queue managers of the present application, there is provided the fifth NVMe queue manager according to the second aspect of the present application, wherein the second cache area is located in a CQM register, and the data processing module updates a position of the CQM register in the second cache area in response to the depositing of the processing result of the command to the CQM register, so that the CQM register is enabled to receive the processing result of the new command.

According to one of the first to fifth NVMe queue managers of the present application, there is provided a sixth NVMe queue manager according to the second aspect of the present application, the data processing module moving the contents of the CQM register to the second buffer area, including: the data processing module sends a third command to the CQM register so that the CQM register moves the content of the CQM register to a second cache region; alternatively, the data processing module sends a fourth command to the processor to cause the processor to move the contents from the CQM register to the second cache area, the processor being coupled to the CQM register.

According to a second NVMe queue manager of the present application, there is provided a seventh NVMe queue manager according to the second aspect of the present application, the queue filling module filling the completion queue with a processing result of the command in the first buffer when the completion queue is available.

According to one of the first to sixth NVMe queue managers of the present application, there is provided an eighth NVMe queue manager according to the second aspect of the present application, the queue populating module populating the completion queue with a processing result of the command in the first buffer and/or a processing result of the command in the second buffer when the completion queue is available, including: after the content of the CQM register is moved to the second cache region, the queue filling module moves the processing result of the command in the second cache region to the first cache region; in response to the completion queue being available, the queue filling module fills the processing result of the command in the first buffer to the completion queue; alternatively, after moving the contents of the CQM register to the second cache, the queue fill module fills the completion queue with the processing results of the commands in the second cache in response to the completion queue being available.

According to an eighth NVMe queue manager of the present application, there is provided the ninth NVMe queue manager according to the second aspect of the present application, wherein the queue filling module moves the processing result of the command in the second buffer area to the first buffer area, and the method includes: when the first cache region stores the processing results of other commands except the processing results of the commands in the second cache region, the queue filling module moves the processing results of the commands in the second cache region to the first cache region, so that when the queue filling module fills the processing results of the commands in the first cache region to the completion queue, the queue filling module firstly fills the processing results of the commands moved from the second cache region to the completion queue.

According to an eighth NVMe queue manager of the present application, there is provided the tenth NVMe queue manager according to the second aspect of the present application, the queue filling module further determining whether a result of processing of the command is present in the second buffer area in response to the completion queue being available; if the second cache area has no processing result of the command, the queue filling module fills the processing result of the command in the first cache area into the completion queue; if the second cache region has the processing result of the command, the queue filling module fills the processing result of the command in the second cache region into the completion queue, and then fills the processing result of the command in the first cache region into the completion queue.

According to one of the second to tenth NVMe queue managers of the present application, there is provided an eleventh NVMe queue manager according to the second aspect of the present application, the determining module determining whether the completion queue is available, including: the judging module detects the capacity of the used storage space of the completion queue; comparing the total capacity of the pre-stored storage space of the completion queue with the capacity of the used storage space; when the capacity of the used storage space is smaller than the total capacity, judging that the completion queue is available; or, if the completion queue is in the host, the judgment module sends a query request to the host, and the query request is used for inquiring whether the completion queue of the host is available; if the host returns an indication that the completion queue is available, the completion queue is determined to be available.

According to one of the first to eleventh NVMe queue managers of the present application, there is provided a twelfth NVMe queue manager according to the second aspect of the present application, the first buffer and/or the second buffer being a queue.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.

FIG. 1 is a block diagram of a prior art memory device;

fig. 2 is an architecture diagram of a host exchanging commands with a storage device control unit according to the NVMe protocol according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of an NVMe queue manager according to an embodiment of the present application;

fig. 4 is a flowchart of an NVMe queue management method according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and "third," etc. in the description and claims of this application and the accompanying drawings are used for distinguishing between different objects and not necessarily for limiting a particular order. Furthermore, the terms "comprising" and "having," as well as variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or modules is not limited to only those steps or elements but may alternatively include other steps or modules not expressly listed or inherent to such process, method, article, or apparatus.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. One skilled in the art will explicitly or implicitly appreciate that the embodiments described herein can be combined with other embodiments.

In order to facilitate understanding by those skilled in the art, some terms of the present application will be explained below.

Both the submission queue SQ and the completion queue CQ are first-in-first-out (FIFO) queues. Both the host and the control component of the storage device supporting the NVMe protocol can access the SQ and CQ. The SQ and CQ are typically located in a DDRDRAM (double data rate Synchronous Random Access Memory) of the host, and may also be located in the control unit of the Memory device. SQ and CQ divide a memory area into several small memory blocks of equal length (called queue entries or entries), each for storing a message of fixed length (e.g., a send message and a complete message). The two queues both comprise a head pointer and a tail pointer, and each time a message is written, the tail pointer moves backwards by a small storage block; the head pointer is also moved one entry backwards each time a message is read. When the head and tail pointers are equal, i.e., the head and tail pointers point to the same entry, the queue is empty. After the pointer moves to the last entry of the queue, the next move will return to the first entry, i.e., the SQ and CQ are circular ring queues. And when the next time the tail pointer moves to the entry where the head pointer is located, the queue is full and new messages cannot be written.

The term "plurality" in the present application means two or more. "and/or" describes the association relationship of the associated objects, and means that there may be three relationships, for example, a and/or B, which means that a exists alone, a and B exist simultaneously, or B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

Embodiments of the present application are described below with reference to the drawings.

For better understanding of the embodiments of the present application, the basic architecture of the embodiments of the present application is described below. Referring to fig. 2, fig. 2 is an architecture diagram of a host exchanging commands with a storage device control unit according to the NVMe protocol according to an embodiment of the present application. SQ201 and CQ202 in fig. 2 are located within host 200, to which control component 203 of the storage device is coupled. For example, the host 200 writes a read command into the SQ201, and issues a hint message to the control unit 203 of the storage device to hint the control unit 203 of the storage device to read the read command from the SQ 201. The control section 203 of the storage device writes the processing result into the CQ202 after processing the read command, and then the control section 203 of the storage device issues hint information to the host 200, thereby informing the host 200 that the processing result can be read from the CQ. In this embodiment, the prompt message includes an interrupt request, a doorbell register updated according to the NVMe protocol, and the like, which is not limited herein.

Fig. 3 exemplarily shows a structural diagram of the NVMe queue manager. Referring to fig. 3, the NVMe queue manager 300 includes an acquisition module 301, a data processing module 302, a CQM (completed queue manager) register 303, a queue filling module 304, and a judgment module 305. The NVMe queue manager 300 in this embodiment executes the NVMe queue management method in this application. It should be understood that the NVMe queue management method in the present application is not limited to being performed by the NVMe queue manager 300, and may be performed by other electronic devices that perform the same function as the NVMe queue manager 300, or integrated within the control component 203.

The NVMe queue management method in the present application will be described below by taking the NVMe queue manager 300 as an example to execute the NVMe queue management method in the present application.

Referring to fig. 4, the NVMe queue management method in the present embodiment includes the following steps:

step S401, obtaining the processing result of the command from the first cache region;

step S402, if the completion queue is unavailable, storing the processing result of the command to a CQM register;

step S403, moving the content of the CQM register to a second cache region;

step S404, when the completion queue is available, filling the processing result of the command in the first buffer area and/or the processing result of the command in the second buffer area into the completion queue.

First, the acquisition module 301 executes step S401.

For example, the acquisition module 301 acquires, from the first buffer 306, the processing result of the command, which is stored to the first buffer 306 by the control section 203. It should be noted that the first cache region 306 may store processing results of a plurality of commands, and the obtaining module 301 may obtain at least one processing result when obtaining the processing results, and the number is not a key point in the present application, and the number is not emphasized. The processing result of the command in the whole text of the present application means at least one processing result, and is not described in detail below. For example, the obtaining module 301 obtains the processing results of 5 commands from the first buffer 306, where the 5 commands include a read command, a write command, and/or an erase command.

Alternatively, before the data processing module 302 executes step S402, the determining module 305 determines whether the completion queue is available, where the completion queue is determined to be available when the completion queue has a storage space into which data can be written, and the completion queue is determined to be unavailable when the completion queue has no storage space into which data can be written.

By way of example, the determining module 305 determines in the following manner, including:

mode 1, detecting the capacity of the used storage space of the completion queue; comparing the total capacity of the pre-stored storage space of the completion queue with the capacity of the used storage space; and when the capacity of the used storage space is smaller than the total capacity, judging that the completion queue is available.

In the mode 2, if the completion queue is in the host, a query request is sent to the host, and the query request is used for inquiring whether the completion queue of the host is available; if the host returns an indication that the completion queue is available, the completion queue is determined to be available.

Mode 3, the head and tail pointers of the completion queue are accessed; and if the next small storage block pointed by the tail pointer is the small storage block pointed by the head pointer, determining that the completion queue is available.

With respect to the above mode 1, for example, the total size of the CQ is 640 bits, the used storage space is 128 bits, and thus the capacity of the used storage space is smaller than the total capacity, and it is determined that the completion queue is available.

With regard to the above-mentioned mode 2, the determining module 305 sends the query request to the host 200, and the host 200 determines whether the completion queue is currently available, and indicates the determination result to the determining module 305. For example, host 200 may determine that the current completion queue is not available, thereby indicating that the determination module 305 is not available. It should be noted that the CQ in the present application may be located in the host or the control component 203, and is not limited herein.

For the above-mentioned mode 3, the determining module 305 obtains the current positions of the tail pointer and the head pointer by accessing the head pointer and the tail pointer, for example, the tail pointer is currently 12 entries away from the head pointer, so as to determine that the completion queue is available.

After executing step S401, the data processing module 302 executes step S402 or S404.

Specifically, when the completion queue is available, step S404 is executed to fill the completion queue with the processing result of the command in the first buffer. In this case, since the completion queue is available after storing the processing result of the command in the first buffer 306, the queue filling module 304 may directly fill the processing result to the completion queue. For example, if there are 10 commands in the first buffer 306 and the completion queue is available, but the completion queue can only store 5 commands currently, the queue filling module 304 fills the top 5 commands in the first buffer 306 into the completion queue.

When the completion queue is not available, the data processing module 302 performs step S402, that is, the data processing module 302 stores the processing result of the command in the CQM register 303.

Alternatively, the data processing module 302 stores the command processing results to the CQM register 303 in response to the completion queue being unavailable, regardless of whether the CQM register 303 has been written to other command processing results. The design of the data module 302 is thus simplified.

In some embodiments, the data processing module 302 sends the processing result of the command retrieved from the first cache to the NVMe controller so that the processing result of the command can be temporarily stored in the NVMe controller, waiting to determine whether the completion queue is available. The NVMe controller is coupled to the NVMe queue manager 300 or the NVMe queue manager 300 includes the NVMe controller. Thus, when step S402 is executed, the NVMe controller moves the processing result of the command to the CQM register 303; alternatively, the NVMe controller moves the processing result of the command from the first cache area 306 to the CQM register.

For example, the data processing module 302 sends a move request to the NVMe controller, which moves the processing result of the command to the CQM register 303.

For another example, the obtaining module 301 does not temporarily store the processing result of the command in the NVMe controller, and the data processing module 302 sends another move request to the NVMe controller, so that the NVMe controller moves the processing result of the command in the first cache region 306 to the CQM register 303

In some embodiments, CQM register 303 is a virtual register located within second cache region 307. The CQM register 303 is associated with a storage location of the second cache region 307. Moving the command processing results to the CQM registers is moving the command processing results to the storage locations associated with the CQM registers within the second cache area 307. And in response to depositing the processing result of the command to the CQM register, updating the storage location of the CQM register associated with the second cache such that the CQM register receives the processing result of the new command. For example, the second buffer 307 is organized as a queue, the CQM registers are associated with the tail of the queue within the second buffer 307, and writing data to the CQM registers is equivalent to filling the queue with data. The queue tail pointer of the queue is updated in response to writing data to the CQM register.

After step S402 is executed, step S403 is executed. That is, the contents of the CQM register 303 are moved to the second cache region 307.

Optionally, the following is used:

mode 3, in response to the CQM register 303 being filled with data, the contents of the CQM register are moved to the second cache region 307;

mode 4, an interrupt is sent to the processor, which moves the contents of the CQM register 303 to the second cache region 307 by executing an interrupt service routine.

With respect to mode 3, for example, the CQM register 303 actively moves all contents saved by itself to the second buffer 307 after detecting that itself is written with data or that itself is full

With respect to mode 4, for example, the NVMe queue manager 300 also includes a processor (not shown in the figure) that sends a data move request to the processor after the CQM registers 303 are filled with data or periodically, so that the processor moves the contents of the CQM registers 303 to the second cache region 307.

Therefore, the content in the CQM register 303 is moved to the second cache area 307 in time, and even if the processing result of the next command is written into the CQM register again by the data processing module 302 in a short time, the processing result of the command stored in the CQM register before is not overwritten. While the second cache 307 has more storage space than the CQM registers and can accommodate more command processing results that cannot be submitted to the completion queue.

Optionally, the second buffer 307 is organized as a queue, each entry of the queue accommodating one of the processing results of the command. Still alternatively, the queue of the second buffer 307 is managed and operated in the interrupt service routine.

After step S403 is performed, step S404 is also performed. The method specifically comprises the following conditions:

in case 1, after the contents of the CQM register 303 are moved to the second cache region 307, the processing result of the command in the second cache region 307 is moved to the first cache region 306; results of processing of commands in the first cache region 306 are populated to the completion queue in response to the completion queue being available.

In case 2, after the contents of the CQM register 303 are moved to the second cache region 307, the results of processing of the commands in the second cache region 306 are populated to the completion queue in response to the completion queue being available.

For case 1, after the processing result of the command is moved to the second buffer area 307, the processing result of the command in the second buffer area 307 is moved to the first buffer area 306 periodically or in response to the specified condition being satisfied, and the method according to steps S401-S404 may continue to be executed circularly until the processing results of the command are all filled in the completion queue. For example, the processor may clock and move the processing results in the second cache 307 to the first cache 306 every 3s or 30 s. For another example, after the processing result is moved to the second buffer area 307, it is periodically determined whether the completion queue is available through the determining module 305, and when the determination result that the completion queue is available is obtained, the processing result in the second buffer area 307 is moved to the first buffer area 306, and then the processing result in the first buffer area 306 is filled into the completion queue.

Optionally, the first buffer 306 and/or the second buffer 307 are queues. For example, if the first buffer area 307 and the second buffer area 307 are both queues, the processing results are still moved to the first buffer area 306 according to the arrangement of the processing results in the second buffer area 307, so that the processing results can be moved without adjusting the order of the processing results.

For case 2, for example, after the processing result is moved to the second buffer area 307, it is determined whether the completion queue is available periodically or in response to a specified condition, and when a determination result that the completion queue is available is obtained, the processing result in the second buffer area 307 is filled into the completion queue.

In some embodiments, after moving the processing results to second buffer 307, a determination is made as to whether the completion queue is available, either periodically or in response to a specified condition, and upon obtaining a determination that the completion queue is available, the processing results within second buffer 307 are moved to first buffer 306, and the processing results of the commands moved from the second buffer are populated to the completion queue prior to populating the completion queue with the processing results of the commands in the first buffer.

In other embodiments, upon determining that a completion queue is available, it is also determined whether there is a result of processing of the command in the second buffer 307; if the second buffer area 307 does not have the processing result of the command, the processing result of the command in the first buffer area 306 is filled into the completion queue; if the second buffer 307 has the processing result of the command, the processing result of the command in the second buffer 307 is filled into the completion queue, and then the processing result of the command in the first buffer 306 is filled into the completion queue.

Since the processing results of the commands stored in the second buffer 307 are due to the fact that the completion queue is full or an error occurs, the processing results of the commands cannot be temporarily filled into the completion queue, and the first buffer 306 stores the processing results of the new commands all the time, so as to ensure that the processing results of the old commands are filled into the completion queue before the processing results of the new commands. For example, if it is determined that there is a processing result of the command in the second buffer 307, the processing result in the second buffer 307 is filled into the completion queue. For example, there are processing results of 8 commands in the second buffer 307, and although the completion queue is available, the completion queue can only fill 4 processing results, so that the first 4 processing results sorted in the second buffer 307 are filled into the completion queue, the remaining 4 processing results continue to wait for the next time the completion queue is available, and the processing results of the commands in the first buffer 306 at this time execute steps S401, S402, and S403.

With continued reference to fig. 3, the present embodiment also provides an NVMe queue manager 300, which includes an obtaining module 301, a data processing module 302, a CQM register 303, and a queue filling module 304. In this embodiment, the manner in which the NVMe queue manager 300 executes the NVMe queue management method in the above embodiment may refer to the above description, and is not described herein again. In this embodiment, the obtaining module 301 obtains the processing result of the command from the first cache region 306; if the completion queue is not available, the data processing module 302 stores the processing result of the command to the CQM register 303, and the data processing module 302 moves the content of the CQM register 303 to the second cache region; when the completion queue is available, queue fill module 304 fills the completion queue with the processing results of the commands in first buffer 306 and/or the processing results of the commands in second buffer 307.

Optionally, the queue filling module 304 is configured to fill the completion queue with processing results of the commands in the first buffer 306, and the processor fills the completion queue with processing results of the commands in the second buffer 307 by executing firmware (software). Further, the processor recognizes that there is a processing result of the command in the second buffer 307 by executing firmware (software), and moves the processing result of the command in the second buffer 307 to the completion queue in preference to the processing result of the command in the first buffer 306. Alternatively, the CPU instructs the queue fill module 304 to suspend moving the command processing results in the first buffer 306 to the completion queue in response to the second buffer 307 having the processing results of the command.

In one embodiment, the NVMe queue manager 300 further comprises a determining module 305, and the determining module 305 determines whether the completion queue 202 is available before storing the processing result of the command in the CQM register 303, wherein the completion queue 202 is determined to be available 202 when the completion queue 202 has a storage space in which data can be written, and the completion queue 202 is determined to be unavailable when the completion queue 202 has no storage space in which data can be written.

In some embodiments, the data processing module stores the processing result of the command to the NVMe controller after acquiring the processing result of the command from the first cache region; the NVMe controller is coupled with or includes the NVMe queue manager.

In one embodiment, the data processing module 302, in storing the processing result of the command to the CQM register 303, includes: the NVMe controller moves the processing result of the command to the CQM register 303; alternatively, the NVMe controls to move 306 the processing result of the command from the first cache area to the CQM register 303.

In some embodiments, the CQM register 303 is located in the second cache 307, and the data processing module 302, in response to depositing the processing results of the command to the CQM register 303, updates the location of the CQM register 303 in the second cache 307 so that the CQM register 303 receives the processing results of the new command.

In some embodiments, the data processing module 302 moves the contents of the CQM register 303 to the second cache bank 3077, including: the data processing module 302 sends a third command to the CQM register 303 to cause the CQM register 303 to move its contents to the second cache region 307; alternatively, data processing module 302 sends a fourth command to the processor to cause the processor to move the contents from CQM register 303 to second cache region 307, the processor being coupled to CQM register 303.

In one embodiment, queue fill module 304 fills the processing results of the commands in first buffer 306 to completion queue 202 when completion queue 202 is available.

In some embodiments, queue fill module 304 fills the processing results of the commands in first buffer 306 and/or the processing results of the commands in second buffer 307 into completion queue 202 when completion queue 202 is available, including: after moving the contents of the CQM register 303 to the second cache region 307, the queue padding module 304 moves the processing results of the commands in the second cache region 307 to the first cache region 306; in response to completion queue 202 being available, queue fill module 304 fills the processing results of the commands in first buffer 306 to completion queue 202; alternatively, after moving the contents of the CQM register 303 to the second cache 307, the queue fill module 304 fills the completion queue 202 with the results of processing of the commands in the second cache 307 in response to the completion queue 202 being available.

In one embodiment, the queue filling module 304 moves the processing result of the command in the second buffer 307 to the first buffer 306, including: when the first buffer 306 stores the processing results of the other commands except the processing results of the commands in the second buffer 307, the queue filling module 304 moves the processing results of the commands in the second buffer 307 to the first buffer 306, so that the queue filling module 304 fills the processing results of the commands moved from the second buffer 307 into the completion queue 304 first when the processing results of the commands in the first buffer 306 are filled into the completion queue 202.

In one embodiment, in response to completion queue 202 being available, queue fill module 304 also determines whether there is a result of processing of the command in second buffer region 307; if there is no processing result of the command in the second buffer 307, the queue filling module 304 fills the processing result of the command in the first buffer 307 into the completion queue 202; if there is a processing result of the command in the second buffer 307, the queue filling module 304 fills the processing result of the command in the second buffer 307 into the completion queue 202, and then fills the processing result of the command in the first buffer 306 into the completion queue 202.

In some embodiments, the determining module 305 determines whether the completion queue 202 is available, including: the determining module 305 detects the capacity of the storage space used by the completion queue 202; comparing the total capacity of the pre-stored memory space of the completion queue 202 with the capacity of the used memory space; when the capacity of the used storage space is smaller than the total capacity, determining that the completion queue 202 is available; alternatively, if completion queue 202 is in the host, determining module 305 sends a query request to the host, where the query request is used to inquire whether host completion queue 202 is available; the completion queue 202 is determined to be available when the host returns an indication that the completion queue 202 is available.

In some embodiments, the first buffer and/or the second buffer are queues.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.