阅读说明：本技术 半导体管芯、半导体器件以及绝缘栅双极晶体管模块 (Semiconductor die, semiconductor device, and insulated gate bipolar transistor module ) 是由 V·范特里克 R·巴布斯克 C·耶格 C·R·缪勒 F-J·尼德诺斯泰德 F·D·普菲尔施 于 2020-10-21 设计创作，主要内容包括：公开了半导体管芯、半导体器件以及绝缘栅双极晶体管模块。一种半导体管芯(510)包括半导体本体(100)。半导体本体(100)包括第一有源部分(191)和第二有源部分(192)。第一有源部分(191)包括第一源极区(111)。第二有源部分(192)包括第二源极区(112)。栅极结构(150)从第一表面(101)延伸到半导体本体(100)中。栅极结构(150)具有沿着横向第一方向(291)的纵向栅极延伸(lg)。第一负载焊盘(311)和第一源极区(111)被电连接。第二负载焊盘(312)和第二源极区(112)被电连接。间隙(230)在横向上分离第一负载焊盘(311)和第二负载焊盘(312)。间隙(230)的在横向上的纵向延伸平行于第一方向(291)或者从第一方向(291)偏离不多于60度。连接结构(390)电连接第一负载焊盘(311)和第二负载焊盘(312)。连接结构(390)被形成在从第一表面(101)延伸到半导体本体(100)中的凹槽中和/或被形成在形成于第一表面(101)上的布线层中。(Semiconductor die, semiconductor device, and insulated gate bipolar transistor module are disclosed. A semiconductor die (510) includes a semiconductor body (100). The semiconductor body (100) comprises a first active portion (191) and a second active portion (192). The first active portion (191) includes a first source region (111). The second active portion (192) includes a second source region (112). The gate structure (150) extends from the first surface (101) into the semiconductor body (100). The gate structure (150) has a longitudinal gate extension (lg) along a lateral first direction (291). The first load pad (311) and the first source region (111) are electrically connected. The second load pad (312) and the second source region (112) are electrically connected. The gap (230) laterally separates the first load pad (311) and the second load pad (312). The longitudinal extension of the gap (230) in the transverse direction is parallel to the first direction (291) or deviates from the first direction (291) by no more than 60 degrees. A connection structure (390) electrically connects the first load pad (311) and the second load pad (312). The connection structure (390) is formed in a recess extending from the first surface (101) into the semiconductor body (100) and/or in a wiring layer formed on the first surface (101).)

1. A semiconductor die, comprising:

a semiconductor body (100) comprising a first active portion (191) and a second active portion (192), the first active portion (191) comprising a first source region (111) and the second active portion (192) comprising a second source region (112);

a gate structure (150) extending from the first surface (101) into the semiconductor body (100), wherein the gate structure (150) has a longitudinal gate extension (lg) along a lateral first direction (291);

a first load pad (311), wherein the first load pad (311) and the first source region (111) are electrically connected;

a second load pad (312), wherein the second load pad (312) and the second source region (112) are electrically connected, wherein the gap (230) laterally separates the first load pad (311) and the second load pad (312), wherein a longitudinal extension of the gap (230) in the lateral direction is parallel to the first direction (291) or deviates from the first direction (291) by no more than 60 degrees; and

a connection structure (390) electrically connecting the first load pad (311) and the second load pad (312), wherein the connection structure (390) is formed in a recess extending from the first surface (101) into the semiconductor body (100) and/or in a wiring layer formed on the first surface (101).

2. The semiconductor die according to the preceding claim, wherein the connection structure (390) comprises a trench connection structure (391) extending into the semiconductor body (100), the trench connection structure (391) comprising a conductive part (395) and an insulating part (399), the insulating part (399) separating the conductive part (395) from the semiconductor body (100).

3. The semiconductor die according to the preceding claim, wherein the longitudinal extension of the trench connection structure (391) runs parallel to the longitudinal extension of the gap (230).

4. A semiconductor die according to claim 2, wherein the longitudinal extension of the trench connection structure (391) is inclined with respect to the longitudinal extension of the gap (230).

5. A semiconductor die according to any of the three preceding claims, wherein the connection structure (390) comprises a plurality of trench connection structures (391).

6. The semiconductor die of any of the preceding four claims, further comprising:

a trench electrode (165) which extends into the semiconductor body (100), wherein the conductive part (395) of the trench connection structure (391) is in contact with the trench electrode (165).

7. A semiconductor die according to any preceding claim, wherein the gap (230) has a gap width (wg) orthogonal to the first direction (291), and wherein the gap width (wg) is at least 2 μm.

8. The semiconductor die according to the preceding claim, wherein the connection structure (390) has a maximum extension (lc) along the second direction (292) and the maximum extension (lc) is at most ten times the gap width (wg).

9. A semiconductor die according to any preceding claim, wherein the connection structure (390) comprises a connection line (392) formed on the semiconductor body (100), wherein the connection line (392) is formed outside the gap (230).

10. The semiconductor die of any of the preceding claims, further comprising:

a first trench electrode (165) formed in the first active portion (191) and extending into the semiconductor body (100), wherein the first trench electrode (165) and the first load pad (311) are in direct contact;

a second trench electrode (165) formed in the second active portion (192) and extending into the semiconductor body (100), wherein the second trench electrode (165) and the second load pad (312) are in direct contact;

a source connection line (397) formed on the semiconductor body (100), wherein the source connection line (397) is in direct contact with the first trench electrode (165), wherein the source connection line (397) is in direct contact with the second trench electrode (165), and wherein the connection structure (390) comprises a portion of the source connection line (397) extending from the first trench electrode (165) to the second trench electrode (165).

11. The semiconductor die of any of the preceding claims,

wherein the semiconductor body (100) further comprises:

a drift region (130) in which the drift region,

a first body region (120) forming a first pn-junction with the drift structure (130) and a second pn-junction with the first source region (110),

a second body region (120) forming a further first pn-junction with the drift structure (130) and a further second pn-junction with the second source region (110), and

the collector region (140), the collector region (140) and the drift region (130) form a third pn-junction (140), wherein the drift region (130) separates the collector region (140) and the body region (120).

12. A semiconductor device, comprising:

a semiconductor die (510) according to any of the preceding claims.

13. A semiconductor device, comprising:

a semiconductor body (100) comprising a first active portion (191) and a second active portion (192), the first active portion (191) comprising a first source region (111) and the second active portion (192) comprising a second source region (112);

a first load pad (311), wherein the first load pad (311) and the first source region (111) are electrically connected;

a second load pad (312), wherein the second load pad (312) and the second source region (112) are electrically connected, and wherein a gap (230) separates the first load pad (311) and the second load pad (312) in a lateral direction;

a metal structure (400);

a first load connection structure (315) connecting the first load pad (311) and the metal structure (400); and

a pad connection structure (390) electrically connecting the first load pad (311) and the second load pad (312), wherein the connection structure (390) has a longitudinal extension at an angle of at least 45 ° to the first load connection structure (315), and wherein the pad connection structure (390) contacts the first load pad (311) and the second load pad (312) at a side positioned opposite to the semiconductor body (100).

14. The semiconductor device as claimed in the preceding claim,

wherein the first load connection structure (315) comprises a load bonding wire (394).

15. Semiconductor device according to one of the two preceding claims,

wherein the pad connection structure (390) includes a bonding wire (393), wherein the bonding wire (393) is in direct contact with the first load pad (311) and the second load pad (312).

16. The semiconductor device of any of the three preceding claims, further comprising:

a second load connection structure (316) connecting the second load pad (312) and the metal structure (400), the first load connection structure (315) and the second load connection structure (316) being separate.

17. The semiconductor device as claimed in the preceding claim,

wherein the electrical path of the connection structure (390) is at least 50% shorter than an electrical path formed between the first load pad (311) and the second load pad (312) by the first load connection structure (315), the metal structure (400), and the second load connection structure (316).

18. An Insulated Gate Bipolar Transistor (IGBT) module comprising:

at least one of the semiconductor device (500) of any of the preceding five claims and/or the semiconductor die (510) of any of claims 1 to 12.

19. An Insulated Gate Bipolar Transistor (IGBT) module comprising:

a semiconductor die (510), the semiconductor die (510) comprising:

a semiconductor body (100) comprising a first active portion (191) and a second active portion (192), the first active portion (191) comprising a first source region (111) and the second active portion (192) comprising a second source region (112);

a first load pad (311), wherein the first load pad (311) and the first source region (111) are electrically connected; and

a second load pad (312), wherein the second load pad (312) and the second source region (112) are electrically connected, and wherein the first load pad (311) and the second load pad (312) are laterally separated;

a metal structure (400); and

a wiring connection structure (590) electrically connecting the first load pad (311) and the second load pad (312) via the metal structure (400), wherein the wiring connection structure (590) comprises a bonding wire (591), and wherein the bonding wire (591) of the wiring connection structure (590) has an inductance of at most 5nH and/or at least 5 x 10⁵s^-1The total damping constant of.

20. The IGBT module according to the preceding claim,

wherein the metal structure (400) comprises at least one of a load current plate (410), a kelvin support structure (420) and an electrode pad (451) of a further semiconductor device (450).

21. IGBT module according to any one of the two preceding claims,

wherein the bonding wire (591) of the wire connection structure (590) has an inductance of at most 1 nH.

Technical Field

Examples of the present disclosure relate to a semiconductor die having at least two load pads electrically connected to a source region. The present disclosure further relates to a power MOSFET (metal oxide semiconductor field effect transistor) or IGBT (insulated gate bipolar transistor) module.

IGBTs combine the gate drive characteristics of MOSFETs with the high current and low saturation voltage capabilities of bipolar transistors. In an IGBT module, a plurality of IGBTs are electrically connected in parallel to achieve a current handling capability on the order of greater than 100A.

There is a need for a semiconductor die that can be efficiently and variably used on a circuit board, a cluster of components, and/or in an IGBT module.

Disclosure of Invention

Embodiments of the present disclosure relate to a semiconductor die including a semiconductor body, a gate structure, a first load pad, a second load pad, and a connection structure. The semiconductor body includes a first active portion and a second active portion. The first active portion includes a first source region. The second active portion includes a second source region. The gate structure extends from the first surface into the semiconductor body and has a longitudinal gate extension along a lateral first direction. The first load pad and the first source region are electrically connected. The second load pad and the second source region are electrically connected. The gap laterally separates the first load pad and the second load pad. The longitudinal extension of the gap in the transverse direction is parallel to the first direction or deviates from the first direction by no more than 60 degrees. The connection structure electrically connects the first load pad and the second load pad. The connection structure is formed in a recess extending from the first surface into the semiconductor body and/or in a wiring layer formed on the first surface.

Another embodiment of the present disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor body, a first load pad, a second load pad, a metal structure, a first load connection structure, and a pad connection structure. The semiconductor body includes a first active portion and a second active portion. The first active portion includes a first source region. The second active portion includes a second source region. The first load pad and the first source region are electrically connected. The second load pad and the second source region are electrically connected. The gap laterally separates the first load pad and the second load pad. The first load connection structure connects the first load pad and the metal structure. The pad connection structure electrically connects the first load pad and the second load pad. The pad connection structure has a longitudinal extension making an angle of at least 45 degrees with the first load connection structure. The pad connection structure contacts the first and second load pads at a side positioned opposite the semiconductor body.

Another embodiment of the present disclosure relates to an IGBT module. The IGBT module includes a semiconductor device, a metal structure, and a wiring connection structure. The semiconductor device includes a semiconductor body, a first load pad, and a second load pad. The semiconductor body includes a first active portion and a second active portion. The first active portion includes a first source region. The second active portion includes a second source region. The first load pad and the first source region are electrically connected. The second load pad and the second source region are electrically connected. The first load pad and the second load pad are laterally separated. The wiring connection structure electrically connects the first load pad and the second load pad via the metal structure. The wiring connection structure includes a bonding wiring. The bonding wire of the wire connection structure has an inductance of at most 20 nH.

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of a semiconductor die, a semiconductor device, and an IGBT module, and together with the description serve to explain the principles of the embodiments. Further embodiments are described in the following detailed description and claims.

Fig. 1A to 1B illustrate a schematic plan view and a schematic cross-sectional view of a semiconductor die portion according to an embodiment, the semiconductor die portion including first and second load pads at a front side and a connection structure connecting the first and second load pads.

Fig. 2A to 2B illustrate a schematic cross-sectional view and a schematic plan view of a semiconductor die portion having a connection structure formed in a trench according to an embodiment.

Fig. 3A to 3B illustrate a schematic cross-sectional view and a schematic plan view of a semiconductor die portion having a plurality of connection structures formed in a trench according to an embodiment.

Fig. 4A-4B illustrate schematic cross-sectional and schematic plan views of a semiconductor die portion having a connection structure extending between two trench electrode structures, according to an embodiment.

Fig. 5A to 5B illustrate a schematic cross-sectional view and a schematic plan view of a semiconductor die portion having a connection structure formed in a wiring plane according to an embodiment.

Fig. 6 illustrates a schematic cross-sectional view of a semiconductor device portion including a pad connection structure having a bonding wire according to an embodiment.

Fig. 7A to 7C illustrate schematic plan views of a semiconductor device having a pad connection structure including a bonding wire according to further embodiments.

Fig. 8A to 8C illustrate schematic plan views of portions of an IGBT module including a short wiring connection structure between a load pad and a metal structure according to an embodiment.

Fig. 9A-9B illustrate schematic plan views of portions of an IGBT module having multiple IGBT semiconductor dies according to another embodiment.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments of a semiconductor die, a semiconductor device, and an IGBT module that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described with respect to one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present disclosure include such modifications and variations. Examples are described using specific language that should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Corresponding elements in different figures are denoted by the same reference numerals if not stated otherwise.

The terms "having," "including," and "comprising," etc. are open-ended and the terms indicate the presence of stated structures, elements, or features, but do not preclude the presence of additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

The term "electrically connected" describes a permanent low resistance connection between electrically connected elements, such as a direct ohmic contact between the relevant elements or a low resistance connection via metal and/or heavily doped semiconductor material. An ohmic contact is a non-rectifying electrical junction with a linear or nearly linear current-voltage characteristic. The term "electrically coupled" includes that one or more intermediate element(s) adapted for signal and/or power transfer may be connected between the electrically coupled elements, e.g., electrically decoupled elements controllable to temporarily provide a low resistance connection in a first state and a high resistance in a second state.

The ranges given for physical dimensions include the boundary values. For example, read for the range of parameter y from a to b as a ≦ y ≦ b. The same applies to ranges having a boundary value such as "at most" and "at least".

The main component of a layer or structure from a chemical composition or alloy is such an element whose atoms form the chemical composition or alloy. For example, copper and aluminum are the main components of copper-aluminum alloys.

The term "on …" is not to be construed as meaning "directly on …". Conversely, if an element is "on" another element (e.g., one layer is "on" another layer or "on" a substrate), then a further component (e.g., a further layer) may be located between the two elements (e.g., if one layer is "on" the substrate, then a further layer may be located between the layer and the substrate).

With respect to the structures and doped regions formed in the substrate, the second region is "below" the first region if the minimum distance between the second region and the main surface of the first substrate at the front side of the substrate is greater than the maximum distance between the first region and the main surface of the first substrate. The second region is "directly below" the first region, wherein vertical projections of the first and second regions into the main surface of the first substrate overlap. The elevation projection is a projection orthogonal to the main surface of the first substrate.

The Safe Operating Area (SOA) defines the following voltage and current conditions: under such voltage and current conditions, the semiconductor device can be expected to operate without self-damage. The SOA is given by a published maximum value for device parameters such as maximum continuous load current, maximum gate voltage, and others.

The term "power semiconductor device" refers to a semiconductor device having a high voltage blocking capability of at least 30V (e.g., 100V, 600V, 3.3kV or higher) and having a nominal on-state current or forward current of at least 1A (e.g., 10A or higher).

The semiconductor die includes the semiconductor portion of the semiconductor device and further structures that are typically formed on a wafer level. For example, the semiconductor die may include front side metallization at the front side and back side metallization at a side opposite the front side. The front side metallization may comprise one or more metal pads. The load current may flow from the metal pad through the semiconductor die to the backside metallization or from the backside metallization to the metal pad.

A semiconductor device includes at least one semiconductor die and at least one further structure formed after separating the semiconductor die from a wafer composite. For example, a semiconductor device may include a semiconductor die, terminals, and bond wires connecting the terminals to metal pads of the semiconductor die.

According to an embodiment, a semiconductor die may include a semiconductor body having a first active portion including a first source region and having a second active portion including a second source region.

At the front side, the semiconductor body may have a first surface with coplanar planar surface sections in a horizontal plane. At the back side, the semiconductor body may have a flat second surface, which may be essentially parallel to the first surface. The side surface region may connect an edge of the first surface and an edge of the second surface. The horizontal cross section of the semiconductor body may be polygonal, for example approximately rectangular. For example, the semiconductor body may have the shape of a regular polygonal (e.g., rectangular or hexagonal) prism with or without rounded edges. The first surface may extend laterally along a plane spanned by the lateral direction and may have a thickness along a vertical direction perpendicular to the lateral direction. The vertical extension or thickness of the semiconductor body may be in the range from 20 μm to 700 μm.

The semiconductor body may comprise a single crystal semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe). In addition to the main component, the semiconductor body may also comprise dopant atoms, such As phosphorus (P), boron (B) and/or arsenic (As). The semiconductor material may include further impurities such as hydrogen (H), fluorine (F) and/or oxygen (O).

The semiconductor body may include a first active portion and a second active portion. The first active portion and the second active portion are defined in a horizontal plane and extend from the first surface to the second surface. The first active portion and the second active portion are laterally separated from each other. The semiconductor body may comprise more than two active portions, for example four, six or eight active portions, wherein each active portion is laterally separated from adjacent active portions.

The active part conducts at least a major part of the load current, e.g. the IGBT collector current. Each active portion comprises a surface portion of the first surface at which a load current enters or leaves the semiconductor body, e.g. via a load contact structure. The surface area of each active portion may be defined by a smallest convex polygon or a smallest rectangle that includes all load contact structures assigned to the respective active portion. Alternatively, the surface area may be defined by an area in which the load pad is in direct contact with the semiconductor body. Each active portion may have a rectangular or approximately rectangular shape in the horizontal plane. The passive portions of the semiconductor body may laterally separate adjacent active portions and may laterally separate the active portions from the side surface regions. The passive part does not contain a load contact structure. The minimum distance between two load contact structures of two adjacent active portions is at least twice, e.g. at least ten times, the average distance between two adjacent load contact structures in the same active portion.

The source region is a heavily doped region of the first conductivity type within the semiconductor body. In addition to the source regions, each active part may also comprise further doped regions which, among other things, comprise the semiconductor part of an insulated gate FET (field effect transistor) for the control part of the IGBT.

The gate structure may extend from the first surface into the semiconductor body. The gate structure may have a longitudinal gate extension along a lateral first direction and a gate width along a lateral second direction orthogonal to the first direction. The longitudinal gate extension is larger than the gate width, for example at least ten times the gate width. The gate structure may include a conductive gate electrode and a gate dielectric separating the gate electrode from the semiconductor body.

The semiconductor die may include a plurality of parallel gate structures. For example, the first plurality of gate structures may extend from at least one side of the first active portion to an opposite side, and the second plurality of gate structures may extend from one side of the second active portion to an opposite side.

The semiconductor die may include a first load pad electrically connected to the first source region. The first load pad may be in direct contact with the first surface, wherein the first load pad and the first source region may form a low-resistance ohmic contact. Alternatively, the first load contact structure may extend vertically from the first load pad into the semiconductor body or into the semiconductor body, wherein the first load contact structure and the first source region form a low-resistance ohmic contact. The first load contact structure may extend through an interlayer dielectric between the first load pad and the semiconductor body.

The semiconductor die may include a second load pad electrically connected to the second source region. The second load pad may be in direct contact with the first surface, wherein the second load pad and the second source region may form a low-resistance ohmic contact. Alternatively, the second load contact structure may extend vertically from the second load pad through the interlayer dielectric into the semiconductor body or into the semiconductor body, wherein the second load contact structure and the second source region form a low-resistance ohmic contact.

In an on state of the semiconductor die, a portion of the load current enters or exits the semiconductor die through the first load pad and the second load pad. The load pad may be a front side emitter pad of the IGBT. The load current may flow through the semiconductor body from the first load pad and the second load pad at the front side to the second surface at the back side of the semiconductor body or in opposite directions.

The gap may laterally separate the first load pad and the second load pad. The longitudinal extension of the gap in the transverse direction may be parallel to the first direction, or may deviate from the first direction by no more than 60 degrees, no more than 45 degrees, or no more than 30 degrees in the horizontal plane. For example, the gap may run parallel or nearly parallel to the gate structure. The connection structure electrically connects the first load pad and the second load pad. The connection structure may be formed in a recess extending from the first surface into the semiconductor body. Alternatively or additionally, the connection structure may be formed in a wiring layer formed on the first surface. For example, a portion of the interlayer dielectric may be formed between the connection structure and the semiconductor body, and the connection structure may be separated from the semiconductor body.

Load pads arranged along a lateral direction orthogonal to the longitudinal direction of the gate structure may be decoupled to some extent at the die level. In other words, the load pads may be electrically separated at the die level, or may be electrically connected only through paths having a relatively high impedance, for example through moderately doped regions in the semiconductor body. The decoupling may cause the load pads to have slightly different potentials in the operational mode. During certain operating states, for example in a short circuit state, the decoupling may facilitate and/or may amplify oscillations in at least part of the load current path of the semiconductor die. The connection structure directly connects the first load pad and the second load pad at the die level. The impedance of the connection structure may be selected independently of other parameters of the semiconductor die, such as the doping concentration in the doped region in the connection path between the first load pad and the second load pad. The impedance of the connection structure may be selected to suppress and/or dampen oscillations without adversely affecting other device characteristics.

For example, the impedance may be selected such that a maximum potential difference between the first load pad and the second load pad is below a critical level during operation of the semiconductor die within the SOA. The resistance of the connection structure may be at most 100m omega. For example, the resistance may be at most 10m Ω or at most 1m Ω. According to another example, the inductance of the connection structure may be at most 20nH or at most 2 nH. By way of example, the connection structure may combine a resistance of at most 100m Ω and an inductance of at most 20nH, a resistance of at most 10m Ω and an inductance of at most 2nH, or a resistance of at most 1m Ω and an inductance of at most 2 nH. According to a further example, the damping constant of the connection structure may be in the range from 0.1m Ω/nH to 20m Ω/nH, for example in the range from 0.5m Ω/nH to 5m Ω/nH.

Connecting the first load pad and the second load pad at the die level may provide more room for the manner in which the semiconductor die may be electrically connected to device terminals or to other devices and/or conductive structures in the subassembly (e.g., in an IGBT module). For example, providing a connection structure on a die level may facilitate bond wires that are connected to the first and second load pads and that carry a load current may extend parallel to the gate structure. In particular, the connection structure can be combined with a load pad including copper as a main component and with a load bonding wire running parallel to the gate structure without increasing the tendency to oscillate.

According to an embodiment, the connection structure may comprise a trench connection structure extending into the semiconductor body. For example, the trench connection structure may extend from the first surface into the semiconductor body. The trench connection structure may include a conductive portion and an insulating portion. The insulating portion may separate the conductive portion from the semiconductor body.

The trench connection structure may be efficiently formed at the wafer level by at least partially using processes that define and form gate structures or other trench structures. The formation of the trench connection structure and the formation of the gate structure and/or other trench structures may share one or more processes. For example, a single trench etch mask may define the gate structure and/or further trench structures and trench connection structures. A single trench etch process may simultaneously form a trench for the gate structure and/or further trench structures and one or more trenches for the connection structures. The insulating portion of the trench connection structure may be formed by using at least some of the processes applied to form the gate dielectric. For example, a single deposition process or a single oxidation process may form at least a portion of the gate dielectric and/or additional trench dielectric and trench connection structure insulating portions. The conductive portion of the trench connection structure may be formed by using at least one of processes for forming the gate electrode and/or the inactive trench electrode. For example, further single deposition and/or patterning processes may form the gate electrode and/or the passive trench electrode and the trench connection structure conductive portion.

Furthermore, the formation of the connection structure in the trench may have only a low or no negative effect on the area efficiency. For example, the connection structure may be formed primarily or entirely outside of any active portion. For example, the trench connection structure between the first load pad and the second load pad may be formed exclusively in a portion of the semiconductor body separating the first active portion and the second active portion.

The trench connection structure conductive portion may comprise doped polysilicon so that the impedance of the trench connection structure may be finely tuned by the doping concentration and geometry of the trench connection structure.

According to an embodiment, the longitudinal extension of the groove connection structure may run parallel to the longitudinal extension of the gap. The resistance and/or the inductance of the trench connection structure may be relatively low. In any operating state, the potential distribution across the first load pad and the second load pad may be fairly uniform.

According to a further embodiment, the longitudinal extension of the groove connection structure may be inclined with respect to the longitudinal extension of the gap, for example at least 30 degrees. For example, the longitudinal extension of the groove connection structure may be orthogonal to the longitudinal extension of the gap. For example, the longitudinal extension may be orthogonal to the longitudinal extension of the gap and orthogonal to the longitudinal extension of the gate structure.

According to an embodiment, the connection structure may include a plurality of groove connection structures. For example, the connection structure may comprise a plurality of groove connection structures running orthogonally to the longitudinal extension of the gap. The trench connection structure may be efficiently formed to have approximately the same width as the gate structure and/or further trench structures.

According to an embodiment, the semiconductor die may comprise a passive trench electrode extending into the semiconductor body. The trench dielectric may electrically separate the passive trench electrode from the semiconductor body. The passive trench electrode may be electrically connected to a predetermined potential. For example, the passive trench electrode may be a source trench electrode electrically connected to the potential of an emitter load pad of an IGBT or a power MOSFET.

The inactive trench electrode and the trench dielectric form an inactive trench structure. The semiconductor die may include a plurality of parallel inactive trench structures. For example, the plurality of first passive trench structures may extend from at least one side of the first active portion to an opposite side, and the plurality of second passive trench structures may extend from one side of the second active portion to an opposite side.

The trench connection structure can be efficiently formed with the passive trench structure. The trench connection structure, the first inactive trench structure closest to the gap, and the second inactive trench structure closest to the gap may form a ladder structure, wherein the first inactive trench structure closest to and the second inactive trench structure closest to form a rail, and wherein the trench connection structure forms a step.

According to an embodiment, the gap between the first load pad and the second load pad may have a gap width along a direction orthogonal to a longitudinal extension of the gap. For example, the gap width may be taken along a transverse second direction orthogonal to the first direction. The gap width may be at least 2 μm. For example, the gap between the first load pad and the second load pad may be free of further conductive structures above the first surface, and the gap width may be at least 2 μm. According to another example, a further conductive structure is formed in the gap on the semiconductor body, wherein the gap width is at least 10 μm. For example, a portion of the metal gate wiring may be formed on the first surface in the gap.

According to an embodiment, the connection structure may have a maximum extension along the width of the gap (in other words, orthogonal to the longitudinal extension of the gap). The maximum extension of the connection structure may be at most ten times the width of the gap, for example at most twice the width of the gap.

According to another embodiment, the connection structure may comprise a connection line. The connection line may be formed on the first surface of the semiconductor body. The connection line may be formed outside the gap. The connecting lines may be separated from the semiconductor body. For example, a portion of the interlayer dielectric structure may separate the connection line from the semiconductor body.

For example, the connection line may comprise a main portion extending parallel to an outer edge of the first surface in an edge portion of the semiconductor body, wherein the edge portion separates the active portion from the side surface region. A further portion of the connecting line may extend laterally from the main portion to below the first and second load pads. The vertical vias may electrically connect the first and second load pads with further connection line portions. Alternatively or additionally, the one or more passive first trench electrodes and the one or more passive second trench electrodes may extend below the connecting line, and the vertical vias may electrically connect the respective passive trench electrodes with the connecting line. The connection line may have the sole purpose of connecting the first load pad and the second load pad.

According to an embodiment, the semiconductor die includes a first passive trench electrode extending from the first surface into the first active portion. The first trench contact structure may electrically connect the first load pad with the first passive trench electrode. The first trench contact structure may extend vertically through the interlayer dielectric between the first load pad and the first inactive trench electrode. The semiconductor die may include a second passive trench electrode extending from the first surface into the second active portion. The second trench contact structure may electrically connect the second load pad and the second inactive trench electrode. The second trench contact structure may extend vertically through the interlayer dielectric between the second load pad and the semiconductor body.

The source connection line may be formed on the first surface between the active portion and the side surface region. The source connection line and the first inactive trench electrode may be electrically connected. For example, the via may extend vertically from the source connection line to the first passive trench electrode. The source connection line and the second inactive trench electrode may be electrically connected. For example, the via may extend vertically from the source connection line to the second passive trench electrode.

The connection structure may include a subsection of the source connection line, wherein the subsection extends from the first inactive trench electrode closest to the gap to the second inactive trench electrode closest to the gap. The connection structure can be efficiently formed by modifying the existing layout.

According to an embodiment, the semiconductor body may further comprise a drift region, a body region and a collector region. The drift region may comprise a relatively lightly doped drift zone of the first conductivity type. The drift zone may extend horizontally through the entire semiconductor body or almost through the entire semiconductor body. The dopant profile and vertical extension of the drift zone are designed to withstand at least a major portion of the nominal blocking voltage of the semiconductor die. Alternatively or in addition to the drift zone, the drift zone may comprise a compensation structure, e.g. a superjunction structure, wherein the superjunction structure may comprise a plurality of p-doped columns and n-doped columns, wherein the p-doped columns and the n-doped columns form a vertical pn-junction, and wherein in a horizontal cross-section of the superjunction structure the surface area across the p-dopant concentration deviates from the surface area across the n-dopant concentration by no more than 20%, e.g. no more than 5%.

The first body region in the first active portion may form a first pn-junction with the drift structure and a second pn-junction with the first source region. The second body region in the second active portion may form a further first pn-junction with the drift structure and may form a further second pn-junction with the second source region.

The collector region may have the second conductivity type or may comprise several laterally separated zones of the second conductivity type. The collector region and the drift region may form one or more third pn-junctions. The drift region is formed between a collector region at one side and a body region at an opposite side. The drift region may separate a collector region at one side and a body region at the opposite side.

The drift region may comprise further doped regions of both conductivity types. For example, the drift zone may comprise an intermediate zone of the first conductivity type between the body zone and the drift zone. The intermediate zone may separate at least a portion of the body zone from the drift zone. The maximum dopant concentration in the intermediate zone may be at least twice as high as the minimum dopant concentration in the drift zone. For example, the maximum dopant concentration in the intermediate zone may be at least ten times the minimum dopant concentration in the drift zone.

The drift region may include a buffer layer of the first conductivity type at a side opposite the body region. The buffer layer may separate the drift zone and the collector region. The maximum dopant concentration in the buffer layer may be at least twice as high as the minimum dopant concentration in the drift zone. For example, the maximum dopant concentration in the buffer layer may be at least ten times the minimum dopant concentration in the drift zone. The drift region may include an intermediate region of the second conductivity type. Each intermediate region may be formed along or adjacent to one of the gate structures. The intermediate region may separate at least part of the body zone from the drift zone. The drift zone and each intermediate region may form one or more pn-junctions.

According to an embodiment, the semiconductor device may comprise any of the semiconductor dies described above. The semiconductor device may further include a first load terminal, a gate terminal, and a second load terminal. The first load terminal may be electrically connected or coupled to the first load pad and the second load pad, for example, by a metal clip and/or a bonding wire (e.g., a circular bonding wire or a ribbon-shaped bonding wire). The second load terminal may be electrically connected or coupled to a backside metallization formed on the second surface of the semiconductor body, for example, by a solder layer. The backside metallization and the collector region may form a low resistance ohmic contact. The gate terminal may be electrically connected or coupled to the gate pad, for example, by a bonding wire. The gate pad may be electrically connected or coupled with a gate electrode in the gate structure. The semiconductor device may be a reverse blocking IGBT or a reverse conducting IGBT.

According to an embodiment, a semiconductor device may include a semiconductor body, a first load pad, a second load pad, a metal structure, a first load connection structure, and a pad connection structure.

The semiconductor body may include a first active portion and a second active portion. The first active portion may include a first source region. The second active portion may include a second source region. The first load pad and the first source region may be electrically connected. The second load pad and the second source region may be electrically connected. The gap may laterally separate the first load pad and the second load pad. The first load connection structure may connect the first load pad and the metal structure. The pad connection structure may electrically connect the first load pad and the second load pad. The connection structure may have a longitudinal extension making an angle of at least 45 ° with the first load connection structure. The connection structure may contact the first and second load pads at a side positioned opposite the semiconductor body.

The connection structure directly connects the first load pad and the second load pad. The impedance of the connection structure may be selected independently of other wiring connections between the load pad and the further structure. The impedance of the connection structure may be selected to suppress and/or damp oscillations that may occur in at least part of the load current path under certain operating conditions without adversely affecting other wiring parameters.

The gate structure may extend from the first surface into the semiconductor body. The gate structure may have a longitudinal gate extension along a lateral direction. The longitudinal gate extension may have an angle of less than 45 degrees to the longitudinal extension of the first load connecting structure. The longitudinal gate extension is larger than a gate width orthogonal to the longitudinal gate extension, e.g. at least ten times the gate width. The gate structure may include a conductive gate electrode and a gate dielectric separating the gate electrode from the semiconductor body. The semiconductor die may include a plurality of parallel gate structures.

According to an embodiment, the first load connection structure may include at least one load bonding wire. For example, the first load connection structure may include at least two load engaging wires, e.g., four, five, or six load engaging wires. All load engaging wires of the first load connecting structure may be arranged electrically in parallel. All load engaging wires of the first load connecting structure may be of the same type, of the same material and/or of the same cross-sectional area. For example, the load bonding wire may be a circular bonding wire or a ribbon bonding wire.

At least over the first load pad, a load connection structure (e.g., one or more bond wires) may extend approximately parallel to the longitudinal extension of the gap. The load connection structure may run parallel or approximately parallel to a gate structure formed in the semiconductor body. The load connection structure may further contact a top surface of a third load pad of the semiconductor device. The connection structure may at least partially compensate for effects on oscillations in the load current path that may be caused by inductance and/or resistance of the load engaging wiring.

According to an embodiment, the pad connection structure may include a bonding wire directly contacting the first load pad and directly contacting the second load pad. The bonding wire may be a circular bonding wire or a ribbon bonding wire. A bonding wire may be attached to the exposed top surface of the first load pad and the exposed top surface of the second load pad. The pad connection structure can be efficiently provided by moderately modifying the wire bonding process.

According to an embodiment, the semiconductor device may further include a second load connection structure connecting the second load pad and the metal structure. The second load connection structure may include at least one load engaging wiring. For example, the second load connection structure may include two, four, five, or six load engaging wires. All load engaging wires of the second load connecting structure may be electrically parallel. All load engaging wires of the second load connecting structure may be of the same type, of the same material and/or of the same cross-sectional area. For example, the load bonding wire may be a circular bonding wire or a ribbon bonding wire.

The first load connection structure and the second load connection structure may be separate. The first load connecting structure and the second load connecting structure may be different entities. The first and second load connecting structures may be the same material or may be made of different materials.

According to an embodiment, the electrical path of the connection structure is at least 50% shorter than the electrical path formed between the first load pad and the second load pad by the first load connection structure, the metal structure and the second load connection structure.

According to an embodiment, the IGBT module may comprise at least one of a semiconductor device as described above and a semiconductor die as described above.

According to an embodiment, an IGBT module may include a semiconductor die, a metal structure, and a wiring connection structure. The semiconductor die may include a semiconductor body, a first load pad, and a second load pad. The semiconductor body may include a first active portion and a second active portion. The first active portion may include a first source region. The second active portion may include a second source region. The first load pad and the first source region may be electrically connected. The second load pad and the second source region may be electrically connected. The first load pad and the second load pad are laterally separated. The wiring connection structure may connect the first load pad and the second load pad via a metal structure. The wiring connection structure may include a bonding wire. The bonding wires of the wire connection structure may have an inductance of at most 5nH (e.g., at most 2 nH) and/or at least 5 x 10⁵s^-1(5E 51/s) total damping constant (R/2L). The inductance of the wiring connection structure may be sufficiently low to efficiently suppress and/or damp oscillations in the portion of the load current path.

The gate structure may extend from the first surface into the semiconductor body. The gate structure may have a longitudinal gate extension along a lateral direction. The longitudinal gate extension may have an angle of less than 45 degrees with respect to a length extension of the wiring connection structure. The longitudinal gate extension is larger than a gate width orthogonal to the longitudinal gate extension, e.g. at least ten times the gate width. The gate structure may include a conductive gate electrode and a gate dielectric separating the gate electrode from the semiconductor body. The semiconductor die may include a plurality of parallel gate structures.

According to an embodiment, the metal structure may comprise at least one of a load current plate, a kelvin support structure and an electrode pad of the further semiconductor device. By way of example, the further semiconductor device may be a power semiconductor diode electrically connected in anti-parallel with the semiconductor die. For example, the lateral distance between the semiconductor die and the load current plate, the lateral distance between the semiconductor die and the kelvin support structure, and/or the lateral distance between the semiconductor die and the further semiconductor device is at most 2mm, for example for a semiconductor device having a blocking capability of at most 1200V.

According to an embodiment, the bonding wire of the wire connection structure may have an inductance of at most 1 nH.

Fig. 1A-1B illustrate a portion of a semiconductor die 510 that includes a connection structure 390 that electrically connects a first load pad 311 and a second load pad 312 at a front side of the semiconductor die 510.

The semiconductor die 510 may be a bare die of an IGBT, such as a reverse blocking IGBT or an RC-IGBT (reverse conducting IGBT). The semiconductor body 100 of the semiconductor die 510 may be formed primarily of a single-crystal semiconductor material, such as, by way of example, silicon (Si), germanium (Ge), silicon germanium crystal (SiGe), silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs).

The semiconductor body 100 has a first surface 101 at the front side. The semiconductor body 100 may have a rectangular shape in a horizontal plane parallel to the first surface 101. A normal line of the first surface 101 defines a vertical direction, and a direction orthogonal to the vertical direction is a lateral direction. The semiconductor body 100 may include active portions 191, 192, 193, 194 defined side-by-side in a horizontal plane. The active portions 191, 192, … are laterally separated from each other. For example, the active portions 191, 192, … may be regularly arranged in rows and columns. The grid-like passive section 180 laterally separates the active sections 191, 192, … from one another and laterally separates the active sections 191, 192, … from the side surface regions 103 at the edge of the semiconductor body 100.

In the active portions 191, 192, …, the semiconductor body 100 comprises semiconductor portions of control IGBTs like IGFET structures. The first active portion 191 further includes a first source region 111 of the first conductive type, among other things. The second active portion 192 further includes a second source region 112 of the first conductivity type. The third active portion 193 includes a third source region of the first conductive type. The fourth active portion 194 includes a fourth source region of the first conductive type. The source regions 111, 112, … may extend from the first surface 101 into the semiconductor body 100. By way of example, the first conductivity type may be n-type. Alternatively, the first conductivity type may be p-type.

The gate structure 150 extends from the first surface 101 into the semiconductor body 100. The gate structure 150 has a longitudinal gate extension along a lateral first direction 291. The gate structure 150 may extend laterally from one side of the active portions 191, 192 to an opposite side, and may extend into the passive portion 180 on both sides. Each gate structure 150 may extend laterally through two active portions 191, 193, 192, 194 arranged along the first direction 291 and through a section (not shown) of the passive portion 180 between the two associated active portions 191, 193, 192, 194. Each source region 111, 112, … may directly adjoin one or more gate structures 150.

Gate structure 150 may include a gate electrode 155 and a gate dielectric 159 separating gate electrode 155 from semiconductor body 100. The gate electrode 155 may be a uniform structure or may have a layered structure including one or more conductive layers. For example, the gate electrode 155 may include heavily doped polysilicon and/or a metal element or metal composition. The gate dielectric 159 may include a semiconductor oxide (e.g., thermally grown or deposited silicon oxide), a semiconductor nitride (e.g., deposited or thermally grown silicon nitride), a semiconductor oxynitride (e.g., silicon oxynitride), and/or a ferroelectric material (e.g., hafnium oxide, HfO)₂Or BaTiO₃) Of the dielectric layer stack.

Load pads 311, 312, … are positioned over each active portion 191, 192, …. For example, the first load pad 311 is formed on the first active portion 191, the second load pad 312 is formed on the second active portion 192, and so on. Each load pad 311, 312, … may have the same horizontal cross-sectional shape as the corresponding active portion 191, 192, …. The horizontal cross-sectional area of each load pad 311, 312, … may be equal to or greater than the horizontal cross-sectional area of the corresponding active portion 191, 192, …. Each load pad 311, 312, … is electrically connected with at least the source regions 111, 112, … of the respective active portions 191, 192, …. The load pads 311, 312, … are separated from the gate electrode 155.

Load pads 311, 312, … may include aluminum or copper as the only major component or as one of several major components. For example, load pads 311, 312, … may include a copper alloy (e.g., copper aluminum alloy (CuAl) with or without silicon (Si)) or an aluminum alloy (e.g., AlSi or AlSiCu).

Gap 230 laterally separates first load pad 311 and second load pad 312. The gap 230 has a longitudinal extension parallel to the first direction 291. Connecting structure 390₁、390₂The first load pad 311 and the second load pad 312 are electrically connected. Connecting structure 390₁、390₂May comprise portions formed in trenches extending into the semiconductor body 100 and/or portions formed in wiring layers on the first surface 101.

Fig. 2A-2B relate to an embodiment comprising a trench connection structure 391. Fig. 2A-2B also show details of an IGBT with a passive electrode trench structure 160.

Fig. 2A shows a semiconductor body 100 having a first surface 101 at the front side and a second surface 102 at the back side. The first surface 101 and the second surface 102 are approximately parallel. The minimum distance between the first surface 101 and the second surface 102 depends on the voltage blocking capability specified for the semiconductor die 510. For example, for a semiconductor die 510 that is silicon (Si) based and specified for a blocking voltage of approximately 1200V, the distance between the first surface 101 and the second surface 102 may be in a range from 90 μm to 120 μm. Other embodiments relating to semiconductor dies with greater blocking capability may provide the semiconductor body 100 with a thickness of several hundred microns. For semiconductor dies with lower blocking voltages, the thickness may range from 35 μm to 90 μm for silicon (Si).

The semiconductor body 100 comprises a drift region 130, source regions 111, 112, body regions 121, 122 and a collector region 140. Drift region 130 may include a relatively lightly doped drift zone 131 of the first conductivity type. The drift zone may extend horizontally through the entire semiconductor body 100 or almost through the entire semiconductor body 100. The drift zone forms a voltage sustaining layer. The dopant profile and vertical extension of drift zone 131 are selected to withstand at least a major portion of the nominal blocking voltage of semiconductor die 510. The dopant concentration in the drift zone 131 may increase or decrease gradually or stepwise with increasing distance to the first surface 101, at least in the vertically extending part thereof. According to other embodiments, the dopant concentration in the drift zone 131 may be approximately uniform. For a silicon-based IGBT die, the average dopant concentration in the drift zone 131 can be at 5 x 10¹²(5E12) cm^-3And 1X 10¹⁵(1E15) cm^-3E.g. from 1 × 10¹³(1E13) cm^-3To 1X 10¹⁴(1E14) cm^-3Within the range of (1). The drift region 130 may include a buffer layer 139 of the first conductivity type between the drift zone 131 and the collector region 140. Buffer layer 139 can separate drift zone 131 and collector region 140. The maximum dopant concentration in buffer layer 139 can be at least twice as high as the maximum dopant concentration in drift zone 131.

The first body region 121 forms a first pn-junction with the drift region 130 and a second pn-junction with the first source region 111. The first body region 121, the first source region 111, and the first load pad 311 may be electrically connected. The second body region 122 may form a further first pn-junction with the drift region 120 and may form a further second pn-junction with the second source region 112. The second body region 122, the second source region 112, and the second load pad 312 may be electrically connected.

The collector region 140 is configured to act as a backside emitter. For non-reverse conducting IGBTs (e.g. with significantly lower than forward blocking)Standard IGBT with reverse blocking capability of capability) or an RC-IGBT with forward blocking capability and reverse blocking capability within the same order of magnitude, the collector region 140 may be a continuous layer of the second conductivity type. For an RC-IGBT, the collector region 140 can include a first zone of the first conductivity type and a second zone of the second conductivity type. The first zone and the second zone are alternately arranged, for example, along the horizontal direction. The collector region 140 (or the first and second zones of the RC-IGBT collector region 140) and the backside metallization 320 form an ohmic contact. The maximum dopant concentration in collector region 140 can be at least 1 x 10¹⁶(1E16) cm^-3E.g. at least 5 x 10¹⁷(5E17) cm^-3。

The semiconductor body 100 may also comprise advanced IGBT-cell design elements, such as various trenches with different functions, i.e. some trench electrodes are connected to a gate potential and some trench electrodes are connected to another potential (like a load terminal) or even left floating. A hole blocking layer of the same conductivity type as the source region may also be implemented between the body region and the drift region to improve device characteristics. Alternatively or additionally, a floating barrier region of the same conductivity type as the body region, for example a floating barrier region forming a pn-junction with a portion of the drift region 131, may be implemented in the semiconductor body 100.

In particular, fig. 2A to 2B show an inactive trench structure 160 extending from the first surface 101 into the semiconductor body 100. The inactive trench structure 160 may be a stripe-like structure extending parallel to the gate structure 150.

The passive trench structure 160 may comprise a passive trench electrode 165 and a trench dielectric 169 separating the passive trench electrode 165 from the semiconductor body 100. The passive trench electrode 165 may be a homogenous structure or may have a layered structure including one or more conductive layers. For example, the passive trench electrode 165 may include a heavily doped polysilicon layer. The passive trench electrode 165 and the gate electrode 155 may have the same configuration and may include the same material.

Trench dielectric 169 may comprise a semiconductor oxide (e.g., thermally grown or deposited silicon oxide), a semiconductor nitride (e.g., deposited or thermally grown silicon nitride), or a semiconductor oxynitride (e.g., silicon oxynitride). The trench dielectric 169 and the gate dielectric 159 may have the same configuration and/or may comprise the same material.

The gate structures 150 and the inactive trench structures 160 may alternate in a regular manner. For example, one single inactive trench structure 160 may be disposed between each pair of gate structures 150. According to other embodiments, two, three, or more passive trench structures 160 may be disposed between each pair of gate structures 150. According to other embodiments, the passive trench structure may be omitted, and the semiconductor die 510 may exclusively include the gate structure 150.

The gate electrode 155 may be electrically connected to a metal gate wiring 330 formed at the front side of the semiconductor body 100. The inactive trench electrode 165 is electrically separated from the gate electrode 155. The inactive trench electrode 165 may be electrically connected to the auxiliary structure or may be electrically floating. According to the illustrated embodiment, the passive trench electrodes 165 of the active portions 191, 192, … are electrically connected with the load pads 311, 312, … assigned to the active portions 191, 192, … in which the passive trench electrodes 165 are formed.

The gap 230 between the first load pad 311 and the second load pad 312 may have a longitudinal axis parallel to the first direction 291. In other words, the longitudinal extension of the gap 230 may be parallel to the gate structure 150. The gap 230 has a gap width wg along a second direction 292 orthogonal to the first direction 291.

The trench connection structure 391 includes a conductive portion 395 and an insulating portion 399 separating the conductive portion 395 from the semiconductor body 100. The trench connection structure 391 may be symmetrically formed with respect to a central plane in the center of the gap 230 and extend along the first direction 291. A portion of the metal gate wire 330 may be formed in the gap 230 on the first surface 101. A portion of the interlayer dielectric 210 separates the metal gate wiring 330 from the trench connection structure conductive portion 395 and from the semiconductor body 100. Interlayer dielectric 210 further separates load pads 311, 312 from gate electrode 155 in gate structure 150.

The first load contact structure 318 vertically connects the first load pad 311 with the first source region 111, the first body region 121, and the inactive trench electrode 165 in the first active portion 191. The second load contact structure 319 vertically connects the second load pad 312 with the second source region 112, the second body region 122, and the inactive trench electrode 165 in the second active portion 192.

The connection via 398 vertically connects the first load pad 311 and the connection structure conductive portion 395, and vertically connects the second load pad 312 and the connection structure conductive portion 395. The lateral extension lc of the trench connection structure 391 along the second direction 292 is larger than the gap width wg and smaller than the distance between the one of the trench structures 150, 160 in the first active portion 191 closest to the gap 230 and the one of the trench structures 150, 160 in the second active portion 192 closest to the gap 230.

Fig. 3A-3B illustrate a connection structure 390 comprising a plurality of trench connection structures 391 oriented parallel to each other. In the illustrated embodiment, the trench connection structure 391 is oriented with a longitudinal axis running orthogonal to the longitudinal extension of the gate structure 150. The trench connection structure 391 and the gate structure 150 may have the same width and/or may have the same vertical extension. According to another embodiment (not shown), the angle between the longitudinal axis of the trench connection structure 391 and the second direction 292 may be 45 degrees or less, e.g. 30 degrees.

In fig. 4A to 4B, each trench connection structure connects the one of the first active portions 191, which is closest to the gap 230, with the one of the second active portions 192, which is closest to the gap 230, which is the inactive trench structure 160. Conductive portion 395 of connection structure 390 and passive trench electrode 165 are directly connected.

Between the one of the first active portions 191 and the one of the second active portions 192 closest to the gap 230, which is the inactive trench structure 160 closest to the gap 230, the semiconductor body 100 does not contain the gate structure 150. The trench connection structure 391 and the passive trench structure 160 may have the same width and/or may have the same vertical extension.

The trench connection structure 391 and the first inactive trench structures 160 on each side of the gap 230 may form a ladder structure, wherein the closest inactive trench structure 160 in the first active portion 191 and the closest inactive trench structure 160 in the second active portion 192 form a rail, and wherein the trench connection structure 391 forms a rung.

Fig. 5A to 5B show a connection structure 390 comprising connection lines 392 formed in a wiring layer on the front side of the semiconductor body 100. The connection lines 392 are formed on the semiconductor body 100 and outside the gaps 230. For example, the connection line 392 is formed on the passive section 180 of the semiconductor body 100 between the side surface region 103 and the first and second active sections 191, 192. The inactive trench structure 160 extends laterally from the active portions 191, 192 to below the connection line 392. The via 397 vertically connects the connection line 392 and the passive trench electrode 165.

The connection line 392 may be a portion of the source channel 317 that extends along the entire lateral extension of the active portions 191, 192 along the second lateral direction 292 between the active portions 191, 192 and the side surface region 103. According to another embodiment, the connection line 392 may be shorter than the extension of the active portions 191, 192 in the second direction, e.g. at most ten times or twice the gap width wg.

The pad connection structure 390 of the semiconductor device 500 in fig. 6 includes one or more bonding wires 393 attached to the exposed top surfaces of the first and second load pads 311 and 312. The bond wire 393 bridges the gap 230. The first load connection structure 315 electrically connects the first load pad 311 with a terminal and/or with another metal structure (not shown). The first load connection structure 315 may include a plurality of parallel bonding wires 394 extending approximately parallel or slightly oblique to the longitudinal direction of the gate trench 150. The second load connection structure 316 connects the second load pad 312 with a terminal and/or with another metal structure. The second load connection structure 316 may include a plurality of parallel bonding wires 394 extending approximately parallel or slightly oblique to the longitudinal direction of the gate structure 150.

The electrical path of the bonding wire 393 is at least 50% shorter than the electrical path formed between the first load pad 311 and the second load pad 312 by the first load connection structure 315, the terminal or metal structure, and the second load connection structure 316.

Fig. 7A-7C illustrate a semiconductor device 500 having a semiconductor die 510, the semiconductor die 510 including: a first load pad 311 electrically connected to a first source region in the first active portion 191; a second load pad 312 electrically connected to the second source region in the second active portion 192; a third load pad 313 electrically connected to the third source region in the third active portion 193; and a fourth load pad 314 electrically connected to the fourth source region in the fourth active portion 194. The gate structure (not shown) runs parallel to the first direction 291.

Each semiconductor device 500 further comprises a first load connection structure 315 electrically connecting the third load pad 313 and the first load pad 311 with a terminal and/or with a further metal structure. The first load connection structure 315 may include a plurality of bonding wires 394. The bonding wire may be a circular bonding wire or a ribbon bonding wire. The second load connection structure 316 connects the fourth load pad 314 and the second load pad 312 with terminals and/or with other metal structures. The second load connection structure 316 may include a plurality of bonding wires. Over the semiconductor die 510, e.g., between the bonding contacts on the load pads 311, 312, 313, 314, the bonding wire 394 may extend approximately parallel to or slightly oblique to the longitudinal direction of the gate trench structure in the semiconductor die 510.

The metal gate wire 330 of the semiconductor die 510 may include a gate pad in a lateral center of the semiconductor die 510. According to another embodiment, the gate pad may be located along an edge of the semiconductor body 100 or in a corner of the semiconductor body 100. The gate bonding wire 335 may electrically connect the gate pad with a gate terminal of the semiconductor device or with a gate metal line of the IGBT module.

Fig. 7A shows a pad connection structure 393 including a bonding wire that crosses under or over the gate bonding wire 335. Pad connection structure 393 may be formed near an edge of semiconductor body 100 opposite to the edge spanned by first load connection structure 315 and second load connection structure 316.

In fig. 7B, the pad connection structure 393 includes a bonding wire that is not under or over the gate bonding wire 335. Pad connection structure 393 may be formed near an edge of semiconductor body 100 spanned by first load connection structure 315 and second load connection structure 316.

In fig. 7C, the pad connection structure 393 includes a first bonding wire that is not across the gate bonding wire 335 and a second bonding wire that is above or below the gate bonding wire 335. The first bonding wire may be formed near an edge of the semiconductor body 100 spanned by the first and second load connection structures 315 and 316. The second bonding wire may be formed near an edge of the semiconductor body 100 opposite to an edge spanned by the first and second load connection structures 315 and 316.

Fig. 8A-8C illustrate portions of an IGBT module that includes a semiconductor die 510 having at least a first load pad 311 and a second load pad 312, a metal structure 400, and a wiring connection structure 590. The gate structure (not shown) runs parallel to the first direction 291.

The back side of the semiconductor die 510 can be soldered or sintered to the collector plate 401. The wiring connection structure 590 may connect the first load pad 311 and the second load pad 312 via the metal structure 400. The inductance of the wiring connection structure 590 may be sufficiently low to efficiently damp and/or dampen oscillations in the load current path, e.g., at most 10nH, at most 5nH, or at most 1 nH. For example, the lateral distance between the semiconductor die 510 and the metal structure 400 is at most 2 mm.

In fig. 8A to 8B, the wiring connection structure 590 includes the first load connection structure 315 and the second load connection structure 316 as described above. In the illustrated embodiment, each of the first load connection structure 315 and the second load connection structure 316 may include four or more bonding wires.

In fig. 8A, metal structure 400 is a load current plate 410. The first slit 240 may electrically separate the load current plate 410 from the collector plate 401. The first slit width dm is at most 2 mm. Orthogonal to the first direction 291, the lateral extension of the load current plate 410 is equal to or greater than the lateral extension of the semiconductor die 510. The bonding wires of the first and second load connection structures 315 and 316 may be formed without lateral bending. The vertical projection of each of the bonding wires of the first and second load connection structures 315 and 316 may be straight.

In fig. 8B, the metal structure 400 is an electrode pad 451 of a further semiconductor device 450. The further semiconductor device 450 may be a power semiconductor diode having a lateral extension orthogonal to the first direction 291 that is smaller than a lateral extension of the semiconductor die 510. The backside electrode of the further semiconductor device 450 may be soldered or sintered to the collector plate 401. The bonding wires of the first and second load connection structures 315 and 316 may be formed with a lateral bend. The lateral distance dd between the semiconductor die 510 and the further semiconductor device 450 is at most 2 mm.

In fig. 8C, metal structure 400 includes kelvin support structure 420. The second slit 250 may electrically separate the kelvin support structure 420 from the collector plate 401. The second slit width dk is at most 2 mm.

The wiring connection structure 590 includes a first kelvin bonding wiring 591 and a second kelvin bonding wiring 592. The first kelvin bonding wire 591 electrically connects the first load pad 311 and the kelvin support structure 420. The second kelvin bond wire 592 electrically connects the second load pad 312 and the kelvin support structure 420. The vertical projection of each kelvin joint wiring 591, 592 may be straight. Kelvin support structure 420 may be electrically connected to a reference input of a high impedance input stage of a gate driver circuit that outputs a gate signal supplied to a gate electrode of semiconductor die 510. Kelvin support structure 420 is outside of any load current path.

The IGBT module further comprises a first load connection structure 315 and a second load connection structure 316 connecting the first load pad 311 and the second load pad 312 with a load current plate 410 separated from the collector plate 401 by the first slit 240. In this embodiment, the first slit width dm may be greater than 2mm because the kelvin bond wires 591, 592 may provide sufficiently low inductive coupling between the first load pad 311 and the second load pad 312.

Fig. 9A combines the embodiment of fig. 7A with an inter-die connection 493 between two load pads 311, 312 of an adjacent semiconductor die 510. The inter-die connections 493 may be further bond wires from the same type as the bond wires 393 of the inter-die pad connection structure. Further, fig. 9A shows the metal gate line 430 separated from the collector plate 401 in the lateral direction. The gate wire bond 335 electrically connects the gate metal wire 330 with the metal gate line 430.

Fig. 9B combines the intra-die pad-connection structure of fig. 7C with the inter-die connections between the two load pads 311, 312 of an adjacent semiconductor die 510 through kelvin bond wires 591 and kelvin support structures 420.

According to another embodiment, a semiconductor die may include a semiconductor body, a gate structure, a first load pad, a second load pad, and a connection structure. The semiconductor body may include a first active portion and a second active portion. The first active portion may include a first source region. The second active portion may include a second source region.

The gate structure may extend from the first surface into the semiconductor body. The gate structure may have a longitudinal gate extension along a lateral first direction. The first load pad and the first source region may be electrically connected. The second load pad and the second source region may be electrically connected. The gap may laterally separate the first load pad and the second load pad.

The connection structure electrically connects the first load pad and the second load pad. The connection structure may be formed in a wiring layer formed on the first surface and/or may be formed in a recess extending from the first surface into the semiconductor body. The connection structure (e.g. formed in the groove) may have a maximum lateral length extension which is at most ten times the gap width, e.g. at most twice the gap width.

The longitudinal extension of the gap in the transverse direction may be orthogonal to the first direction or may deviate no more than at least 30 degrees from the first direction.