阅读说明：本技术 电荷泵电路及其动态调整电压的供电方法 (Charge pump circuit and power supply method for dynamically adjusting voltage thereof ) 是由 简志刚 于 2019-10-21 设计创作，主要内容包括：本公开包含一种电荷泵电路及动态调整电压的供电方法,电荷泵电路包含电源接收端、接地端、正电输出端及负电输出端、第一储能电容及第二储能电容、第一飞驰电容及第二飞驰电容及泵单元电路。电源接收端接收电源电压。第一储能电容耦接于正电输出端及接地端间。第二储能电容耦接于负电输出端及接地端间。泵单元电路配置以：在两倍电源电压供电模式中,使第一飞驰电容及第二飞驰电容与电源接收端、接地端、正电输出端以及负电输出端间在第一操作时间及第二操作时间分别具有第一连接关系及第二连接关系。泵单元电路交错运行于第一操作时间及第二操作时间,使正电输出端、负电输出端分别输出电源电压两倍的正输出电压、负输出电压。(The disclosure includes a charge pump circuit and a power supply method for dynamically adjusting voltage, the charge pump circuit includes a power receiving end, a ground end, a positive output end, a negative output end, a first energy storage capacitor, a second energy storage capacitor, a first flying capacitor, a second flying capacitor and a pump unit circuit. The power receiving terminal receives a power voltage. The first energy storage capacitor is coupled between the positive output end and the ground end. The second energy storage capacitor is coupled between the negative electricity output end and the grounding end. The pump unit circuit is configured to: in the double-power-supply-voltage power supply mode, the first flying capacitor and the second flying capacitor respectively have a first connection relation and a second connection relation with the power receiving end, the grounding end, the positive output end and the negative output end at a first operation time and a second operation time. The pump unit circuit operates in a first operation time and a second operation time in a staggered mode, so that the positive output end and the negative output end respectively output positive output voltage and negative output voltage which are twice of the power supply voltage.)

1. A charge pump circuit, comprising:

a power receiving terminal configured to receive a power voltage;

a ground terminal;

a positive output terminal configured to output a positive output voltage;

a negative output terminal configured to output a negative output voltage;

a first energy storage capacitor electrically coupled between the positive output terminal and the ground terminal;

a second energy storage capacitor electrically coupled between the negative electricity output terminal and the ground terminal;

a first flying capacitor and a second flying capacitor;

a pump unit circuit configured to enable the first flying capacitor and the second flying capacitor to have a first connection relationship with the power receiving terminal, the ground terminal, the positive output terminal and the negative output terminal at a first operation time and a second connection relationship with the power receiving terminal, the ground terminal, the positive output terminal and the negative output terminal at a second operation time in a double power supply mode:

the pump unit circuit operates in the double power supply voltage supply mode in the first operation time and the second operation time in a staggered mode, so that the positive output end and the negative output end respectively output the positive output voltage and the negative output voltage which are twice of the power supply voltage.

2. The charge pump circuit of claim 1, wherein the pump unit circuit electrically couples a first flying cathode of the first flying capacitor to the power sink, electrically couples a second flying cathode of the second flying capacitor to the ground, and electrically couples a first flying anode of the first flying capacitor and a second flying anode of the second flying capacitor to the positive output terminal during the first operation time; and

and the pump unit circuit enables the first flying cathode of the first flying capacitor and the second flying anode of the second flying capacitor to be electrically coupled to the grounding terminal, enables the first flying anode of the first flying capacitor to be electrically coupled to the power receiving terminal and enables the second flying cathode of the second flying capacitor to be electrically coupled to the negative power output terminal in the second operation time.

3. The charge pump circuit of claim 1, wherein the pump unit controls a plurality of switches according to a first clock and a second clock whose operation phases do not overlap to operate the pump unit at the first operation time and the second operation time, the switches comprising:

a first switch coupled between the power receiving terminal and the first flying positive of the first flying capacitor;

a second switch coupled between the positive output terminal and the first flying positive of the first flying capacitor;

a third switch coupled between the positive output terminal and the second flying positive of the second flying capacitor;

a fourth switch coupled between the ground terminal and the second flying positive of the second flying capacitor;

a fifth switch coupled between the negative output terminal and the second flying cathode of the second flying capacitor;

a sixth switch coupled between the ground terminal and the second flying cathode of the second flying capacitor;

a seventh switch coupled between the ground terminal and the first flying cathode of the first flying capacitor; and

an eighth switch coupled between the power receiving terminal and the first flying cathode of the first flying capacitor.

4. The charge pump circuit of claim 3, wherein in the double supply voltage supply mode, the second switch, the third switch, the sixth switch, and the eighth switch conduct in response to an operating phase of the first clock, and the first switch, the fourth switch, the fifth switch, and the seventh switch conduct in response to an operating phase of the second clock.

5. The charge pump circuit of claim 1, wherein the pump unit operates at the first operating time and the second operating time by controlling a plurality of switches using a first clock and a second clock whose operating phases do not overlap, the switches comprising:

a first switch coupled between the power receiving terminal and the first flying positive of the first flying capacitor;

a second switch coupled between the positive output terminal and the first flying positive of the first flying capacitor;

a third switch coupled between the positive output terminal and the second flying positive of the second flying capacitor;

a fourth switch coupled between the positive output terminal and the first flying cathode of the first flying capacitor;

a fifth switch coupled between the ground terminal and the second flying positive of the second flying capacitor;

a sixth switch coupled between the negative output terminal and the first flying cathode of the first flying capacitor;

a seventh switch coupled between the negative output terminal and the second flying cathode of the second flying capacitor;

an eighth switch coupled between the ground terminal and the second flying cathode of the second flying capacitor;

a ninth switch coupled between the ground terminal and the first flying positive of the first flying capacitor;

a tenth switch coupled between the power receiving terminal and the positive output terminal;

an eleventh switch coupled between the ground terminal and the first flying cathode of the first flying capacitor; and

a twelfth switch coupled between the power receiving terminal and the first flying cathode of the first flying capacitor.

6. The charge pump circuit of claim 5, wherein in the double supply voltage supply mode, the second switch, the third switch, the eighth switch, and the twelfth switch conduct in response to an operating phase of the first clock, and the first switch, the fifth switch, the seventh switch, and the eleventh switch conduct in response to an operating phase of the second clock.

7. The charge pump circuit of any of claims 1 to 6, further comprising:

an amplitude detector configured to detect an amplitude of an input signal or an output signal of a subsequent circuit supplied with the positive output voltage and the negative output voltage, to select a power supply mode of the pump unit accordingly;

wherein the amplitude detector selects a one-third supply voltage supply mode when the amplitude is less than a first threshold, a one-half supply voltage supply mode when the amplitude is greater than the first threshold and less than a second threshold, a supply voltage supply mode when the amplitude is greater than the second threshold and less than a third threshold, and a double supply voltage supply mode when the amplitude is greater than the third threshold.

8. A power supply method for dynamically adjusting voltage is applied to a charge pump circuit, and comprises the following steps:

enabling a power supply receiving end to receive a power supply voltage, enabling a positive output end to output a positive output voltage and enabling a negative output end to output a negative output voltage;

electrically coupling a first energy storage capacitor between the positive output terminal and a ground terminal and electrically coupling a second energy storage capacitor between the negative output terminal and the ground terminal;

enabling a pump unit circuit to have a first connection relation among a first flying capacitor and a second flying capacitor, the power receiving end, the grounding end, the positive electricity output end and the negative electricity output end in a first operation time and a second connection relation in a second operation time in a double power supply voltage power supply mode; and

and the pump unit circuit is enabled to operate in the first operation time and the second operation time in a staggered mode in the double-power-supply-voltage power supply mode, so that the positive output end and the negative output end respectively output the positive output voltage and the negative output voltage which are twice of the power supply voltage.

9. The power supply method of claim 8, further comprising:

enabling the pump unit circuit to enable a first flying cathode of the first flying capacitor to be electrically coupled to the power receiving end, enable a second flying cathode of the second flying capacitor to be electrically coupled to the grounding end, and enable a first flying anode of the first flying capacitor and a second flying anode of the second flying capacitor to be electrically coupled to the positive output end during the first operation time; and

and enabling the pump unit circuit to enable the first flying cathode of the first flying capacitor and the second flying anode of the second flying capacitor to be electrically coupled to the grounding terminal in the second operation time, enable the first flying anode of the first flying capacitor to be electrically coupled to the power supply receiving terminal, and enable the second flying cathode of the second flying capacitor to be electrically coupled to the negative power output terminal.

10. The power supply method according to claim 8 or 9, further comprising:

an amplitude detector detects the amplitude of the input signal or the output signal of the subsequent circuit supplied by the positive output voltage and the negative output voltage, so as to select a power supply mode of the pump unit;

when the amplitude is smaller than a first threshold value, enabling the amplitude detector to select a one-third power supply voltage power supply mode;

when the amplitude is larger than the first threshold value and smaller than a second threshold value, enabling the amplitude detector to select a half power supply voltage power supply mode;

when the amplitude is larger than the second threshold and smaller than a third threshold, the amplitude detector selects a power supply mode of the power supply voltage; and

when the amplitude is greater than the third threshold, the amplitude detector is caused to select the double supply voltage supply mode.

Technical Field

The present disclosure relates to charge pump technologies, and in particular, to a charge pump circuit and a power supply method for dynamically adjusting a voltage thereof.

Background

Charge pump (charge pump) circuits are often used in driving circuits of electronic products. The charge pump circuit mainly utilizes the capacitance principle to realize voltage conversion so as to provide required output voltage. Among them, a headphone (headset) is also one of the devices that are often driven by a charge pump circuit.

With the increasing demand for high fidelity audio (Hi-Fi audio) in recent years, the specifications of earphones are increasing. Under the condition of Full Scale Output Voltage (FSOV) of partial earphone amplifier output specification, the volume of the earphone with low impedance is moderate, but the volume of the earphone with high impedance is insufficient; however, if a higher full-scale output voltage is applied to achieve the volume of the high-impedance earphone, the problem of power saving cannot be achieved. The main reason is that the full-scale output voltage is limited by the power supply voltage of the charge pump, and if the full-scale output voltage is low, the full-scale output voltage is more power-saving and cannot supply enough volume to the high-impedance earphone; however, if the voltage is high, the power cannot be saved.

Therefore, if a positive output voltage and a negative output voltage with absolute values higher than the power supply voltage can be generated while using a low power supply voltage, the power consumption and the performance of the charge pump circuit can be greatly improved.

Disclosure of Invention

In view of the problems of the prior art, an object of the present disclosure is to provide a charge pump circuit and a power supply method for dynamically adjusting a voltage thereof, so as to improve the prior art.

An objective of the present disclosure is to provide a charge pump circuit and a power supply method for dynamically adjusting a voltage thereof, so as to dynamically adjust an output voltage according to different output driving requirements, and achieve a power saving effect while driving a high impedance load.

The present disclosure includes a charge pump (charge pump) circuit, one embodiment of which includes: the power supply circuit comprises a power supply receiving end, a grounding end, a positive electricity output end, a negative electricity output end, a first energy storage capacitor, a second energy storage capacitor, a first flying capacitor, a second flying capacitor and a pump unit circuit. The power receiving terminal is configured to receive a power supply voltage. The positive electrical output is configured to output a positive output voltage. The negative output terminal is configured to output a negative output voltage. The first energy storage capacitor is electrically coupled between the positive output end and the ground end. The second energy storage capacitor is electrically coupled between the negative electricity output end and the grounding end. The pump unit circuit is configured to: in the double-power-supply-voltage power supply mode, the first flying capacitor and the second flying capacitor are enabled to have a first connection relation with the power receiving terminal, the grounding terminal, the positive output terminal and the negative output terminal at a first operation time and have a second connection relation at a second operation time. The pump unit circuit operates in a first operation time and a second operation time in a double power supply voltage supply mode in a staggered mode, so that the positive output end and the negative output end respectively output a positive output voltage and a negative output voltage which are double the power supply voltage.

The present disclosure further includes a power supply method for dynamically adjusting a voltage, applied to a charge pump circuit, an embodiment of which includes the following steps: enabling the power supply receiving end to receive the power supply voltage, enabling the positive electricity output end to output positive output voltage and enabling the negative electricity output end to output negative output voltage; electrically coupling the first energy storage capacitor between the positive output end and the ground end and electrically coupling the second energy storage capacitor between the negative output end and the ground end; enabling the pump unit circuit to have a first connection relation among the first flying capacitor and the second flying capacitor, the power receiving end, the grounding end, the positive electricity output end and the negative electricity output end at a first operation time and a second connection relation at a second operation time in a double power supply voltage power supply mode; and enabling the pump unit circuit to operate in a first operation time and a second operation time in a staggered mode in a power supply mode with twice power supply voltage, so that the positive output end and the negative output end respectively output positive output voltage and negative output voltage with twice power supply voltage.

The features, implementations, and technical advantages of the present disclosure will be described in detail with reference to the accompanying drawings.

Drawings

Fig. 1 shows a block diagram of a charge pump circuit in an embodiment of the present disclosure;

FIG. 2 shows a timing diagram of a first clock and a second clock in an embodiment of the present disclosure;

FIGS. 3A and 3B are schematic diagrams of pump unit circuits according to an embodiment of the present disclosure;

FIG. 4 is a first equivalent circuit diagram of the charge pump circuit in the double supply voltage power mode for a first operation time controlled by the working phase of the first clock according to an embodiment of the present disclosure;

FIG. 5 is a second equivalent circuit diagram of the charge pump circuit in the double supply voltage supply mode for a second operation time controlled by the working phase of the second clock according to an embodiment of the present disclosure;

FIG. 6 shows a schematic diagram of an amplifier circuit and a load according to an embodiment of the present disclosure; and

fig. 7 shows a flow chart of a power supply method for dynamically adjusting voltage according to an embodiment of the disclosure.

Description of the symbols

100 charge pump circuit

120 pump unit circuit

122 multiplexing circuit

122a, 122b multiplexer

124 amplitude detector

140 signal generating unit

600 amplifier circuit

610 load

700 power supply method

AMP amplifier

Cf1 first flying capacitor

Cf2 second flying capacitor

CK clock

CK1 first clock

CK2 second clock

Cm1, Cm2 control signals

Cp1 first energy storage capacitor

Cp2 second energy storage capacitor

GND ground terminal

N0 power receiving terminal

Positive electric output terminal of N1

N2 negative electricity output terminal

N3-N6 node

PH1 and PH2 working phases

S1-S12 switch

S710-S750 steps

VDD Power supply Voltage

VEE negative output voltage

Vin input signal

Vout output signal

VPP positive output voltage

Detailed Description

An objective of the present disclosure is to provide a charge pump circuit and a power supply method for dynamically adjusting a voltage thereof, so as to dynamically adjust an output voltage according to different output driving requirements, and achieve a power saving effect while driving a high impedance load.

Refer to fig. 1. Fig. 1 is a block diagram of a charge pump circuit 100 according to an embodiment of the disclosure. The charge pump circuit 100 includes: the pump unit circuit comprises a power receiving end N0, a ground end GND, a positive electric output end N1, a negative electric output end N2, a first energy storage capacitor Cp1, a second energy storage capacitor Cp2, a first flying capacitor Cf1, a second flying capacitor Cf2 and the pump unit circuit 120.

In one embodiment, the charge pump circuit 100 is configured to control the pump unit circuit 120 according to the first clock CK1 and the second clock CK2 to change the connection relationship between the first energy-storing capacitor Cp1, the second energy-storing capacitor Cp2, the first flying capacitor Cf1, and the second flying capacitor Cf2 and the circuit nodes, such as the power receiving terminal N0, the ground terminal GND, the positive output terminal N1, and the negative output terminal N2, so as to convert the input power voltage VDD into different positive output voltage VPP and negative output voltage VEE in different power supply modes.

Refer to fig. 2. Fig. 2 is a timing diagram of the first clock CK1 and the second clock CK2 according to an embodiment of the disclosure. As shown in fig. 2, the operating phase PH1 of the first clock CK1 does not overlap with the operating phase PH2 of the second clock CK2, so as to avoid the situation that the paths operating at different phases in the circuit and not connected with each other are not properly connected.

In one embodiment, the charge pump circuit 100 has four power modes. The charge pump circuit 100 has different power conversion rates in the four power supply modes. In the four power supply modes, the charge pump circuit 100 generates four output voltages (i.e., voltage difference between the positive output voltage VPP and the negative output voltage VEE) of the power supply voltage VDD, for example, output voltages 4 times (± 2VDD), 2 times (± VDD), 1 time (± 1/2VDD), and 2/3 times (± 1/3VDD) of the input power supply voltage VDD. The charge pump circuit 100 may select a power supply mode depending on the amount of power required by the subsequent stage circuit (i.e., the target circuit to which the charge pump circuit 100 supplies power).

For convenience of explanation, the four power supply modes are hereinafter referred to as a double power supply voltage power supply mode, a half power supply voltage power supply mode, and a one-third power supply voltage power supply mode, respectively.

The structure of the charge pump circuit 100 will be described in more detail below.

The power receiving terminal N0 is electrically connected to a system voltage source and receives a power voltage VDD from the system voltage source. The ground GND is electrically connected to the ground of the system.

The first storage capacitor Cp1 is coupled between the positive output terminal N1 and the ground terminal GND, and the second storage capacitor Cp2 is coupled between the negative output terminal N2 and the ground terminal GND.

The pump unit circuit 120 is coupled to the power receiving terminal N0, the ground terminal GND, the positive output terminal N1, the negative output terminal N2, the first flying capacitor Cf1 and the second flying capacitor Cf 2.

The pump unit circuit 120 operates in the selected power supply mode, and utilizes the first clock CK1 and the second clock CK2 to control the electrical connection relationship between the elements and the nodes, so as to convert the input power voltage VDD into the positive output voltage VPP and the negative output voltage VEE corresponding to the selected power supply mode.

In more detail, after the electrical connection relationship is determined, the positive output terminal N1 outputs the positive output voltage VPP generated by the charge pump circuit 100 converting the power supply voltage VDD, and the negative output terminal N2 outputs the negative output voltage VEE generated by the charge pump circuit 100 converting the power supply voltage VDD, thereby supplying the power required for the operation to the subsequent circuit. The first storage capacitor Cp1 and the second storage capacitor Cp2 may also be used as voltage stabilizing capacitors for the positive output voltage VPP and the negative output voltage VEE, respectively.

The first clock CK1 and the second clock CK2 can be generated by the signal generating unit 140. Since the implementation structure and operation principle of the signal generating unit 140 are well known to those skilled in the art, they are not described herein again.

Refer to fig. 3A and 3B. Fig. 3A and 3B are schematic diagrams of a pump unit circuit 120 according to an embodiment of the disclosure.

As shown in FIG. 3A, the pump cell circuit 120 includes a plurality of switches S1-S12. In fig. 3A, reference numeral "CK" denotes at least one of the first clock CK1 and the second clock CK 2.

As shown in fig. 3B, the pump unit circuit 120 may also include a multiplexing circuit 122. The multiplexing circuit 122 is coupled to each of the switches S1-S12. The multiplexing circuit 122 is also coupled to the signal generating unit 140.

When the charge pump circuit 100 is operating, the multiplexing circuit 122 inputs the first clock CK1 and the second clock CK2 to the control terminal of at least one of the switches respectively in response to the power mode to be performed by the pump unit circuit 120. In some embodiments, the multiplexing circuit 122 may include a multiplexer 122a and a multiplexer 122 b.

The multiplexer 122a has an input terminal coupled to the signal generating unit 140, and an output terminal coupled to one or more switches (e.g., S1, S2, S3, S4, S8, S10, S11, or S12) to turn on and output the first clock CK1 received from the input terminal to at least one output terminal according to the selected power supply mode.

The multiplexer 122b has an input terminal coupled to the signal generating unit 140, and an output terminal coupled to one or more switches (e.g., S1, S2, S5, S6, S7, S9, S10, or S11) to turn on and output the second clock CK2 received from the input terminal to at least one output terminal according to the selected power supply mode.

In some embodiments, the pump unit circuit 120 may further include an amplitude detector 124 coupled to the multiplexing circuit 122 and electrically connected to the input or output of the subsequent stage circuit. The power supply terminals of the latter circuit are coupled to the positive output terminal N1 and the negative output terminal N2, and are supplied with an input signal for driving or supplying the latter circuit by the positive output voltage VPP and the negative output voltage VEE.

The amplitude detector 124 can determine the power supply mode to be executed by the pump unit circuit 120 (the charge pump circuit 100) according to the magnitude of the signal amplitude value of the input signal or the output signal of the subsequent stage within a predetermined time period, and output the corresponding control signals Cm1 and Cm2 to the multiplexer 122a and the multiplexer 122b of the multiplexing circuit 122, so as to control the internal conduction path thereof to connect the input terminal and the output terminal.

In the example shown in fig. 3A, the switches include a first switch S1 through a twelfth switch S12.

The first switch S1 is electrically connected between the power receiving terminal N0 and the positive electrode (node N3) of the first fly capacitor Cf 1. The second switch S2 is electrically connected between the positive output terminal N1 and the positive terminal (node N3) of the first fly capacitor Cf 1. The third switch S3 is electrically connected between the positive output terminal N1 and the positive terminal (node N5) of the second fly capacitor Cf 2. The fourth switch S4 is electrically connected between the positive output terminal N1 and the negative terminal (node N4) of the first fly capacitor Cf 1. The fifth switch S5 is electrically connected between the ground GND and the positive electrode (node N5) of the second flying capacitor Cf 2. A sixth switch S6 is coupled between the negative output terminal N2 and the negative terminal (node N4) of the first fly capacitor Cf 1. That is, the sixth switch S6 is electrically connected to the negative output terminal N2 and the negative terminal of the first flying capacitor Cf1 (node N4). The seventh switch S7 is electrically connected between the negative output terminal (node N2) and the negative terminal (node N6) of the second fly capacitor Cf 2. The eighth switch S8 is electrically connected between the ground GND and the negative terminal (node N6) of the second flying capacitor Cf 2. The ninth switch S9 is electrically connected between the ground GND and the positive electrode (node N3) of the first flying capacitor Cf 1. The tenth switch S10 is electrically connected between the power receiving terminal N0 and the positive power output terminal N1. The eleventh switch S11 is electrically connected between the ground GND and the negative terminal (node N4) of the first flying capacitor Cf 1. The twelfth switch S12 is electrically connected between the power receiving terminal N0 and the negative terminal (node N4) of the first fly capacitor Cf 1.

In some embodiments, the first to twelfth switches S1 to S12 may employ power switches (power switches).

In some embodiments, the double supply voltage supply mode, the half supply voltage supply mode, and the one-third supply voltage supply mode may be a highest supply mode, a high supply mode, a medium supply mode, and a low supply mode, respectively.

In the double-power-supply-voltage supply mode, the amplitude detector 124 controls the multiplexer 122a of the multiplexing circuit 122 such that the first clock CK1 is input to the control terminals of the switches S2, S3, S8, and S12. The amplitude detector 124 controls the multiplexer 122b of the multiplexer circuit 122, and inputs the second clock CK2 to the control terminals of the switches S1, S5, S7, and S11. The control terminals of the switches S4, S6 and S9-S10 do not receive any control signal, so that the switches S4, S6 and S9-S10 are open-circuited. That is, in the double supply voltage supply mode, the switches S1-S3, S5, S7-S8, S11-S12 are active, while the switches S4, S6, S9-S10 are inactive.

Therefore, the switches S2, S3, S8 and S12 are turned on in response to the operating phase PH1 of the first clock CK1 to form a first equivalent circuit. Refer to fig. 4. Fig. 4 is a first equivalent circuit diagram of the first operation time of the charge pump circuit 100 controlled by the working phase PH1 of the first clock CK1 in the double supply voltage power mode according to an embodiment of the disclosure.

During the operation phase PH1 of the first clock CK1, the first fly capacitor Cf1 is coupled between the power receiving terminal N0 and the positive output terminal N1 in reverse. The second flying capacitor Cf2 and the first energy storage capacitor Cf1 are connected in parallel in the forward direction between the positive output terminal N1 and the ground terminal GND. That is, the positive electrode (node N3) of the first flying capacitor Cf1 is coupled to the positive output terminal N1, and the negative electrode (node N4) of the first flying capacitor Cf1 is coupled to the power receiving terminal N0. The positive terminal (node N5) of the second flying capacitor Cf2 is coupled to the positive output terminal N1, and the negative terminal (node N6) of the second flying capacitor Cf2 is coupled to the ground GND. At this time, the negative output terminal N2 is only directly coupled to the second storage capacitor Cp 2.

In the first equivalent circuit of the double power supply voltage supply mode, the voltage across Vcf2 of the second flying capacitor Cf2 and the voltage across the first energy storage capacitor Cp1 are equal to the terminal voltage of the positive output terminal N1 (i.e., the positive output voltage VPP). The terminal voltage of the positive electrical output terminal N1 (i.e., the positive output voltage VPP) is the sum of the voltage Vcf1 across the first fly capacitor Cf1 plus the supply voltage VDD. The second storage capacitor Cp2 is floating between the negative output terminal N2 and the ground terminal GND.

Thus, the following (formula 1) and (formula 2) can be obtained.

VPP ═ Vcf1+ VDD (equation 1)

Vcf2 ═ VPP (formula 2)

Furthermore, the switches S1, S5, S7 and S11 are turned on in response to the operating phase PH2 of the second clock CK2 to form a second equivalent circuit. Refer to fig. 5. Fig. 5 is a second equivalent circuit diagram of the second operation time of the charge pump circuit 100 controlled by the working phase PH2 of the second clock CK2 in the double supply voltage power supply mode according to the embodiment of the disclosure.

The first flying capacitor Cf1 is coupled in forward direction between the power receiving terminal N0 and the ground terminal GND during the operating phase PH2 of the second clock CK 2. The second flying capacitor Cf2 is coupled in reverse between the negative output terminal N2 and the ground terminal GND. That is, the positive terminal (node N3) of the first flying capacitor Cf1 is coupled to the power receiving terminal N0, and the negative terminal (node N4) of the first flying capacitor Cf1 is coupled to the ground GND. The positive terminal (node N5) of the second flying capacitor Cf2 is coupled to the ground GND, and the negative terminal (node N6) of the second flying capacitor Cf2 is coupled to the negative output terminal N2.

In the second equivalent circuit of the double-power-supply-voltage power supply mode, the voltage across the second flying capacitor Cf2 is inversely dropped on the second energy-storing capacitor Cp2 (i.e., the negative output voltage VEE). The voltage across the first flying capacitor Cf1 is the supply voltage VDD.

Thus, the following (formula 3) and (formula 4) can be obtained.

Vcf1 ═ VDD (equation 3)

VEE ═ Vcf2 (formula 4)

From (equation 1) to (equation 4), in the double-power-supply-voltage power supply mode, the positive output voltage VPP outputted from the positive output terminal N1 is (2) power supply voltage, i.e., 2VDD, and the negative output voltage VEE outputted from the negative output terminal N2 is (-2) input power supply voltage, i.e., -2 VDD.

In addition, when the charge pump circuit 100 is powered in the double power supply voltage supply mode, the pump cell circuit 120 alternately operates in the first operation time and the second operation time corresponding to the first clock and the second clock. Therefore, the electrical connection relationship among the power receiving terminal N0, the ground terminal GND, the positive output terminal N1, the negative output terminal N2, the positive electrode of the first flying capacitor Cf1 (node N3), the negative electrode of the first flying capacitor Cf1 (node N4), the positive electrode of the second flying capacitor Cf2 (node N5), and the negative electrode of the second flying capacitor Cf2 (node N6) repeatedly and alternately presents the first equivalent circuit and the second equivalent circuit.

Similarly, in the power supply mode, the amplitude detector 124 controls the multiplexer 122a of the multiplexing circuit 122 such that the first clock CK1 is input to the control terminals of the switches S1, S3, S8, S10, S11. The amplitude detector 124 controls the multiplexer 122b of the multiplexer circuit 122, and inputs the second clock CK2 to the control terminals of the switches S5, S6, S7, S9, and S10. The control terminals of the switches S2 and S4 do not receive any control signal, so that the switches S2 and S4 are open-circuited.

In this case, the positive output voltage VPP outputted from the positive electric output terminal N1 is the power supply voltage VDD, and the negative output voltage VEE outputted from the negative electric output terminal N2 is (-) power supply voltage, i.e., -VDD.

In the half-mains voltage supply mode, the amplitude detector 124 controls the multiplexer 122a of the multiplexing circuit 122 such that the first clock CK1 is input to the control terminals of the switches S1, S3, S4, and the switch S8. The amplitude detector 124 controls the multiplexer 122b of the multiplexer circuit 122, and inputs the second clock CK2 to the control terminals of the switches S5, S6, S7, and S9. The control terminals of the switches S2, S10, and S11 do not receive any control signal, so that the switch S2 and the switches S10 to S11 are turned off. In this case, the positive output voltage VPP outputted from the positive electric output terminal N1 is (1/2) the power supply voltage VDD/2, and the negative output voltage VEE outputted from the negative electric output terminal N2 is (-1/2) the power supply voltage VDD/2.

In the one-third power supply mode, the amplitude detector 124 controls the multiplexer 122a of the multiplexing circuit 122 such that the first clock CK1 is input to the control terminals of the switches S1, S3, S4, and S8. The amplitude detector 124 controls the multiplexer 122b of the multiplexer circuit 122, and inputs the second clock CK2 to the control terminals of the switches S2, S5, S6, and S7. The control terminals of the switches S9, S10, and S11 do not receive any control signal, so that the switches S9 to S11 are turned off. In this case, the positive output voltage VPP outputted from the positive electric output terminal N1 is (1/3) the power supply voltage, i.e., VDD/3, and the negative output voltage VEE outputted from the negative electric output terminal N2 is (-1/3) the input power supply voltage, i.e., -VDD/3.

Refer to fig. 6. Fig. 6 is a schematic diagram of an amplifier circuit 600 and a load 610 according to an embodiment of the disclosure.

In one embodiment, the charge pump circuit 100 in fig. 1 can be applied to a driving device including the charge pump circuit 100 and the amplifier circuit 600. Therefore, the aforementioned subsequent stage circuit is the amplifier circuit 600. The amplifier circuit 600 mainly includes an amplifier AMP having two input terminals, an output terminal, and two power source terminals. Wherein the output of the amplifier AMP is coupled to a load 610. Taking the earphone driving device as an example, the load 610 may be an earphone.

The positive electric output terminal N1 and the negative electric output terminal N2 of the charge pump circuit 100 are coupled to the two power source terminals of the amplifier AMP, respectively. The positive output voltage VPP and the negative output voltage VEE output via the positive electric output terminal N1 and the negative electric output terminal N2 are respectively applied to both power supply terminals of the amplifier AMP as electric power required for the operation of the amplifier AMP.

With power supplied from the charge pump circuit 100, the input signal Vin received by the amplifier circuit 600 is input to the input terminal of the amplifier AMP through two resistors. The amplifier AMP processes the signal received at the input terminal to generate an output signal Vout, and provides the output signal Vout to the load 610.

The amplitude detector 124 of the charge pump circuit 100 may be electrically connected to the input terminal and/or the output terminal of the amplifier AMP, and may detect the input signal Vin and/or the output signal Vout of the amplifier AMP correspondingly. For example, the amplitude detector 124 is electrically connected to the input end of the amplifier AMP to detect the amplitude of the input signal Vin of the amplifier AMP.

When the amplitude detector 124 detects that the amplitude of the input signal Vin is less than or equal to the first threshold value for a preset period of time, the amplitude detector 124 controls the pump unit circuit 120 to perform a one-third power supply voltage supply mode to apply the positive output voltage VPP and the negative output voltage VEE of the power supply voltage VDD (+1/3) times and (-1/3) times, respectively, to the power supply terminal of the amplifier AMP.

When the amplitude detector 124 detects that the amplitude of the input signal Vin is greater than the first threshold value and less than or equal to the second threshold value, the amplitude detector 124 controls the pump unit circuit 120 to perform the half power supply voltage supply mode to apply the positive output voltage VPP and the negative output voltage VEE of the power supply voltage VDD (+1/2) times and (-1/2) times, respectively, to the power supply terminal of the amplifier AMP.

When the amplitude detector 124 detects that the amplitude of the input signal Vin is greater than the second threshold value and less than or equal to the third threshold value, the amplitude detector 124 controls the pump unit circuit 120 to perform the power supply voltage supply mode to apply the positive output voltage VPP and the negative output voltage VEE of (+1) times and (-1) times, respectively, the input power supply voltage VDD to the power supply terminal of the amplifier AMP.

When the amplitude detector 124 detects that the amplitude of the input signal Vin is greater than the third threshold value, the amplitude detector 124 controls the pump unit circuit 120 to perform the double power supply voltage supply mode to apply the positive output voltage VPP and the negative output voltage VEE of the input power supply voltage VDD (+2) times and (-2) times, respectively, to the power supply terminal of the amplifier AMP.

In this way, the magnitudes of the positive output voltage VPP and the negative output voltage VEE can be dynamically adjusted according to the magnitude of the input signal Vin.

Please note that, although the disclosure takes the first clock and the second clock whose working phases are not overlapped, the two flying capacitors (the first flying capacitor and the second flying capacitor), the two energy storage capacitors (the first energy storage capacitor and the second energy storage capacitor), and the plurality of switches as an example, the disclosure is not limited thereto.

Refer to fig. 7. Fig. 7 is a flowchart of a power supply method 700 for dynamically adjusting voltage according to an embodiment of the disclosure.

In addition to the foregoing devices, the present disclosure also discloses various power supply methods 700 for dynamically adjusting voltage, which can be applied to, for example (but not limited to) the charge pump circuit 100 of fig. 1. One embodiment of a power supply method 700 for dynamically adjusting voltage is shown in fig. 7, and comprises the following steps:

s710: the power receiving terminal N0 receives the power voltage VDD, the positive output terminal N1 outputs the positive output voltage VPP, and the negative output terminal N2 outputs the negative output voltage VEE.

S720: the first storage capacitor Cp1 is electrically coupled between the positive output terminal N1 and the ground terminal GND, and the second storage capacitor Cp2 is electrically coupled between the negative output terminal N2 and the ground terminal GND.

S730: in the double-power-supply-voltage supply mode, the pump unit circuit 120 has a first connection relationship between the first flying capacitor Cf1 and the second flying capacitor Cf2 and the power receiving terminal N0, the ground terminal GND, the positive output terminal N1 and the negative output terminal N2 at a first operation time, and a second connection relationship at a second operation time.

In more detail, during the first operation time in the double power voltage supply mode, the pump unit circuit 120 electrically couples the first flying cathode of the first flying capacitor Cf1 to the power receiving terminal N0, electrically couples the second flying cathode of the second flying capacitor Cf2 to the ground GND, and electrically couples the first flying anode of the first flying capacitor Cf1 and the second flying anode of the second flying capacitor Cf2 to the positive power output terminal N1.

Further, during a second operation time in the double power supply mode, the pump unit circuit 120 electrically couples the first flying cathode of the first flying capacitor Cf1 and the second flying cathode of the second flying capacitor Cf2 to the ground GND, electrically couples the first flying cathode of the first flying capacitor Cf1 to the positive output terminal N1, and electrically couples the second flying cathode of the second flying capacitor Cf2 to the negative output terminal N2.

S740: the pump unit circuit 120 is operated alternately for the first operation time and the second operation time in the double power supply mode, so that the positive output terminal N1 and the negative output terminal N2 respectively output the positive output voltage VPP and the negative output voltage VEE which are two times of the power supply voltage VDD.

In summary, the charge pump circuit and the power supply method for dynamically adjusting voltage thereof in the disclosure can dynamically adjust the output voltage according to different output driving requirements, and achieve the technical effect of saving power while driving a high impedance load.

Although the embodiments of the present disclosure have been described above, the embodiments are not intended to limit the present disclosure, and those skilled in the art can make variations on the technical features of the present disclosure according to the explicit or implicit contents of the present disclosure, and all such variations may fall within the scope of patent protection sought by the present disclosure, in other words, the scope of patent protection of the present disclosure should be subject to the claims of the present specification.