阅读说明：本技术 连接器以及具有表面接地平面的印刷电路板 (Connector and printed circuit board with surface ground plane ) 是由 培鲁兹·阿姆雷西 谢璞 大卫·L·布伦克尔 蒂莫西·R·麦克莱兰德 滕凯·陈 于 2019-09-25 设计创作，主要内容包括：连接器(1300)和印刷电路板的组合包括增加电气耦合的相对的电气接地结构。所述组合还减少在一印刷电路板中的信号之间的所不想要的串扰。(The combination of the connector (1300) and the printed circuit board includes opposing electrical grounding structures that increase electrical coupling. The combination also reduces unwanted cross-talk between signals in a printed circuit board.)

1. A printed circuit board comprising:

a top surface for mounting a connector, said top surface having a plurality of signal mounting locations for said connector, a plurality of ground mounting locations for said connector, a plurality of antipads surrounding said plurality of signal mounting locations, and a mounting area having an outer boundary formed between adjacent ones of said plurality of signal mounting locations; and

a ground plane covering the top surface at the mounting area, wherein a surface area of the ground plane covers at least 50% of a total surface area of the mounting area.

2. The printed circuit board of claim 1, wherein an outer boundary of the mounting area is further formed between outermost adjacent ground mounting locations of the plurality of ground mounting locations.

3. The printed circuit board of claim 1, wherein the ground mounting locations comprise ground vias and the signal mounting locations comprise signal vias.

4. The printed circuit board of claim 1, wherein the ground mounting locations comprise ground surface mounting pads and the signal mounting locations comprise signal surface mounting pads.

5. The printed circuit board of claim 1, wherein the plurality of antipads includes at least one antipad surrounding a pair of the plurality of signal mounting locations.

6. The printed circuit board of claim 1, wherein the plurality of antipads includes an antipad surrounding each of the plurality of signal mounting locations.

7. The printed circuit board of claim 1, wherein the surface area of the ground plane covers at least 60% of the total surface area of the mounting area.

8. The printed circuit board of claim 1, wherein the surface area of the ground plane covers at least 70% of the total surface area of the mounting area.

9. The printed circuit board of claim 1, wherein the surface area of the ground plane covers at least 80% of the total surface area of the mounting area.

10. The printed circuit board of claim 1, wherein the surface area of the ground plane covers at least 90% of the total surface area of the mounting area.

11. A printed circuit board comprising:

a top surface for mounting a connector, said top surface having a plurality of signal mounting locations for said connector, a plurality of ground mounting locations for said connector, a plurality of antipads surrounding said plurality of signal mounting locations, and a mounting area, said mounting area having an outer boundary formed between outermost signal mounting locations; and

a ground plane overlying the top surface of the mounting region except for vias and the plurality of antipads, wherein a surface area of the ground plane covers at least 50% of a total surface area of the mounting region.

12. The printed circuit board of claim 11, wherein the ground mounting locations comprise ground vias and the signal mounting locations comprise signal vias.

13. The printed circuit board of claim 11, wherein the ground mounting locations comprise ground surface mounting pads and the signal mounting locations comprise signal surface mounting pads.

14. The printed circuit board of claim 11, wherein the plurality of antipads includes at least one antipad surrounding a pair of the plurality of signal mounting locations.

15. The printed circuit board of claim 11, wherein the plurality of antipads includes an antipad surrounding each of the plurality of signal mounting locations.

16. The printed circuit board of claim 11, wherein the surface area of the ground plane covers at least 60% of the total surface area of the mounting area.

17. The printed circuit board of claim 11, wherein the surface area of the ground plane covers at least 70% of the total surface area of the mounting area.

18. The printed circuit board of claim 11, wherein the surface area of the ground plane covers at least 80% of the total surface area of the mounting area.

19. The printed circuit board of claim 11, wherein the surface area of the ground plane covers at least 90% of the total surface area of the mounting area.

20. A connector, comprising:

a plurality of wafers configured to form a mounting face and a mating face, the mounting face further configured for mounting on a top surface of a printed circuit board, the printed circuit board having a ground plane with a surface area covering at least 50% of a total surface area of an area opposite a mounting area of the mounting face, the mounting face including at least one conductive surface electrically coupled to a ground, the connector configured for mounting on the circuit board such that the at least one conductive surface is within 0.3mm of the ground plane and further configured to operate at a data rate of at least 56Gbps,

wherein the plurality of wafers includes a plurality of signal wafers configured to support a plurality of signal terminals, and each of the plurality of signal terminals includes a tail portion, a contact portion, and a body portion extending between the contact portion and the tail portion such that (i) the contact portions of the plurality of signal terminals are adjacent to the mating face and (ii) the tail portions of the signal terminals are adjacent to the mounting face and form a mounting area on the mounting face.

21. The connector of claim 20, wherein the plurality of wafers includes a plurality of ground wafers.

22. The connector of claim 21, wherein the at least one conductive surface electrically coupled to a ground includes plated edges of the plurality of ground wafers.

23. The connector of claim 22, wherein the first and second connectors are integrally formed,

wherein the plurality of ground wafers includes a plurality of trailing inserts;

and wherein the at least one conductive surface electrically coupled to a ground further comprises portions of the tail insert positioned along the mounting region.

24. The connector of claim 22, wherein the plurality of wafers includes a pair of ground wafers and a pair of signal wafers, the pair of signal wafers being positioned adjacent to each other and the pair of ground wafers being positioned on either side of the adjacent pair of signal wafers.

25. The connector of claim 22, wherein the ground wafer comprises plated plastic.

26. The connector of claim 25, wherein the ground wafer includes a tail insert.

27. The connector of claim 22, further comprising a plurality of transverse grounding blades electrically coupling the plurality of grounding wafers.

28. The connector of claim 27, wherein the lateral grounding blade includes a tail configured to electrically couple to the ground plane.

29. The connector of claim 28, wherein the ground wafer includes a tail insert and the lateral ground blade interlocks with the tail insert.

30. The connector of claim 27, wherein the lateral grounding blade extends in a non-perpendicular direction across the plurality of grounding wafers.

31. A method for reducing crosstalk between signals of a Printed Circuit Board (PCB), comprising:

forming a printed circuit board having a grounded frame mounting area and an active port area, wherein the active port area comprises a total surface area of a plurality of antipads and a total surface area of a plurality of signal mounting locations on the printed circuit board;

varying a surface area of the ground frame region and varying the active port region to vary crosstalk between signals at the plurality of signal mounting locations.

32. The method of claim 31, further comprising: increasing a surface area of the ground frame region and reducing the active port region to reduce crosstalk between signals at the plurality of signal mounting locations.

Technical Field

The present disclosure relates to the field of connectors, and more particularly to connectors and combinations of Printed Circuit Boards (PCBs) and connectors for use in transferring data at high data rates.

Background

This section introduces aspects that may be helpful in facilitating a better understanding of the described aspects of the invention. Accordingly, the statements in this section are to be read in this light and are not to be construed as admissions of what exists or does not exist in the prior art.

PCBs used in high-speed communication applications may be connected using suitable connectors. Typically, many PCBs may be spaced apart by only a few millimeters (mm), with their arrangement being close or dense. This presents a greater challenge when multiple PCBs are arranged such that the required pitch density in a given PCB carrying multiple discrete signals may approach or exceed operating differential signal pairs within 1-3mm of each other. The ability to eliminate or substantially reduce inductive or capacitive coupling of one differential signal pair being transferred on the same PCB and so closely aligned with another adjacent differential signal pair on the same PCB is very challenging. Additionally to this challenge, as the speed of signals being communicated by a PCB increases, the tendency for unwanted coupling (often referred to as unwanted noise or simply "crosstalk") also increases.

In addition, existing connector-to-PCB designs mate the signal pin locations and ground pin locations of a pin array (footprint) of a connector with corresponding receiving structures, such as conductive press-fit pin holes for the respective signal locations and ground locations. In addition, conductive ground connecting vias may be used within a PCB to electrically connect selected ground plane assignments together to create a robust low impedance ground loop. However, these existing designs do not adequately address the problem of unwanted noise coupling.

Disclosure of Invention

The present inventors describe various exemplary PCB and connector combinations and related methods, particularly (amplitude other connections) that provide for reducing cross-talk between signals within a PCB and increasing coupling between a connector and a ground structure of a PCB by varying the surface area of a ground frame mounting area and the surface area of an active port area of a PCB (wherein an active port area includes a total surface area of a plurality of antipads and a total surface area of signal mounting locations on the PCB).

An embodiment of a PCB may comprise: a top surface for mounting a connector, said top surface having a plurality of signal mounting locations for said connector, a plurality of ground mounting locations for said connector, a plurality of antipads surrounding said plurality of signal mounting locations, and a mounting area having an outer boundary formed between outermost adjacent ones of said plurality of signal mounting locations, wherein said mounting area includes a plurality of signal mounting locations; a ground plane covering the top surface at the mounting area, the top surface at the mounting area further housing (accmodating) a plurality of ground mounting locations and a plurality of signal mounting locations and including a plurality of antipads surrounding a plurality of signal mounting locations, wherein a surface area of the ground plane covers at least 50% of a total surface area of the mounting area.

In an embodiment, an outer boundary of the mounting area may be formed between adjacent ground mounting locations that are outermost of the plurality of ground mounting locations, wherein the mounting area includes a plurality of ground mounting locations.

In some embodiments, (i) the ground mounting locations may include ground vias and the signal mounting locations may include signal vias; or (ii) the ground mounting location may comprise a ground surface mounting pad and the signal mounting location may comprise a signal surface mounting pad; or (iii) the plurality of antipads may include at least one antipad surrounding a pair of signal mounting locations of the plurality of signal mounting locations; or (iv) the plurality of antipads includes an antipad that may surround each of the plurality of signal mounting locations.

In some embodiments described herein, the surface area of the ground plane may cover: (i) at least 60% of the total surface area of the mounting area, or (ii) at least 70% of the total surface area of the mounting area, or (iii) at least 80% of the total surface area of the mounting area, or (iv) at least 90% of the total surface area of the mounting area.

An alternative exemplary PCB may include: a top surface for mounting a connector, said top surface having a plurality of signal mounting locations for said connector, a plurality of ground mounting locations for said connector, a plurality of antipads surrounding said plurality of signal mounting locations, and a mounting area having an outer boundary formed between outermost signal mounting locations, wherein said mounting area includes a plurality of signal mounting locations; and a ground plane overlying the top surface of the mounting region except for vias and the antipads, wherein a surface area of the ground plane covers at least 50% of a total surface area of the mounting region.

Such exemplary PCBs may further include (i) the ground mounting locations include ground vias and the signal mounting locations include signal vias, or (ii) the ground mounting locations include ground surface mounting pads and the signal mounting locations include signal surface mounting pads, or (iii) the plurality of antipads include at least one antipad surrounding a pair of the plurality of signal mounting locations, or (iv) the plurality of antipads include an antipad surrounding each of the plurality of signal mounting locations.

Similar to the previous embodiment, in an alternative PCB: (i) the surface area of the ground plane may cover at least 60% of the total surface area of the mounting area, or (ii) the surface area of the ground plane may cover at least 70% of the total surface area of the mounting area, or (iii) the surface area of the ground plane may cover at least 80% of the total surface area of the mounting area, or (iv) the surface area of the ground plane may cover at least 90% of the total surface area of the mounting area.

In addition to the inventive PCB, the inventors illustrate the inventive connector. An exemplary connector may include: a plurality of wafers configured to form a mounting face and a mating face, the mounting face further configured for mounting on a top surface of a printed circuit board, the printed circuit board having a ground plane with a surface area covering at least 50% of a total surface area of an area opposite a mounting area of the mounting face, the mounting face including at least one conductive surface electrically coupled to a ground, the connector configured for mounting on the circuit board such that the at least one conductive surface is within 0.3mm of the ground plane and further configured to operate at a data rate of at least 56Gbps, wherein the plurality of wafers include a plurality of signal wafers configured to support a plurality of signal terminals, and each of the plurality of signal terminals includes a tail portion, a contact portion, and a body portion extending between the contact portion and the tail portion, such that (i) the contact portions of the plurality of signal terminals are adjacent the mating face and (ii) the tail portions of the signal terminals are adjacent the mounting face and form a mounting area on the mounting face.

Further, in the exemplary connector: (i) the plurality of wafers may include a plurality of ground wafers; (ii) the at least one conductive surface electrically coupled to a ground may include plated edges of the plurality of ground wafers; (iii) the plurality of ground wafers may include a plurality of tail inserts, wherein the at least one conductive surface electrically coupled to a ground further includes portions of the tail inserts positioned along the mounting region; (iv) the plurality of wafers may include a pair of ground wafers and a pair of signal wafers positioned adjacent to each other with the pair of ground wafers positioned on either side of the pair of adjacent signal wafers.

In some embodiments, the ground wafer may include: (i) plating plastic; and/or (ii) a caudal insert.

The example connector as described herein above may also include a plurality of lateral grounding blades for electrically coupling the plurality of grounding wafers, wherein the lateral grounding blades may include tails configured to electrically couple to the ground plane, and the grounding wafers may include tail inserts. The lateral grounding blade may interlock with the tail insert.

In alternative embodiments, the lateral grounding blade may extend in a non-perpendicular direction across the plurality of grounding wafers.

In addition to the inventive PCB and connector, the inventors also describe the method of juxtaposition and involvement of the inventive PCB and connector as described above and elsewhere herein.

In addition, the present inventors describe methods for reducing crosstalk between signals of a PCB. One such method may include: forming a PCB having a grounded frame mounting area and an active port area, wherein the active port area comprises a total surface area of a plurality of antipads and a total surface area of a plurality of signal mounting locations on the PCB; and varying a surface area of the ground frame region and varying the active port region to vary crosstalk between signals at the plurality of signal mounting locations.

More particularly, the exemplary method may further comprise: increasing a surface area of the ground frame region and reducing the active port region to reduce crosstalk between signals at the plurality of signal mounting locations.

Drawings

The present invention is illustrated by way of example and not limited in the accompanying figures in which like references indicate similar elements and in which:

fig. 1-33 illustrate various embodiments of the present invention that reduce unwanted coupled noise, particularly that can be used to support high data rate functions and performance of certain embodiments.

Further, fig. 1-5 illustrate exemplary configurations of receptacle mounted on an exemplary PCB according to embodiments of the present invention, and fig. 6 illustrates an exemplary connector including more than one group of wafers, where each group may include more than one ground wafer and signal wafer arranged to provide more than one ground-signal-ground arrangement or pattern in which the presence of ground pins may be repeated to form a gssggsg pattern or represented in a more compact GSSGSSG repeating pattern (where "G" represents "ground" and "S" represents "signal"). Fig. 8-11 illustrate arrangements of tail inserts, grounding blades, ground planes, ground mounting locations, and signal terminal pairs according to embodiments of the present invention. Fig. 12 and 14 illustrate an exemplary PCB having an overlaid (overlapping) antipad and a mounting surface conductive surface (e.g., a rim of a ground wafer, a lateral ground blade) according to embodiments of the invention, and fig. 13 illustrates an exemplary arrangement of a PCB and connector according to an embodiment of the invention in which a docking connector having a conductive shield wafer actually establishes a conductive ceiling between a plurality of active signal ports and the PCB surface actually establishes a conductive floor between the plurality of active signal ports, such that when the connectors are engaged at a defined height from the PCB surface, the opposing connector and PCB ground surface form a substantially closed hole/waveguide between the plurality of active signal ports, thereby electrically isolating the plurality of active signal ports from one another within a bandwidth of the intended operating frequency. Fig. 15 shows a cut-away view of a connector mounted to a PCB showing the engagement of a plug module, connector and spacer pads extending over other copper layers of the PCB. Fig. 16-20 illustrate four different exemplary PCBs and corresponding mounting surfaces, wherein a surface area of each mounting surface includes a ground plane and a plurality of antipads, wherein the surface area of the ground plane covers a percentage of a total surface area of a corresponding mounting area and a surface area of the plurality of antipads covers a percentage of the total surface area of the mounting area, in accordance with embodiments of the present invention. Fig. 21-32 show example graphs of insertion loss, crosstalk, impedance, and return loss for the four example PCBs of fig. 16-20 and corresponding mounting surfaces.

In addition, fig. 33 shows an enlarged perspective cut-away view of a portion of a mounting face of a connector mounted on a circuit board according to an embodiment of the present invention.

Specific embodiments of the present invention are disclosed below with reference to the various figures and sketches. The specification and drawings have been drafted to enhance understanding. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements and well-known elements that are advantageous or even necessary to a commercially successful implementation may not be shown so that a less obstructed and more clearly presented embodiment may be achieved.

Detailed Description

It is submitted with the understanding that it will be readily apparent to those skilled in the art from the description and the drawings that will be used to best enable the manufacture, use and best practice of the invention. Those skilled in the art will recognize that various modifications and changes may be made to the specific embodiments described herein without departing from the spirit and scope of the present invention. Accordingly, the specification and figures are to be regarded in an illustrative and exemplary rather than a restrictive or all-encompassing sense, and all such modifications to the specific embodiments described herein are intended to be included within the scope of the present invention. Also, it is to be understood that the following detailed description describes exemplary embodiments and is not intended to be limited to the explicitly disclosed combinations. Thus, unless otherwise noted, features disclosed herein may be combined together to form additional combinations not otherwise described or illustrated for the sake of brevity.

As used herein and in the appended claims, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article of manufacture, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article of manufacture, or apparatus. As used herein, the terms "a" (a, an indefinite article before a consonant) or "an" (an, an indefinite article before a vowel) are defined as more than one rather than one. The term "plurality", as used herein, is defined as more than two, rather than two. The term another, as used herein, is defined as at least a second or more. Unless otherwise indicated herein, the use of relational terms, if any, such as "first" and "second," "top" and "bottom," and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship, priority, importance, or order between such entities or actions.

As used herein, the terms "including in participle form" and/or "having in participle form" are defined as comprising in participle form (i.e., open language). As used herein, the term "coupled" means that the energy of an electric field associated with at least a current in one conductor is applied to another conductor that is not galvanically (galvanostically) connected. In other words, the term "coupled in the form of a word" is not limited to a mechanical connection, an electro-fluidic connection, or a field-mediated electromagnetic interaction, but it can include more than one such connection unless the meaning is limited by the context of a particular statement herein.

It should also be noted that more than one exemplary embodiment may be described in terms of a method. Although a method may be described in an exemplary order (i.e., sequentially), it should be understood that such methods may also be performed in parallel, concurrently, or simultaneously. In addition, the various formation steps within a method may be rearranged. A described method may terminate upon completion and may also include additional steps not described herein, for example, if known to those skilled in the art.

As used herein, the term "embodiment" or "exemplary" refers to an example that falls within the scope of the present invention.

The inventors have discovered that the configuration of the connector and circuit board, when used in conjunction with one another, can reduce unwanted coupled noise, among other advantages.

As further described herein, the inventive embodiments mate the ground structure of the connector to capacitively mate with a similarly aligned ground structure on an interface PCB. In addition to galvanic (galvanic) signal and ground connections, the inventive mating ground structure adds an additional electrical element (capacitive ground coupling) to the connector pin arrangement.

Referring now to fig. 1, an exemplary receptacle 500 of a connector is shown mounted on a PCB100 such that the receptacle is arranged at a right angle to the PCB100 to receive a plug module (not shown) for the receptacle 500. Although not specifically shown, it should be understood that the same or similar operating mechanism may be employed for a vertical connector (vertical connector) arranged in a direct connector (straight connector). In one embodiment, the receptacle 500 may be formed by a base 502 disposed or positioned within an enclosure 501, the base 502 also serving as a connector 505 (see fig. 2 and 3). The shroud 501 serves to support and control at least the mating plug module (not shown) and the connector, and also serves to provide electromagnetic interference (EMI) protection. The cover 501 also helps to maintain mechanical integrity during application operation.

Referring to fig. 4, in one embodiment, the connector functions to support a plurality of terminals, each including a tail portion 508, a contact portion 506, and a body portion (not shown) between the tail portion 508 and the contact portion 506, the plurality of terminals further functioning to allow the mating plug module to be electrically connected to a PCB (or cable, if a by-pass design is desired). In the exemplary embodiment of fig. 4, the tail 508 may be configured as a press-fit tail. However, in alternative embodiments, the tail portions of the terminals may be configured in various forms other than press-fit to support a desired mounting configuration or arrangement (e.g., surface mount) or interconnection (e.g., to a cable). In the embodiment of fig. 4 (and fig. 5), the socket 500 may be press fit onto a PCB for ease of assembly. Thus, the plurality of terminals of the connector should be aligned with the plurality of terminals on the cage. In one embodiment, the housing 501 may comprise a metal housing. Further, the tails 508 may be arranged in a fairly repeatable layout and may include dimensions similar to one another.

Referring now to fig. 6 and 7, an exemplary connector may include more than one set of wafers 620. In one embodiment, wafer set 620 includes two ground wafers 661, 664 and two signal wafers 662, 663 arranged in a ground-signal-ground pattern (see fig. 7). This particular application may repeat in a GSSGSSG pattern as shown or include additional ground wafers forming a GSSGGSSG repeating pattern (where "G" represents "ground" and "S" represents "signal"). In the illustrated embodiment, the signal wafers 662 and 663 each include an insulative frame (e.g., molded plastic, such as Liquid Crystal Polymer (LCP)) that functions to support the signal terminals therein (each having a contact portion and an associated tail portion, as shown in fig. 7). In the embodiment shown in fig. 7, ground wafers 661 and 664 are formed of metalized plastic to enable conduction and commoning. Further, such metallized plastic may be: (1) doping to become sufficiently conductive, (2) plating, (3) doping and plating, (4) inking, (5) etching, or (6) some combination of any of the foregoing, to function at least with a formed generally conductive surface. In some embodiments, the plated metallized plastic may cover the entire surface area of a ground wafer, in the case of plating, or may cover less than the entire surface area of a ground wafer (i.e., selective plating). Thus, in some embodiments, the entire surface of an insulating frame (e.g., molded plastic such as LCP) may be plated to become conductive. Thus, in an embodiment, the ground wafer may initially include a stamped/formed conductive plate (possibly including ground contacts and tail features) that is overmolded (over-molded) with plastic and then plated. The contact and/or tail features may be inserted into the ground wafer before or after plating, if desired. The features of these conductive tails function to provide a direct conductive path between the ground wafer and an interface PCB.

In some embodiments, the metal contact inserts 668 and metal tail inserts 669 may then be plugged (stuck) or inserted (inserted) into the cavities in the ground wafers 661, 664 (as shown after plugging in fig. 7) rather than being formed by an over-molding process (like the terminals of the signal wafers 662, 663). Such insertion of the insert (whether for the contact portions or the tail portions or both) can be made with respect to all or any of the ground wafers 661, 664. Similar contacts and/or tail inserts may be formed for various signal wafers or power wafers and then inserted into those wafers as desired. Additionally, the tail insert may comprise a press-fit tail insert or a surface mount tail insert. In further embodiments, rather than employing tail inserts, the ground wafers 661, 664 may include plated or metalized conductive plastic tails. Such tails may be formed as part of any molded wafer and may alternatively be conductive or made conductive (e.g., plated).

As shown, the exemplary ground wafers 661 and 664 may include a number of raised areas (nubs (nub))680, stakes 681a and recesses 681b for interfacing with one another when the signal wafers 662, 663 are sandwiched therebetween. In some embodiments, the stub 681a and recess 681b of one ground wafer may be formed or arranged to be an interference fit with an opposing ground wafer for sandwiching. Further, in some embodiments, the raised region of each ground wafer may be sufficient to substantially fill the void (void) of the sandwiched pair of signal wafers. Also, according to this embodiment, some or all of the ground wafer recesses 681b may alternatively be formed as holes in one ground wafer for receiving the stub portions 681a of the opposing ground wafer. Therefore, it is to be understood that the arrangement of the stub 681a and the recess 681b shown in fig. 7 is only an example, and many variations are possible.

In one embodiment, it may be desirable to metalize (i.e., include metalized elements) some or all of the raised areas (nubs) 680, stubs 681a, and/or recesses 681b to enable conduction and commoning between the ground wafers 661, 664.

Referring now to fig. 33, an exemplary enlarged cut-away view of an exemplary mounting area of a connector is shown illustrating the mounting of the connector to a PCB according to some embodiments of the present invention. In more detail, a portion of the top surface of the PCB is shown in fig. 33 as including a ground plane 101 and antipads such as antipads 102. Signal mounting locations 103 and ground mounting locations 104 for the connectors are also shown. In the illustrated embodiment, the signal mounting locations 103 include signal vias 103(vias), while the ground mounting locations 104 include ground vias 104. In other embodiments, such as those combining a PCB with a surface mount connector, the signal mounting locations may include signal surface mounting pads and the ground mounting locations may include ground surface mounting pads. Also, although the antipads 102 are shown as surrounding each of two signal mounting locations, in other embodiments, multiple antipads 102 may be joined together rather than a single antipad surrounding two (or possibly more) signal mounting locations. In this exemplary embodiment, the surface area of the ground plane 101 is shown to cover slightly more than 50% of the total surface area of the mounting area, as shown in fig. 33. A mounting area can be defined as the minimum area encompassing all signal mounting locations. Preferably, the surface area of the ground plane covers more than 50%, 60%, 70%, 80% or even 90% of the total surface area of a mounting area. Unless other top surface features are desired (e.g., larger antipads or additional vias), it is desirable that the surface area of the ground plane cover as much of the total surface area of the mounting area as possible.

Referring again to fig. 33, a cut-away view of the mounting area of the connector is shown in which a portion of the signal terminals are shown. In particular, a portion of the tail portion 675 of the signal terminal is shown. In this embodiment, the tail 675 includes a press-fit tail. In other embodiments, the tail may alternatively be configured for surface mounting to a PCB. Also shown are a portion of a ground wafer and tail insert of the connector, such as ground wafer 671 with its tail insert 679, and a portion of a plurality of transverse (transpose) ground blades (blades) 677. In an embodiment, a plurality of transverse ground blades 677 may be arranged or configured to electrically connect all ground wafers 671 that are positioned, for example, substantially perpendicular to all rows of aligned blades 677 (i.e., the geometric plane that includes the blades 677 "crosses" the geometric plane that includes the wafers 671) across (across). It should be understood, however, that the ground blade member does not have to be perpendicular to the ground wafer, but may extend transversely at other angles as desired. Further, according to this embodiment, the lateral grounding blade members 677 may interlock or fit with the tail inserts 679 into slots formed on the grounding wafer 671 or the lateral grounding blade members 677 may be arranged in both ways to employ a grounding wafer that is cross-wise to electrically connect to them (see, e.g., fig. 8-11, where fig. 10 shows a bottom or mounting face of a connector and fig. 11 shows an enlarged view of a portion of fig. 10). Both the lateral grounding blade 677 and the trailing insert 679 may also be electrically coupled to the ground plane 101 through the ground mounting locations 104. In the illustrated embodiment, a plurality of transverse grounding blades (such as transverse grounding blade 677) are located between rows of signal terminal tail pairs 675.

Ground wafer 671 may be formed of metallized plastic to achieve conduction and common. As previously mentioned, the metallized plastic may take various forms. The ground wafer 671 may be plated on its molded plastic frame, including an edge facing its mounting area. The face of the connector facing the mounting area of the connector includes a plurality of conductive surfaces that are electrically coupled to ground, of which the plated edge of the ground wafer is dominant. The tail insert and the portion of the lateral (or transverse) grounding blade positioned along a face of a mounting area may also include a plurality of conductive surfaces that are electrically coupled to ground. However, the plated edge of the ground wafer 671 is significantly larger than the edge of the ground blade or the edge of the trailing insert in terms of surface area, at least for the embodiment shown.

Referring now to fig. 12 and 14, exemplary configurations are shown in which a PCB has a plurality of antipads 1202 overlapping each other and a conductive surface of a mounting area. Fig. 12 shows a portion of the trailing insert 1211 (in the ground wafer) and the edge 1210 of a face of a mounted ground wafer positioned along the mounting surface, while fig. 14 additionally shows a portion of the transverse ground blade 1220 positioned along the face of the mounting area.

Referring now to fig. 13, a general configuration or arrangement of a combination of a connector 1300 mounted to a PCB 2301 is shown. As shown, because the surface of the connector 1300 is not flush with (i.e., in contact with) the surface of the PCB 2301, there is a porous/waveguide (waveguide) region 1302 between the surface of the PCB 2301 and the electrically coupled ground structure on the surface of the connector 1300 closest to the PCB 2301. In some embodiments of the present invention, it is desirable that the aperture/waveguide region 1302 be as small as possible to reduce unwanted noise.

More particularly, when a connector is operated at the elevated speeds of 56Gbps-PAM4 to 112Gps-PAM4, as well as other non-modulating applications (such as 56Gbps-NRZ), unwanted noise can become a significant degradation factor limiting operating margin (margin) and functional channel length.

Recognizing this, the inventors provide exemplary embodiments herein in which a connector is combined with a PCB mounting. One such embodiment is illustrated in the aforementioned fig. 33, where a connector may be configured or arranged for mounting more than one of the conductive surfaces that are one face of a mounting area may nominally (nominally) be within 0.3mm of a surface of the PCB's ground plane 101. As such, the underside surface of the ground wafer 671 (hidden from view) may be within 0.3mm of the surface of the portion of the ground plane 101 of the PCB immediately below it. In an alternative embodiment, it is preferable that the conductive surface of the face of the mounting area is in the range of 0.15mm or less from the surface of the ground plane 101.

It will be appreciated that when using the dimensional configurations or arrangements described in the preceding paragraphs, the combined surfaces of the inventive connector and PCB discussed herein may serve to increase their electrical coupling to electrical ground to an improved degree over prior configurations. Furthermore, it should be understood that rather than describing the same improvement in electrical coupling in terms of mechanical dimensions, such improvement may also be described by stating that the proximity between the surface of an inventive ground plane of a PCB and the inventive conductive surface of a mounting face of a connector should preferably not exceed a wavelength fraction (wavelength fraction) of 1/15 of a wavelength of the highest expected operating frequency in the transition region between the surface of the PCB and the conductive surface of the connector.

It is also believed that the inventive combination of a configured or arranged connector and PCB including a surface of a ground plane of a PCB and a plurality of conductive surfaces of a face of a mounting area of a connector in close proximity (e.g., 0.3mm or less) to one another provides an improved enhanced capacitive coupling over prior configurations. This enhanced capacitive coupling enables a plurality of substantially equipotential plane surfaces to be realized in which a more efficient RF ground coupling is established and maintained between the surface of the PCB and the interface connector, thereby further providing significantly improved noise reduction. Also, it is believed that the enhanced capacitive coupling provided by the inventive connector/PCB combination acts to form an electrical shunt (electrical shunt) between the surface of the ground plane of the PCB and the conductive surface of the face of the mounting area of the connector. The shunt capacitance (shunt capacitance) is considered to be substantially parallel to the direct galvanic conduction (direct galvanic conduction) of the plurality of ground pins (ground pins) that are pressed in. It should be noted that the presence of ground current in the return path of a signal is not always limited to ground pins. Time-varying difference voltages (time-varying difference voltages) can support "local" displacement current differences (displaced currents) that are not effectively transmitted (communicated) to the surface of the PCB, across the conductive plane of the shield wafer, which results in possible voltage differences between the conductive wafer of the connector and the ground plane of the PCB. Recognizing this, the inventors provide embodiments in which the opposing PCB and conductive connector surfaces are sufficiently (substitionallly) close to each other to support a parallel plate capacitance (parallel plate capacitance) between the opposing PCB and conductive connector surfaces, which in turn provides a capacitive coupling path that couples displacement current from the conductive wafer to the PCB's ground plane. The capacitive coupling path operates (works) to keep the voltage difference between the connector and the PCB to a minimum, thereby being substantially equipotential.

Referring now to fig. 15, a cut-away view of a connector 1500 mounted to a PCB 1501 is shown engaging a plug module, connector and spacer pads extending over other copper layers of the PCB on the surface of the PCB, the spacer pads containing active signal mounting locations/ports, thereby forming an active port area. When these active ports extend vertically below the surface of the PCB, they effectively become active cavities (filled with insulation (dielectric) but without copper and surrounded by copper portions of the PCB ground frame (bound). These active cavities can be managed to preserve high speed electrical performance until the desired wiring signal layer is reached.

Referring now to fig. 16-32, arrangements of connectors and various exemplary PCBs according to embodiments discovered by the inventors through simulations are shown. In more detail, fig. 16-19 show four different exemplary PCBs, labeled 1-4, and their corresponding simulated mounting regions, wherein the surface area of each mounting region includes a ground plane having a surface area and a plurality of antipads having a combined antipad surface area. More specifically, the surface area of the ground plane and the surface area of the combined antipad may vary such that the surface area of the ground plane and the surface area of the combined antipad within each mounting region 1-4 are different. Thus, each mounting area 1-4 has a different percentage of ground plane coverage as shown in table 1 below. In other words, as the surface area of the ground plane (expressed as a first percentage of the total possible surface area of each mounting area) increases from PCB1 to PCB4, the surface area of the combined antipad (expressed as a second percentage of the total surface area of each mounting area) decreases. It should be noted that the mounting areas of the CB 1-4 comprise different spacer disk shapes and sizes corresponding to the surface areas of different spacer disks.

Table 1: exemplary antipad areas for PCBs 1-4 in FIGS. 16-32

It should be understood that the values in table 1 are exemplary. Further, the exemplary ground enclosure percentage is calculated after removing the area dedicated to the active signal ports (see explanation below). The percentage of the footprint of the grounding receptacle corresponds to the area dedicated to a surface ground plane area compared to the maximum area within a specified grounding receptacle boundary.

FIG. 20 shows all four exemplary different PCB board mounting areas for CBS 1-4 side by side. Referring to CB4 in fig. 20, an exemplary surface area of a mounting area 4000 of a ground frame, antipads 4001a-n plus signal mounting location areas 4002a-n is shown. The combined surface areas of the isolator plate and signal mounting location form an "active port area" that is excited by signal energy. In other words, the exemplary surface areas 4001a-n of the spacer disks (where "n" represents the last spacer disk) and the exemplary surface areas 4002a-n of the signal mounting locations 4002a-n (where "n" represents the last signal mounting location) combine, wherein the total surface area of the spacer disks 4001a-n and the total surface area of the signal mounting locations 4002a-n form an active port area. One of the objects of the present invention is to inhibit a signal in one active port region from coupling to a signal in another active port region.

It should be understood that a "first" percentage of the total surface area of each grounded frame mounting area described herein may be calculated by subtracting the surface area of the active port area from the total surface area of the grounded frame mounting area. Thus, as the first percentage increases in the respective PCB 1-4, the second percentage, which is the active port area (4001a-n +4002a-n), decreases in the respective PCB 1-4. Further, as the occupancy percentage of the ground enclosure increases, the crosstalk decreases.

Fig. 21-32 show exemplary graphs of insertion loss, crosstalk, impedance, and return loss for each of the four exemplary PCBs in fig. 16-20 with a corresponding mounting surface based on simulations completed by the inventors. It will be clear from the graphs in fig. 21-32 that PCBs No. 3 and No. 4 (which contain a larger ground plane surface area due to the larger percentage of the total surface area of the respective mounting areas than PCBs No. 1 and No. 2) provide reduced crosstalk compared to PCBs No. 1 and No. 2. Thus, as the inventive ground plane surface area increases as a percentage of the total surface area of the respective mounting area increases and the total surface area of the antipad plus signal mounting location (i.e., active port area) decreases as a percentage of the total surface area of the respective mounting area decreases, unwanted crosstalk decreases. The inventors have also noted that although crosstalk gradually decreases as the percentage of the footprint of the grounded enclosure increases, the impedance of the signal lines may not optimally match the use of the largest decreasing area of the antipads. As a result, the exemplary antipad design shown in PCB 3 (shown in fig. 20) exhibits improved impedance matching performance compared to the antipad design shown in PCB4 (see fig. 27-29). Thus by varying the surface area of the antipad and the percentage of grounded enclosure, the present inventors have provided an inventive method to determine the performance tradeoff of achieving reduced noise coupling while balancing the operational performance of the antipad with ground coupling for improved impedance matching. In this manner, good impedance matching and reduced noise can be balanced at the same time to achieve overall performance. A further advantage of the inventive methods described herein is that they provide the ability to effectively balance the two aspects of reduced noise coupling and impedance matching to optimize a connector and associated PCB interface for overall improved signal-to-noise ratio transmission and impedance matching performance. In this manner, it can be seen that the antipad design shown in the exemplary PCB 3 shown in fig. 20 provides good impedance matching while at the same time providing a very good level of noise rejection.

Although the benefits, advantages, and solutions to problems have been described above with regard to specific embodiments of the present invention, it should be understood that such benefits, advantages, and solutions, and any element(s) that may cause or result in such benefits, advantages, or solutions, or cause such benefits, advantages, or solutions to become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims appended to or derived from this disclosure.