阅读说明：本技术 半导体设备封装及其制造方法 (Semiconductor device package and method of manufacturing the same ) 是由 陈毅 于 2020-10-27 设计创作，主要内容包括：本公开涉及一种包含衬底和插入件的半导体设备封装。所述插入件的底表面通过包含间隔件的导电粘性层附接到所述衬底的顶表面。(The present disclosure relates to a semiconductor device package including a substrate and an interposer. The bottom surface of the insert is attached to the top surface of the substrate by a conductive adhesive layer containing spacers.)

1. A semiconductor device package, comprising:

a first substrate; and

a first insert;

wherein a bottom surface of the first interposer is attached to a top surface of the first substrate by a first electrically conductive adhesive layer comprising spacers.

2. The semiconductor device package of claim 1, wherein the first conductive adhesive layer is made of a solderable conductive material that includes a spacer.

3. The semiconductor device package of claim 2, wherein the solderable electrically conductive material comprises a thermosetting resin and an electrically conductive material.

4. The semiconductor device package of claim 1, wherein the spacer is in direct contact with the first substrate and a corresponding first interposer.

5. The semiconductor device package of claim 1, wherein each of the first interposers includes a plurality of pads at the bottom surface of the first interposer.

6. The semiconductor device package of claim 5, wherein the pads are arranged in a staggered manner.

7. The semiconductor device package of claim 5, wherein each of the first interposers includes an insulating layer disposed at the bottom surface of the first interposer and covering a periphery of the pad, a corresponding one of the insulating layer and the pad defining a recess that receives the first conductive adhesive layer.

8. The semiconductor device package of claim 1, further comprising a second substrate, wherein a top surface of the first interposer is attached to a bottom surface of the second substrate by a second conductive adhesive layer.

9. The semiconductor device package of claim 8, wherein the second conductive adhesive layer is made of a solder conductive material including a spacer.

10. The semiconductor apparatus package of claim 1, wherein the top surface of the first substrate comprises one or more electronic components.

11. The semiconductor apparatus package of claim 8, wherein the bottom surface of the second substrate comprises one or more electronic components.

12. The semiconductor device package of claim 8, wherein a distance between the bottom surface of the second substrate and the top surface of the first substrate is substantially the same from center to periphery.

13. The semiconductor apparatus package of claim 8, wherein a top surface of the second substrate comprises one or more electronic components.

14. The semiconductor device package of claim 1, further comprising at least two first interposers spaced apart from each other.

15. The semiconductor device package of claim 8, further comprising a second interposer attached to a top surface of the second substrate by a third conductive adhesive layer including spacers.

16. The semiconductor device package of claim 15, further comprising an encapsulation layer encapsulating the first substrate, the second substrate, the first interposer, the second interposer, the first conductive adhesive layer, the second conductive adhesive layer, and the third conductive adhesive layer.

17. The semiconductor device package of claim 16, wherein the encapsulation layer has a planar top surface and a pad of each of the second interposers is exposed from the top surface of the encapsulation layer.

18. A method of manufacturing a semiconductor device package, comprising:

providing a first substrate;

providing an insert; and

forming a spacer in contact with the first substrate and the interposer.

19. The method of claim 18, wherein forming spacers in contact with the first substrate and the interposer comprises:

placing a holder between a first surface of the interposer and a first surface of the first substrate to define a receiving space for a conductive adhesive layer; and

heating the conductive adhesive layer to form the spacer.

20. The method of claim 19, further comprising ensuring that a distance between the first surface of the interposer and the first surface of the first substrate is substantially the same from a center of the interposer to a periphery of the interposer.

Technical Field

The present disclosure relates to a semiconductor device package and a method of manufacturing the same.

Background

In three-dimensional (3D) stacked semiconductor structures, an interposer is typically disposed between two stacked semiconductor substrates to support the substrates and provide electrical connections therebetween. The interposer forms a gap between the substrates for receiving the semiconductor device. The configuration and arrangement of the interposer affects the available surface area of the substrate for mounting the semiconductor device. In addition, for excellent uniformity, the gap should be well controlled to reduce the pitch-off deviation.

Disclosure of Invention

According to some embodiments of the present disclosure, a semiconductor device package includes a first substrate and a first interposer. The bottom surface of the first interposer is attached to the top surface of the first substrate by a first conductive adhesive layer containing spacers.

According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device package includes providing a first substrate, providing an interposer, and forming a spacer in contact with the first substrate and the interposer.

Drawings

Aspects of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

Fig. 2 is a cross-sectional view of another semiconductor device package, according to some embodiments of the present disclosure.

Fig. 3A is an enlarged view of region CS as shown in fig. 2, according to some embodiments of the present disclosure.

Fig. 3B is an enlarged view of region CS as shown in fig. 2, according to some embodiments of the present disclosure.

Fig. 4A is a top view of an insert according to some embodiments of the present disclosure.

Fig. 4B is another top view of an insert according to some embodiments of the present disclosure.

Fig. 4C is another top view of an insert according to some embodiments of the present disclosure.

Fig. 4D is another top view of an insert according to some embodiments of the present disclosure.

Fig. 5A, 5B, 5C, and 5D illustrate various stages of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

Common reference numerals are used throughout the drawings and the detailed description to refer to the same or like elements. The disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these components and arrangements are merely examples and are not intended to be limiting. In the present disclosure, in the following description, reference to a first feature being formed over or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

Fig. 1 is a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure. The semiconductor device package 1 includes substrates 10a and 10b, a plurality of electronic components 11a, 11b, 11c, 11d, and 11e, and a plurality of interposers 16a, 16b, 16c, and 16 d.

Each of electronic components 11a, 11b, 11c, 11d, and 11e, and other electronic components shown but not indicated in fig. 1, may include one or more passive electronic components, such as capacitors, resistors, or inductors; and/or one or more active electronic components, such as a processor component, a switch component, or an Integrated Circuit (IC) chip. Each electronic component may be electrically connected into one or more other electronic components and to the substrate 10a or 10b, and the electrical connections may be achieved, for example, by means of flip-chip (flip-chip) or other techniques.

Referring to fig. 1, one or more electronic components, such as 11b, 11c, and 11d, are disposed on the top surface of substrate 10 b. One or more electronic components (e.g., 11a) are disposed on the bottom surface of the substrate 10a, and one or more electronic components (e.g., 11e) are disposed on the top surface of the substrate 10 a.

The interposers 16a and 16b may be disposed between the substrate 10a and the substrate 10b to separate the two substrates 10a and 10b and define a space to accommodate electronic components (e.g., 11b, 11c, and 11d) disposed on the top surface of the substrate 10b and electronic components (e.g., 11a) disposed on the bottom surface of the substrate 10 a. Each of the interposers 16a and 16b has a plurality of pads disposed at a top surface thereof and a plurality of pads disposed at a bottom surface thereof, and may provide an electrical connection between the two substrates 10a and 10 b. In some embodiments, additional interposers (i.e., 16c and 16d) may be disposed on the top surface of the substrate 10a to electrically connect the substrate 10a with another substrate or other device.

The encapsulating layer 12 covers or encapsulates the electronic components 11a, 11b, 11c, 11d, and 11e, the interposers 16a, 16b, 16c, and 16d, and the substrates 10a and 10 b. The encapsulant layer 12 may comprise an epoxy resin having a filler contained therein, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material containing silicone dispersed therein, or a combination thereof.

In some comparative embodiments, attachment of the interposers 16a, 16b, 16c, and 16d is achieved by using solder paste (e.g., layer 14), and thus, several reflow processes are required. However, the size (e.g., height) of the solder paste layer 14 may decrease after each reflow process. Therefore, it is difficult to control the height of each solder paste layer, which results in a stand-off deviation, especially in the case where a plurality of independent inserts are used at the same level. Due to the pitch deviation, the substrate 10a is inclined and it is difficult to maintain the interposers 16c and 16d formed on the top surface of the substrate 10a at the same height. Some of the topmost I/O pads (e.g., pad 16c1 of interposer 16 c) may thus become buried after application of encapsulation layer 12, which adversely affects the reliability and performance of semiconductor device package 1.

Fig. 2 is a cross-sectional view of another semiconductor device package 2, in accordance with some embodiments of the present disclosure. Semiconductor device package 2 is a stacked structure that may include substrates, such as 20a and 20 b; electronic components such as 21a, 21b, 21c, 21d, 21e, 21f, and 21 g; and inserts, such as 26a, 26b, 26c, and 26 d. The substrate may include traces, pads, or interconnects (not shown) for electrical connection.

As shown in fig. 2, one or more electronic components (e.g., 21a, 21b, and 21c) may be disposed on the bottom surface of the substrate 20 a. One or more electronic components, such as 21d, may be disposed on the top surface of the substrate 20 a. One or more electronic components, such as 21e, 21f, and 21g, may be disposed on the top surface of the substrate 20 b.

Each of the electronic components 21a, 21b, 21c, 21d, 21e, 21f, and 21g may include one or more passive electronic components and/or one or more active electronic components as discussed above.

In some embodiments, the semiconductor device package 2 includes a first substrate 20b and a first interposer 26a or 26 b. The first interposer 26a or 26b is disposed on the top surface of the first substrate 20 b. The bottom surface of the interposer 26a or 26b is attached to the top surface of the substrate 20b by a first conductive adhesive layer 24c or 24d, and the first conductive adhesive layer 24c or 24d contains spacers. In some embodiments, the spacers are in direct contact with the first substrate 20b and the corresponding first insert 26a or 26 b. The first interposer 26a or 26b has a plurality of pads disposed at a bottom surface thereof to provide electrical connection to the substrate 20 b. The semiconductor device package 2 may include at least one first interposer, or at least two first interposers, at least three first interposers, or more first interposers spaced apart from each other.

In some embodiments, the semiconductor device package 2 further includes a second substrate 20 b. The top surface of the interposer 26a or 26b is attached to the bottom surface of the second substrate 20b by a second conductive adhesive layer 24a or 24 b. In some embodiments, the second conductive adhesive layer 24a or 24b includes a spacer. In some embodiments, the spacers are in direct contact with the second substrate 20a and the corresponding first insert 26a or 26 b. The first interposer 26a or 26b has a plurality of pads disposed at a top surface thereof to provide electrical connection to the second substrate 20 a.

In some embodiments, the semiconductor device package 2 further includes a second interposer 26c or 26 d. The second interposer 26c or 26d is attached to the top surface of the second substrate 20a by a third conductive adhesive layer 24e or 24 f. In some embodiments, the third conductive adhesive layer 24e or 24f includes a spacer. In some embodiments, the spacers are in direct contact with the second substrate 20a and the corresponding second interposer 26c or 26 d. The second interposer 26a or 26b has a plurality of pads disposed at a bottom surface thereof to provide electrical connection to the substrate 20 a. The semiconductor device package 2 may include at least one second interposer, or at least two second interposers, at least three second interposers, or more second interposers spaced apart from each other.

In some embodiments, the semiconductor device package 2 further includes an encapsulation layer 22. The encapsulating layer 22 covers or encapsulates the electronic components 21a, 21b, 21c, 21d, 21e, 21f, and 21g, the interposers 26a, 26b, 26c, and 26d, the conductive adhesive layers 24a, 24b, 24c, 24d, 24e, and 21f, the substrate 20a, and the substrate 20 b. The encapsulant layer 22 can include an epoxy resin having a filler included therein, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including silicone dispersed therein, or a combination thereof.

The inserts 26a, 26b, 26c and 26d are independent of each other. The semiconductor device package may include one, two, three, or more interposers (e.g., interposers 26a and 26b and interposers 26c and 26d) spaced apart from each other at the same level. The shape of the insert is not particularly limited. In some embodiments, the insert may have a strip shape or a ribbon-like shape. In some embodiments, to increase the available surface area of a substrate for disposing electronic components and to maintain balance of the substrates to be stacked thereon, at least two inserts having a strip shape may be used.

The conductive adhesive layers 24a, 24b, 24c, 24d, 24e, and 24f are independent of each other and may be made of the same or different materials. The conductive adhesive layer may be made of a solderable conductive material. In some embodiments, the solderable electrically conductive material may include a thermosetting resin. In some embodiments, the solderable electrically conductive material may include a thermosetting resin and an electrically conductive material. The thermosetting resin may be epoxy, acrylate, polyimide, silicone, etc. The conductive material may be a metal powder, such as gold, silver or copper. The thermosetting resin may be a B-stage resin.

The conductive adhesive layer may include spacers or may be formed in situ as spacers. The spacer to be added to the conductive adhesive layer may be conductive or non-conductive, which may be a metal, plastic or glass spacer, for example. The spacers may comprise copper core bumps or balls, plastic core bumps or balls, or glass balls. The spacer can be sized to control the gap between the insert and the substrate. In some embodiments, the spacers can have an average diameter of 60 μm or more, 80 μm or more, 90 μm or more, 100 μm or more, 110 μm or more, 120 μm or more, 130 μm or more, 150 μm or more, 180 μm or more, 200 μm or more, 220 μm or more, 250 μm or more, or 300 μm or more.

In some embodiments, the solderable electrically conductive material may be a metal paste (e.g., a copper paste) that includes a metal powder (e.g., a copper powder) as the electrically conductive material and a thermosetting resin (e.g., an epoxy resin) as the binder. The total volume of the spacer is greater than about 2% by volume of the metal paste (e.g., about 3% or more by volume of the metal paste, about 4% or more by volume of the metal paste, or about 5% or more by volume of the paste), and the total volume of the metal powder and the thermosetting resin is less than about 98% by volume of the metal paste (e.g., about 97% or less by volume of the metal paste, about 96% or less by volume of the metal paste, or about 95% or less by volume of the metal paste).

In the following paragraphs, the structure of the insert is further explained by reference to insert 26 b. However, it should be noted that other inserts may have the same or similar structure.

Fig. 3A is an enlarged view of region CS as shown in fig. 2, according to some embodiments of the present disclosure. The first insert 26b includes a pad 26b1 at the bottom surface of the insert 26 b. The gasket 26b1 is disposed at or embedded within the bottom surface of the insert 26 b. The substrate 20b includes a pad 20b1 at the top surface of the substrate 20 b. The pad 20b1 is disposed at or embedded within the top surface of the substrate 20 b. A gap D1 is created between the exposed surface of pad 26b1 and the exposed surface of pad 20b 1.

As depicted in fig. 3A, the insert 26 has a recess at the bottom surface of the insert 26, and the pad 26b1 of the insert 26 is exposed from the recess. Pad 26b1 includes a central region P1 and a peripheral region P2 that surrounds central region P1. First interposer 26b includes an insulating layer 28 (not indicated in fig. 3A) disposed at a bottom surface of first interposer 26b and covering peripheral region P2 of pad 26b 1. The central region P1 of the pad 26b1 is exposed from the insulating layer 28 and has an exposed surface 26S. The exposed surfaces 26S of the insulating layer 28 and the pads 26b1 define recesses. Similarly, the substrate 20b may have a recess to expose a central area of the pad 20b1 of the substrate 20 b.

The recess of the insert 26b receives the conductive adhesive layer 24d, or in some embodiments, the recess of the first insert 26b receives the conductive adhesive layer 24d along with the recess of the substrate 20 b. The conductive adhesive layer 24d may include a spacer 24d1 covered or surrounded by a thermosetting resin 24d2, or in some embodiments, the conductive adhesive layer 24d constitutes a spacer. The spacer may be in direct contact with the exposed surface 26S of the pad 26b 1. The spacers may be in direct contact with the substrate 20b (e.g., the exposed surface of the pad 20b 1). In some embodiments, the exposed surface 26S of the insert 'S liner and the exposed surface of the substrate' S liner are substantially equal to or greater than the average diameter of the spacer.

Fig. 3B is an enlarged view of region CS as shown in fig. 2, according to some embodiments of the present disclosure. The enlarged view CS of fig. 3B is similar to the enlarged view of fig. 3A except that in fig. 3B, the conductive adhesive layer 24d contains two spacers.

Fig. 4A, 4B, 4C, and 4D illustrate the arrangement of pads in an insert according to some embodiments of the present disclosure. The arrangement of multiple pads discussed below may further improve the tilt problem of the stacked structure.

Fig. 4A is a top view of an insert according to some embodiments of the present disclosure. As shown in fig. 4A, the insert has a strip structure or ribbon-like structure having a length S1 and a width S2. The insert contains a plurality of pads such as RG1, RG2, RG3, RG4, RG5, and RG 6. The pads RG1, RG2, RG3, RG4, RG5 and RG6 are spaced apart from one another and can be arranged regularly or irregularly. An insulating layer 18 is disposed at the top surface of the interposer and covers the peripheral region of the pad. A central region of the pad is exposed from the insulating layer 28 and has an exposed surface 26S.

In fig. 4A, the pads RG1, RG2, RG3, RG4, RG5, and RG6 are arranged in a staggered manner or a staggered-like manner. In some embodiments, the pads RG 1-RG 6 are arranged in two lines (e.g., L1 and L2), three lines, four lines, or more lines that are substantially parallel to each other and extend along the length direction S1.

Fig. 4B is another top view of an insert according to some embodiments of the present disclosure. The top view of fig. 4B is similar to fig. 4A, except that in fig. 4B, the pads are arranged on two or more lines (e.g., L1 and L2) that are substantially parallel to each other but not in an interleaved manner. The center of the pad is positioned on one of the lines.

Fig. 4C is another top view of an insert according to some embodiments of the present disclosure. The top view of fig. 4C is similar to fig. 4B, except that in fig. 4C, two pads (RG1 and RG2) are disposed on line L1, followed in sequence by: two pads (RG3 and RG4) are disposed on line L2, two pads (RG5 and RG6) are disposed on line L1, two pads (RG7 and RG8) are disposed on line L2, and so on.

Fig. 4D is another top view of an insert according to some embodiments of the present disclosure. In fig. 4D, a portion of the pads RG2, RG4, RG6, and RG8 are arranged on the centerline L3, and another portion of the pads RG1, RG3, RG5, RG7, and RG9 are arranged beside the centerline L3. The gaskets RG1, RG3, RG5, RG7 and RG9 may be arranged regularly or irregularly.

By disposing the interposers between the substrates and using the spacers to ensure a desired distance between the substrates and the interposers, the interposers disposed at the same level can be well controlled, and the distance between the bottom surface of the upper substrate and the top surface of the lower substrate (whether from the center to the periphery) can be substantially the same. Accordingly, the inclination problem of the stack structure due to the pitch deviation may be solved, and thus the reliability or performance of the semiconductor device package may be improved.

In some embodiments, a method for manufacturing a semiconductor device package according to the present disclosure includes: providing a first substrate; providing an insert; and forming a spacer in contact with the first substrate and the interposer.

The stage of forming the spacer in contact with the first substrate and the interposer includes: placing a holder (or a set of holders) between the insert and the first substrate to define a receiving space for the conductive adhesive layer; and heating the conductive adhesive layer to form the spacer. In this stage, a solderable electrically conductive material is filled into the receiving space and then heated to form the spacer. The height of the spacer may be predetermined and controlled by the holder. After heating, the solderable electrically conductive material is cured into a spacer of a predetermined height and then the holder is removed. By forming the spacer with a predetermined height, a desired distance between the interposer and the first substrate can be ensured. In some embodiments, the distance between the interposer and the first substrate is substantially the same from the center of the interposer to the periphery of the interposer.

Fig. 5A, 5B, 5C, and 5D illustrate various stages of a method for fabricating a semiconductor device package according to some embodiments of the present disclosure.

Referring to fig. 5A, a first substrate 20a having a first surface SF1 and a second surface SF2 opposite to the first surface SF1 is provided, and first and second interposers are disposed on the first and second surfaces SF1 and SF2, respectively, to form a cell apparatus. First inserts 26a and 26b are mounted to first surface SF1 through conductive adhesive layers 24a and 24b, respectively. Second inserts 26c and 26d are mounted to second surface SF2 via conductive adhesive layers 24e and 24f, respectively. In some embodiments, the conductive adhesive layer may be formed on the surface of the substrate, for example, by printing a solderable conductive material on the surface of the substrate. The solderable electrically conductive material may include a spacer. In some embodiments, the surface of the substrate may include recesses and the conductive adhesive layer fills the corresponding recesses of the substrate. Inserts 26a, 26b, 26c, and 26d may be disposed on conductive adhesive layers 24a, 24b, 24e, and 24f, respectively, such that the conductive adhesive layers fill the recesses of the corresponding inserts and each of the recesses accommodates one or more spacers. Subsequently, the conductive adhesive layers 24a, 24b, 24e, and 24f are cured, for example, by heating or in a reflow process. Thus, the gap between the substrate 20a and each of the interposers 26a, 26b, 26c, and 26d may be controlled by the height of the spacers. Electronic components (e.g., 21a, 21b, and 21c) are formed or disposed on the first surface SF1, and electronic components (e.g., 21d) are formed or disposed on the second surface SF 2.

Referring to fig. 5B, a second substrate 20B having a surface SF3 is provided. The conductive adhesive layers 24c and 24d may be formed on the surface SF3 of the second substrate 20b, for example, by printing a solderable conductive material on the surface SF 3. The solderable electrically conductive material may include a spacer. In some embodiments, surface SF3 of second substrate 20b may include recesses and the conductive adhesive layer fills the corresponding recesses of second substrate 20 b. Electronic components (e.g., 21e, 21f, and 21g) are formed or disposed on surface SF3 of second substrate 20 b.

Referring to fig. 5C, the unit device prepared in the stage illustrated in fig. 5A is attached to the second substrate 20b through the conductive adhesive layers 24C and 24 d. The interposers 26a and 26b mounted on the unit devices may be disposed on the conductive adhesive layers 24c and 24d, respectively. Each of the inserts 26a and 26b may include a recess on its surface in contact with the conductive adhesive layers 24c and 24 d. The conductive adhesive layer fills the recesses of the insert, and each of the recesses accommodates one or more spacers. Subsequently, the conductive adhesive layers 24c and 24d are cured, for example, by heating or in a reflow process. Thus, the gap between the second substrate 20b and each of the interposers 26a and 26b may be controlled by the height of the spacer.

Referring to fig. 5D, encapsulation layer 22 covers or encapsulates electronic components 21a, 21b, 21c, 21D, 21e, 21f, and 21g, interposers 26a, 26b, 26c, and 26D, conductive adhesive layers 24a, 24b, 24c, 24D, 24e, and 24f, substrate 20a, and surface 20 b.

By using the conductive adhesive layers 24a, 24b, 24c, 24d, 24e, and 24f, the present disclosure can keep the gap between the lower substrate 20b and the interposer 26a or 26b and the gap between the interposer 26a or 26b and the upper substrate 20a uniform, and thus can reduce pitch deviation and can avoid the upper substrate from being inclined, compared to using the conventional solder paste. In addition, the conductive adhesive layer is made of a solderable conductive material, such as a copper paste, which can be easily applied to a surface and subsequently cured by heating. Therefore, the number of reflow processes can be reduced and high instability of the solder paste during the reflow process can be avoided.

As used herein, spatially relative terms, such as "below," "lower," "above," "upper," "lower," "left," "right," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

As used herein, the terms "approximately," "substantially," "generally," and "about" are used to describe and account for minor variations. When used in conjunction with an event or circumstance, the terms can refer to the situation where the event or circumstance occurs precisely as well as the situation where the event or circumstance occurs in close proximity. As used herein with respect to a given value or range, the term "about" generally means within ± 10%, ± 5%, ± 1%, or ± 0.5% of the given value or range. Ranges may be expressed herein as from one end point to the other end point or between the two end points. Unless otherwise specified, all ranges disclosed herein are inclusive of the endpoints. The term "substantially coplanar" may refer to two surfaces located along the same plane within a few microns (μm), such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm. When referring to "substantially" the same numerical value or property, the term can refer to values that are within ± 10%, ± 5%, ± 1%, or ± 0.5% of the mean of the stated values.

The foregoing summarizes features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or obtaining the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure.