阅读说明：本技术 三分频器电路 (Three-frequency divider circuit ) 是由 余振兴 孙小鹏 郑浩 石灿 王超 于 2020-12-30 设计创作，主要内容包括：本发明实施例提供了一种新型全差分注入锁定三分频器电路,包括：第一差分输入端、第二差分输入端、第三差分输入端、变压器、第一晶体管器件、第二晶体管器件,构成交叉耦合对的第三晶体管器件以及第四晶体管器件,第一差分输出端；所述变压器的主线圈两个端口与所述第一差分输入端相连,所述变压器的次线圈两个端口与所述第一晶体管器件的源极以及所述第二晶体管器件的源极相连；所述第一晶体管器件的栅极与所述第三晶体管器件的栅极通过串联电阻相连,所述第二晶体管器件的栅极与所述第四晶体管器件的栅极通过串联电阻相连,所述第三晶体管以及第四晶体管器件的漏极与所述第一差分输出端相连,该三分频器电路可提高分频带宽和灵敏度。(The embodiment of the invention provides a novel fully differential injection locking three-frequency divider circuit, which comprises: the differential amplifier comprises a first differential input end, a second differential input end, a third differential input end, a transformer, a first transistor device, a second transistor device, a third transistor device and a fourth transistor device which form a cross-coupled pair, and a first differential output end; two ports of a primary coil of the transformer are connected with the first differential input end, and two ports of a secondary coil of the transformer are connected with a source electrode of the first transistor device and a source electrode of the second transistor device; the grid electrode of the first transistor device is connected with the grid electrode of the third transistor device through a series resistor, the grid electrode of the second transistor device is connected with the grid electrode of the fourth transistor device through a series resistor, the drain electrodes of the third transistor device and the fourth transistor device are connected with the first differential output end, and the frequency division bandwidth and the sensitivity of the three-frequency divider circuit can be improved.)

1. A frequency divider circuit, comprising:

the differential amplifier comprises a first differential input end, a second differential input end, a third differential input end, a transformer, a first transistor device, a second transistor device, a third transistor device and a fourth transistor device which form a cross-coupled pair, and a first differential output end;

the input end of the transformer, namely two ports of the primary coil, is connected with the first differential input end, and the output end of the transformer, namely two ports of the secondary coil, is connected with the second differential input end;

the gate of the first transistor device is connected to the gate of the third transistor device, the gate of the second transistor device is connected to the gate of the fourth transistor device, the sources of the third and fourth transistor devices are connected to the third differential input terminal, and the drains of the third and fourth transistor devices are connected to the first differential output terminal.

2. The circuit of claim 1, wherein a gate of the third transistor device is coupled to a gate of the first transistor device through a first resistor, and a gate of the fourth transistor device is coupled to a gate of the second transistor device through a second resistor.

3. The circuit of claim 1,

the transformer and the periphery of the first transistor device and the periphery of the second transistor device are provided with parasitic capacitances, and the parasitic capacitances, the inductance of the transformer, the parasitic capacitances and the external capacitance form a first resonant cavity.

4. The circuit of claim 3, wherein the resonant frequency of the first resonant cavity is three times the frequency of the signal output by the divide-by-three circuit.

5. The circuit of claim 1, wherein a second resonant cavity is further between the drain of the first transistor device and the drain of the second transistor device.

6. The circuit of claim 5, wherein the resonant frequency of the second resonant cavity is twice the frequency of the signal output by the divide-by-three circuit.

7. The circuit of claim 1, further comprising:

and the source electrode of the fifth transistor device is connected with the power supply, and the drain electrode of the fifth transistor device is connected with the drain electrodes of the third and fourth transistor devices.

8. The circuit of claim 7, wherein a third resonant cavity is further between the fifth transistor device and the cross-coupled pair, and a resonant frequency of the third resonant cavity coincides with a frequency of a signal output by the divide-by-three circuit.

[ technical field ] A method for producing a semiconductor device

The invention relates to the technical field of frequency division circuits, in particular to a three-frequency divider circuit.

[ background of the invention ]

Currently, PLL (Phase Locked Loop) and FS (Frequency Synthesizers) are indispensable modules in wireless communication and radar transceivers. In general, millimeter wave PLLs and FS require multi-stage frequency dividers, where the first stage frequency divider usually needs to be implemented by injection locked frequency division due to the highest operating frequency. The conventional injection locking three-way frequency divider is generally a single-ended input structure, and the circuit structure thereof is shown in fig. 1, wherein an input signal is injected from the gate of the transistor M3 in a single-ended manner, an output signal is connected from the source and the drain of the transistor M3, a resonant cavity is equivalent to a band-pass filter and works near an output frequency, and the transistors M1 and M2 form a cross-coupled pair to generate a second harmonic of the output signal. The input of the frequency divider is a single-ended mode, and since a Voltage-Controlled Oscillator (VCO) of a preceding stage circuit of the frequency divider generally adopts a differential output mode, the direct adoption of a traditional three-frequency dividing structure will cause circuit mismatch. Unless a single port to differential port (S2D) block is added, the active S2D block not only increases circuit power consumption, but also introduces noise, thereby degrading the phase noise of the PLL or PS. The passive S2D module is implemented by using an inductor-capacitor matching network or a transformer, which not only increases the chip area but also reduces the VCO output signal amplitude due to the matching network loss, and an additional buffer stage circuit is provided before the frequency divider.

Therefore, it is necessary to provide a fully differential three-frequency divider circuit.

[ summary of the invention ]

The present invention is directed to a fully differential injection locked divide-by-three circuit, hereinafter referred to as a divide-by-three circuit for simplicity of description.

The technical scheme of the invention is as follows:

according to a first aspect of the present invention, there is provided a divide-by-three circuit comprising:

the first differential input end, the second differential input end, the transformer, a first transistor device and a second transistor device configured by a common-gate amplifier, a third differential input end, a third transistor device and a fourth transistor device forming a cross-coupled pair, and a first differential output end; the transformer primary coil port is connected to the first differential input terminal, and the transformer secondary coil port is connected to the second differential input terminal (i.e., respectively connected to the source of the first transistor device and the source of the second transistor device); the grid electrode of the first transistor device is connected with the grid electrode of the third transistor device, the grid electrode of the second transistor device is connected with the grid electrode of the fourth transistor device, and the drain electrodes of the third transistor device and the fourth transistor device are connected with the first differential output end.

The gate of the third transistor device is connected to the gate of the first transistor device through a first resistor, and the gate of the fourth transistor device is connected to the gate of the second transistor device through a second resistor.

The transformer and the peripheries of the first transistor device and the second transistor device are provided with parasitic capacitances, and the parasitic capacitances and self inductances, the parasitic capacitances and/or external capacitances in the transformer form a first resonant cavity.

The resonant frequency of the first resonant cavity is three times the frequency of the signal output by the three-frequency divider circuit.

A second resonant cavity is also provided between the drain of the first transistor device and the drain of the second transistor device.

The resonant frequency of the second resonant cavity is twice the frequency of the signal output by the three-frequency divider circuit.

The circuit further comprises: and the fifth transistor device is a current source and is a P-type transistor device, the source electrode of the fifth transistor device is connected with the power supply, and the drain electrode of the fifth transistor device is connected with the drain electrodes of the third transistor device and the fourth transistor device.

And a third resonant cavity is arranged between the fifth transistor device and the cross-coupling pair, and the resonant frequency of the third resonant cavity is consistent with the frequency of the signal output by the three-frequency divider circuit.

The first transistor device and the second transistor device are Field Effect Transistors (FETs) or other types of transistor devices, such as Bipolar Junction Transistor (BJT) devices, Heterojunction Bipolar Transistor (HBT) devices, etc.

Aiming at the three-frequency-division circuit based on the bipolar transistor device, the circuit structure is the same as the three-frequency-division circuit structure of the field effect transistor device, the position of an emitting electrode of the three-frequency-division circuit structure corresponds to the source electrode of the field effect transistor device, the position of a collecting electrode of the three-frequency-division circuit structure corresponds to the drain electrode of the field effect transistor device, and the position of a base electrode of the three-frequency-division circuit structure corresponds.

The invention has the beneficial effects that: in the three-frequency divider circuit provided by the embodiment of the invention, the differential input matching network formed by the parasitic capacitors of the transformer, the first transistor device and the second transistor device is added in the three-frequency divider circuit, so that the three-frequency divider circuit is convenient to be cascaded with the differential output end of the VCO, the first transistor device and the second transistor device are configured in a common-gate amplifier mode to form an intermediate isolation stage, the frequency division bandwidth of the three-frequency divider circuit can be improved, and the gates of the third transistor and the fourth transistor are connected with the gates of the first transistor and the second transistor through resistors to form a positive feedback loop to improve the sensitivity of the frequency divider.

[ description of the drawings ]

Fig. 1 is a schematic diagram of a conventional single-ended injection-locked three-way divider circuit according to the present invention;

fig. 2 is a schematic diagram of a conventional differential injection locked three-way divider circuit according to the present invention;

fig. 3 is a schematic diagram illustrating a structure of a novel fully differential injection locked three-frequency divider circuit according to an exemplary embodiment of the present invention.

[ detailed description ] embodiments

The invention is further described with reference to the following figures and embodiments.

It should be noted that all expressions using "first", "second", "third" and "fourth" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it is to be understood that "first", "second", "third" and "fourth" are only for convenience of description and should not be construed as limitations on the embodiments of the present invention, and the descriptions in the following embodiments are omitted.

Fig. 2 is a schematic diagram of a conventional differential injection locking three-way divider circuit according to an embodiment of the present invention, and as shown in fig. 2, an input signal is differentially injected by gates of transistors M3 and M4, and an output signal is output from drains of cross-coupled pairs M1 and M2. Although this structure adopts a fully differential input/output scheme, the transistors M3 and M4 do not have a dc path, and if the transistor size is small, the transistors are likely to be turned off or the injection efficiency is low, and therefore, the transistor size is required to be large. However, the larger the transistor size is, the larger the parasitic parameter is, so the frequency divider circuit structure has various defects of large input signal power, low operating frequency, small bandwidth, more frequency spectrum spurious components and the like. In view of this, embodiments of the present invention provide a transformer-based fully differential injection locked three-frequency divider circuit.

Fig. 3 is a schematic diagram showing a structure of a three-frequency divider circuit according to an exemplary embodiment of the present invention, as shown in fig. 3, the three-frequency divider circuit includes:

first differential anode input terminal V_inj+A first differential cathode input terminal V_inj-A second differential anode input terminal V_a+A second differential cathode input terminal V_b-TF of transformer₁A first transistor device M1, a second transistor device M2, a third differential anode input terminal V_b+And a third differential cathode input terminal V_b-A third transistor device M3 and a fourth transistor device M4 forming a cross-coupled pair, a first differential anode output terminal V_Out+And a first differential cathode output terminal V_Out-；

Wherein the first differential anode input end V_inj+And a first differential cathode input terminal V_inj-For the circuit to receive a differential input signal; accordingly, the first differential anode output terminal V_Out+And a first differential cathode output terminal V_Out-The circuit is used for outputting the differential signal after the three-frequency division.

The transformer TF₁Two ports of the primary coil are connected with the first differential input end to form a differential input end of the three-frequency divider, and the transformer TF₁The two ports of the secondary winding of the second transistor device M2 are connected with the source of the first transistor device M1 and the source of the second transistor device M3578 to form a second differential input terminal; the drain of the first transistor device M1 and the drain of the second transistor device M2 are connected to the source of the third transistor device M3 and the source of the fourth transistor device M4, respectively, to form a third differential input.

The transformer TF1 at the signal input terminal of the three-frequency divider circuit is implemented by two intertwined or stacked spiral inductors, and the first resonant cavity formed by the two intertwined or stacked spiral inductors and the peripheral capacitor can resolve the influence introduced by the parasitic capacitance of the sources of the transistors M1 and M2, so that the input signal can be smoothly and efficiently transmitted to the next circuit module.

The gate of the first transistor device M1 is connected to the gate of the third transistor device M3 through a series resistor R1, the gate of the second transistor device M2 is connected to the gate of the fourth transistor device M4 through a resistor R2, and the drain of the third transistor device M3 is connected to the first differential anode output terminal V_Out+A drain of the fourth transistor device M4 connected to the second differential cathode output terminal V_Out-And based on the pair of differential input ends and the pair of differential output ends, the three-frequency divider circuit can realize fully differential input and output.

In the three-frequency divider circuit provided by the embodiment of the invention, the differential input matching network formed by the transformer, the first transistor device and the second transistor device is added in the three-frequency divider circuit, so that the three-frequency divider circuit is convenient to be cascaded with the differential output end of the VCO, the first transistor device and the second transistor device form the input stage of the cross coupling pair of the three-frequency divider circuit in a common-gate amplifier configuration mode, and the common-gate amplifier configuration mode has natural direct current grounding, so that not only can the frequency dividing bandwidth of the three-frequency divider circuit be improved, but also the isolation between the output stage and the input stage can be increased, and thus stray can be reduced. In addition, compared with the existing three-frequency divider circuit, the three-frequency divider circuit has the advantages that although the differential input matching network is added, the power consumption of the circuit is not increased. And does not increase the chip area.

In an exemplary embodiment of the invention, the gate of the third transistor device is connected to the gate of the first transistor device through a first resistor, and the gate of the fourth transistor device is connected to the gate of the second transistor device through a second resistor. Still taking the three-frequency divider shown in fig. 3 as an example, the first resistor is exemplified by a resistor R1, the second resistor is exemplified by a resistor R2, the resistor R1 is connected in series between the gate of M1 and the gate of M3, and the resistor R2 is connected in series between the gate of M2 and the gate of M4, based on this, the resistor R1 and the resistor R2 can provide gate bias for the common-source amplifier stage transistors M1 and M2, and have a certain positive feedback effect, so that the frequency division sensitivity of the three-frequency divider circuit can be improved.

In an exemplary embodiment of the present invention, a parasitic capacitor is disposed between the transformer and the periphery of the first transistor device and the periphery of the second transistor device, the parasitic capacitor forms a first resonant cavity with an inductor and a capacitor in the transformer, and in the case of the three-way divider circuit shown in fig. 3, the capacitor C1 and the inductor L1 of the transformer and the parasitic capacitor of the periphery circuit of the transformer form a resonant cavity 1 as shown in a dashed box in fig. 3, the resonant cavity 1 is an example of a first resonant cavity, and the resonant cavity is resonant at a certain frequency by the inductor and the capacitor of the transformer and the parasitic capacitor of the periphery circuit of the transformer, and has a band-pass filter characteristic such that a useful input signal is transmitted to a lower-stage circuit module, and a useless out-of-band signal is filtered.

In an exemplary embodiment of the present invention, a resonant frequency of the first resonant cavity may be three times a frequency of a signal output from the divide-by-three circuit, based on which it may be ensured that an input signal is transmitted to a lower stage circuit module.

In an exemplary embodiment of the present invention, a second resonant cavity may be further provided between the drain of the first transistor device and the drain of the second transistor device. Still taking the divide-by-three circuit shown in fig. 3 as an example, a resonant cavity 2 is further provided between the drain of M1 and the drain of M2, the resonant cavity 2 is an example of a second resonant cavity, and the resonant cavity 2 can function like a band-pass filter, for example, to filter the input signal of the divide-by-three circuit and to present a high impedance to the second harmonic signal of the output signal of the divide-by-three circuit.

In an exemplary embodiment of the present invention, a resonant frequency of the second resonant cavity may be twice a frequency of a signal output by the divide-by-three circuit. Still taking the three-divider circuit shown in fig. 3 as an example, the resonant cavity 2 may be implemented by an LC resonant network, which not only absorbs the influence of the parasitic capacitance at the sources of the third and fourth transistor devices, but also functions like a band-pass filter, and may operate near twice the output frequency of the three-divider circuit to filter the input signal entering the sources of the third and fourth transistor devices.

In an exemplary embodiment of the present invention, the divide-by-three circuit may further include:

and the source electrode of the fifth transistor device is connected with the power supply, and the drain electrode of the fifth transistor device is connected with the drain electrodes of the third and fourth transistor devices. Still taking the three-way divider shown in fig. 3 as an example, the fifth transistor device is exemplified by a field effect transistor M5, and the fifth transistor device functions as a current source, providing cross-coupled pair drain biasing and a dc level of the output signal of the three-way divider. As shown in FIG. 3, the source of M5 is connected to the power supply VDD, and the drain of M5 is connected to the first differential anode output terminal V_Out+And a first differential cathode output terminal V_Out-The gate of M5 is connected to an external circuit to control the power consumption of the entire divide-by-three circuit via an external control circuit.

In an exemplary embodiment of the invention, a third resonant cavity may be further provided between the fifth transistor device and the cross-coupled pair, and a resonant frequency of the third resonant cavity may coincide with a frequency of a signal output by the frequency-divider circuit. Still taking the three-frequency divider circuit shown in fig. 3 as an example, a resonant cavity 3 is further provided between M5 and the cross-coupled pair M3 and M4, the resonant cavity 3 is an example of a third resonant cavity, and the resonant cavity 3 can function like a multi-order band-pass filter and can operate near the output frequency of the three-frequency divider circuit to filter out unwanted frequency components.

It should be noted that the frequency of the output signal of the three-frequency divider circuit in the above embodiments may also be referred to as the output frequency of the three-frequency divider circuit, and still taking the three-frequency divider circuit shown in fig. 3 as an example, the output frequency of the three-frequency divider circuit is the output frequency of the first differential anode output terminal V_Out+And a first differential cathode output terminal V_Out-The frequency of the output signal.

In an exemplary embodiment of the present invention, the differential input signal is transmitted to the sources of the transistors M1 and M2 through the transformer TF1, the input stage can be a common source amplification configuration, has the advantages of wide band matching, and the circuit matching is simple.

In an exemplary embodiment of the invention, the field effect transistors M3 and M4 form a cross-coupled pair whose nonlinear characteristics can produce a 2 nd harmonic frequency component of the output frequency.

It should be noted that the first transistor device, the second transistor device, the third transistor device, and the fourth transistor device in each of the above embodiments may be independently selected from one of a polysilicon thin film transistor, an amorphous silicon thin film transistor, an oxide thin film transistor, and an organic thin film transistor. The "gate" referred to in the above embodiments may specifically refer to a gate or a base of a transistor.

In addition, in the above embodiments, except that the current source is a P-type transistor, the other transistors are N-type transistors, which is a preferable solution that is convenient to implement in this embodiment, and does not limit the technical solution of the present invention. It should be understood by those skilled in the art that the type (N-type or P-type) or kind (FET transistor, BJT transistor) of each transistor and the current source and bias can be changed to implement the same operation principle of the divide-by-three circuit in this embodiment, which all fall within the protection scope of this application.

The specific cases are not illustrated here. While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.