阅读说明：本技术 正倒计数电路和计数器 (Count-up and count-down circuit and counter ) 是由 曹进伟 陈孟邦 卢玉玲 邹云根 蔡文前 张丹丹 肖敏 陈航强 林丽菲 于 2020-12-30 设计创作，主要内容包括：本发明提出一种正倒计数电路和计数器,其中,正倒计数电路包括第一信号处理电路、第二信号处理电路和多个触发器电路,通过采用第一信号处理电路接收正计数控制信号或者倒计数控制信号并输出对应的正计数触发信号和倒计数触发信号,同时,由第二信号处理电路为各触发器电路提供时钟信号,各触发器电路根据时钟信号以及对应的触发信号正向或者倒向切换输出电平,仅需设置一套计数电路即可完成正计数和倒计数,简化了电路结构和设计成本。(The invention provides a forward and backward counting circuit and a counter, wherein the forward and backward counting circuit comprises a first signal processing circuit, a second signal processing circuit and a plurality of trigger circuits, the first signal processing circuit is used for receiving a forward counting control signal or a backward counting control signal and outputting a corresponding forward counting trigger signal and a corresponding backward counting trigger signal, meanwhile, the second signal processing circuit provides a clock signal for each trigger circuit, each trigger circuit switches output levels in a forward direction or a backward direction according to the clock signal and the corresponding trigger signal, only one set of counting circuit is needed to complete forward counting and backward counting, and the circuit structure and the design cost are simplified.)

1. A forward and backward counting circuit is characterized by comprising a first signal processing circuit, a second signal processing circuit and a plurality of trigger circuits, wherein the plurality of trigger circuits comprise a first trigger circuit to an Nth trigger circuit, and the output ends of the first trigger circuit to the Nth trigger circuit are respectively a zeroth bit to an Nth-1 bit;

the first signal processing circuit is electrically connected with the second trigger circuit to the Nth trigger circuit respectively, and the second signal processing circuit is electrically connected with each trigger circuit respectively;

the first signal processing circuit is used for converting the received count-up control signal and count-down control signal into a count-up trigger signal and a count-down trigger signal respectively and outputting the count-up trigger signal and the count-down trigger signal to the second trigger circuit to the Nth trigger circuit, wherein the count-up control signal and the count-down control signal are both effective at low level;

the second signal processing circuit is configured to convert the count-up control signal and the count-down control signal into first clock signals and output the first clock signals to each of the flip-flop circuits

The first trigger circuit is used for outputting high and low level signals in a circulating mode when the first clock signal is received;

the second trigger circuit to the Nth trigger circuit are used for outputting N-1 correspondingly-turned high-low level signals according to the first clock signal, the positive counting trigger signal and high-low level signals output by a plurality of previous trigger circuits, wherein the N-1 correspondingly-turned high-low level signals and the high-low level signals output by the first trigger circuit correspond to binary values of N-bit positive counting; and

and outputting N-1 correspondingly-turned high-low level signals according to the first clock signal, the countdown triggering signal and high-low level signals output by the previous trigger circuits, wherein the N-1 correspondingly-turned high-low level signals and the high-low level signals output by the first trigger circuits correspond to N-bit countdown binary values.

2. The positive countdown circuit according to claim 1, wherein the positive countdown circuit further includes a reset circuit and a clock circuit;

the reset circuit is used for outputting a reset signal to control the first signal processing circuit, the second signal processing circuit and the plurality of trigger circuits to be powered on and reset;

the clock circuit is configured to output a second clock signal to the first signal processing circuit, the second signal processing circuit, and the plurality of flip-flop circuits.

3. The count-up and down circuit of claim 2, wherein the first signal processing circuit comprises a pulse signal conversion circuit and a trigger signal conversion circuit;

the pulse signal conversion circuit is connected with the trigger signal conversion circuit;

the pulse signal conversion circuit is used for respectively converting the count-up control signal and the count-down control signal into a count-up pulse signal and a count-down pulse signal and outputting the count-up pulse signal and the count-down pulse signal;

the trigger signal conversion circuit is used for converting and outputting the count-up trigger signal when receiving the count-up pulse signal and switching and outputting the count-down trigger signal when receiving the count-down pulse signal.

4. The forward-down counting circuit of claim 3, wherein the pulse signal conversion circuit comprises a first not gate, a second not gate, a third not gate, a fourth not gate, a fifth not gate, a sixth not gate, a first nor gate, a second nor gate, a first D flip-flop and a second D flip-flop;

the input end of the first not gate is used for inputting the positive counting control signal, the output end of the first not gate, the input end of the second not gate and the trigger signal end of the first D flip-flop are interconnected, the input end of the third not gate and the positive phase clock signal end of the first D flip-flop are connected in common and used for receiving the second clock signal, the output end of the third not gate is connected with the inverse phase clock signal end of the first D flip-flop, the reset signal end of the first D flip-flop is used for receiving the reset signal, the same phase output end of the first D flip-flop is connected with the first input end of the first not gate, the output end of the second not gate is connected with the second input end of the first nor gate, and the output end of the first nor gate is the first signal output end of the pulse signal conversion circuit;

the input end of the fourth not gate is used for inputting the countdown control signal, the output end of the fourth not gate, the input end of the fifth not gate and the trigger signal end of the second D flip-flop are interconnected, the input end of the sixth not gate and the normal phase clock signal end of the second D flip-flop are connected in common and used for receiving the second clock signal, the output end of the sixth not gate is connected with the reverse phase clock signal end of the second D flip-flop, the reset signal end of the second D flip-flop is used for receiving the reset signal, the same phase output end of the second D flip-flop is connected with the first input end of the second nor gate, the output end of the fifth not gate is connected with the second input end of the second nor gate, and the output end of the second nor gate is the second signal output end of the pulse signal conversion circuit.

5. The positive down-count circuit of claim 3, wherein the trigger signal conversion circuit comprises a seventh not gate, an eighth not gate, a third nor gate, and a third D flip-flop;

an input end of the seventh not gate, a normal phase clock signal end of the third D flip-flop and a second signal output end of the pulse signal conversion circuit are connected, an output end of the seventh not gate is connected with an inverted phase clock signal end of the third D flip-flop, a trigger signal end of the third D flip-flop is connected with a positive power supply, a first input end of the third nor gate is connected with a first signal output end of the pulse signal conversion circuit, a second input end of the third nor gate is used for receiving the reset signal, an output end of the third nor gate is connected with an input end of the eighth not gate, an output end of the eighth not gate is connected with a reset signal end of the third D flip-flop, and an output end of the third D flip-flop is a signal output end of the trigger signal conversion circuit; or

The trigger signal conversion circuit comprises a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a third NOR gate and a third D trigger;

the input end of the seventh NOT gate, the non-inverting clock signal end of the third D flip-flop and the first signal output end of the pulse signal conversion circuit are connected, the output end of the seventh NOT gate is connected with the inverted clock signal end of the third D flip-flop, the trigger signal end of the third D flip-flop is connected with a positive power supply, the first input end of the third NOR gate is connected with the second signal output end of the pulse signal conversion circuit, a second input terminal of the third nor gate is configured to receive the reset signal, an output terminal of the third nor gate is connected to an input terminal of the eighth not gate, the output end of the eighth not gate is connected with the reset signal end of the third D flip-flop, the output end of the third D flip-flop is connected with the input end of the ninth not gate, and the output end of the ninth not gate is the signal output end of the trigger signal conversion circuit.

6. The forward down-count circuit of claim 2, wherein said second signal processing circuit comprises a tenth not gate and a fourth D flip-flop;

an input end of the tenth not gate is commonly connected with a positive phase clock signal end of the fourth D flip-flop and is configured to receive the second clock signal, an output end of the tenth not gate is connected with a negative phase clock signal end of the fourth D flip-flop, a trigger signal end of the fourth D flip-flop is a signal input end of the second signal processing circuit, and a same phase output end and a negative phase output end of the fourth D flip-flop are signal output ends of the second signal processing circuit.

7. The count-up and count-down circuit of claim 6, further comprising a count-lock circuit electrically connected to the plurality of flip-flop circuits and the second signal processing circuit, respectively;

the counting locking circuit is used for stopping outputting the count-up control signal or the count-down control signal when the count-up binary number value or the count-down binary number value corresponding to the high-low level signal output by the plurality of trigger circuits is counted to a set value.

8. The count up and down circuit of claim 7, wherein the count lock circuit comprises a first nand gate, a second nand gate, a fourth nor gate, an eleventh not gate, a twelfth not gate, a first selector, and a second selector;

the input end of the first nand gate is connected to the high-low level signals output by the plurality of flip-flop circuits, the output end of the first nand gate is connected to the selection signal end of the selector, the first signal end of the first selector is connected to the positive power supply, the second signal end of the first selector is connected to the positive counting control signal, the output end of the first selector is connected to the first input end of the second nand gate, the input end of the fourth nor gate is connected to the high-low level signals output by the plurality of flip-flop circuits, the output end of the fourth nor gate is connected to the input end of the eleventh not gate, the output end of the eleventh not gate is connected to the selection signal end of the second selector, the first signal end of the second selector is connected to the positive power supply, and the second signal end of the second selector is connected to the countdown control signal, the output end of the second selector is connected with the second input end of the second nand gate, the output end of the second nand gate is connected with the twelfth not gate, and the output end of the twelfth not gate is the signal output end of the count locking circuit.

9. The positive down-count circuit of claim 1, wherein the plurality of flip-flop circuits comprises a first flip-flop circuit, a second flip-flop circuit, and a third flip-flop circuit, wherein a signal output of the first flip-flop circuit is connected to a signal input of the second flip-flop circuit and a signal input of the third flip-flop circuit, respectively, and wherein a signal output of the second flip-flop circuit is further connected to a signal input of the third flip-flop circuit.

10. A counter comprising the forward-backward counting circuit according to any one of claims 1 to 9.

Technical Field

The invention belongs to the technical field of counters, and particularly relates to a forward and backward counting circuit and a counter.

Background

The counting circuit or the counter is applied to various occasions, in a general IC circuit, the counting can be realized by a D trigger or a T trigger through simple connection, but if the counting can be seamlessly switched, two sets of circuits need to be designed or other circuit structures such as a signal detection circuit need to be added, the circuit structure is complex, and the cost is increased.

Therefore, the conventional technical scheme has the problems of complex circuit structure and high cost.

Disclosure of Invention

The invention aims to provide a forward and backward counting circuit, which aims to solve the problems of complex circuit structure and high cost of the traditional counting circuit.

A first aspect of an embodiment of the present invention provides a count-up/down circuit, where the count-up/down circuit includes a first signal processing circuit, a second signal processing circuit, and a plurality of flip-flop circuits, where the plurality of flip-flop circuits includes first to nth flip-flop circuits, and output ends of the first to nth flip-flop circuits are respectively a zeroth bit to an N-1 th bit;

the first signal processing circuit is electrically connected with the second trigger circuit to the Nth trigger circuit respectively, and the second signal processing circuit is electrically connected with each trigger circuit respectively;

the first signal processing circuit is used for converting the received count-up control signal and count-down control signal into a count-up trigger signal and a count-down trigger signal respectively and outputting the count-up trigger signal and the count-down trigger signal to the second trigger circuit to the Nth trigger circuit, wherein the count-up control signal and the count-down control signal are both effective at low level;

the second signal processing circuit is configured to convert the count-up control signal and the count-down control signal into first clock signals and output the first clock signals to each of the flip-flop circuits;

the first trigger circuit is used for outputting high and low level signals in a circulating mode when the first clock signal is received;

the second trigger circuit to the Nth trigger circuit are used for outputting N-1 correspondingly-turned high-low level signals according to the first clock signal, the positive counting trigger signal and high-low level signals output by a plurality of previous trigger circuits, wherein the N-1 correspondingly-turned high-low level signals and the high-low level signals output by the first trigger circuit correspond to binary values of N-bit positive counting; and

and outputting N-1 correspondingly-turned high-low level signals according to the first clock signal, the countdown triggering signal and high-low level signals output by the previous trigger circuits, wherein the N-1 correspondingly-turned high-low level signals and the high-low level signals output by the first trigger circuits correspond to N-bit countdown binary values.

In one embodiment, the positive and negative count circuit further comprises a reset circuit and a clock circuit;

the reset circuit is used for outputting a reset signal to control the first signal processing circuit, the second signal processing circuit and the plurality of trigger circuits to be powered on and reset;

the clock circuit is configured to output a second clock signal to the first signal processing circuit, the second signal processing circuit, and the plurality of flip-flop circuits.

In one embodiment, the first signal processing circuit includes a pulse signal conversion circuit and a trigger signal conversion circuit;

the pulse signal conversion circuit is connected with the trigger signal conversion circuit;

the pulse signal conversion circuit is used for respectively converting the count-up control signal and the count-down control signal into a count-up pulse signal and a count-down pulse signal and outputting the count-up pulse signal and the count-down pulse signal;

the trigger signal conversion circuit is used for converting and outputting the count-up trigger signal when receiving the count-up pulse signal and switching and outputting the count-down trigger signal when receiving the count-down pulse signal.

In one embodiment, the pulse signal conversion circuit includes a first not gate, a second not gate, a third not gate, a fourth not gate, a fifth not gate, a sixth not gate, a first nor gate, a second nor gate, a first D flip-flop, and a second D flip-flop;

the input end of the first not gate is used for inputting the positive counting control signal, the output end of the first not gate, the input end of the second not gate and the trigger signal end of the first D flip-flop are interconnected, the input end of the third not gate and the positive phase clock signal end of the first D flip-flop are connected in common and used for receiving the second clock signal, the output end of the third not gate is connected with the inverse phase clock signal end of the first D flip-flop, the reset signal end of the first D flip-flop is used for receiving the reset signal, the same phase output end of the first D flip-flop is connected with the first input end of the first not gate, the output end of the second not gate is connected with the second input end of the first nor gate, and the output end of the first nor gate is the first signal output end of the pulse signal conversion circuit;

the input end of the fourth not gate is used for inputting the countdown control signal, the output end of the fourth not gate, the input end of the fifth not gate and the trigger signal end of the second D flip-flop are interconnected, the input end of the sixth not gate and the normal phase clock signal end of the second D flip-flop are connected in common and used for receiving the second clock signal, the output end of the sixth not gate is connected with the reverse phase clock signal end of the second D flip-flop, the reset signal end of the second D flip-flop is used for receiving the reset signal, the same phase output end of the second D flip-flop is connected with the first input end of the second nor gate, the output end of the fifth not gate is connected with the second input end of the second nor gate, and the output end of the second nor gate is the second signal output end of the pulse signal conversion circuit.

In one embodiment, the trigger signal conversion circuit includes a seventh not gate, an eighth not gate, a third nor gate, and a third D flip-flop;

an input end of the seventh not gate, a normal phase clock signal end of the third D flip-flop and a second signal output end of the pulse signal conversion circuit are connected, an output end of the seventh not gate is connected with an inverted phase clock signal end of the third D flip-flop, a trigger signal end of the third D flip-flop is connected with a positive power supply, a first input end of the third nor gate is connected with a first signal output end of the pulse signal conversion circuit, a second input end of the third nor gate is used for receiving the reset signal, an output end of the third nor gate is connected with an input end of the eighth not gate, an output end of the eighth not gate is connected with a reset signal end of the third D flip-flop, and an output end of the third D flip-flop is a signal output end of the trigger signal conversion circuit; or

The trigger signal conversion circuit comprises a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a third NOR gate and a third D trigger;

the input end of the seventh NOT gate, the non-inverting clock signal end of the third D flip-flop and the first signal output end of the pulse signal conversion circuit are connected, the output end of the seventh NOT gate is connected with the inverted clock signal end of the third D flip-flop, the trigger signal end of the third D flip-flop is connected with a positive power supply, the first input end of the third NOR gate is connected with the second signal output end of the pulse signal conversion circuit, a second input terminal of the third nor gate is configured to receive the reset signal, an output terminal of the third nor gate is connected to an input terminal of the eighth not gate, the output end of the eighth not gate is connected with the reset signal end of the third D flip-flop, the output end of the third D flip-flop is connected with the input end of the ninth not gate, and the output end of the ninth not gate is the signal output end of the trigger signal conversion circuit.

In one embodiment, the second signal processing circuit includes a tenth not gate and a fourth D flip-flop;

an input end of the tenth not gate is commonly connected with a positive phase clock signal end of the fourth D flip-flop and is configured to receive the second clock signal, an output end of the tenth not gate is connected with a negative phase clock signal end of the fourth D flip-flop, a trigger signal end of the fourth D flip-flop is a signal input end of the second signal processing circuit, and a same phase output end and a negative phase output end of the fourth D flip-flop are signal output ends of the second signal processing circuit.

In one embodiment, the count-up/down circuit further comprises a count-lock circuit electrically connected to the plurality of flip-flop circuits and the second signal processing circuit, respectively;

the counting locking circuit is used for stopping outputting the count-up control signal or the count-down control signal when the count-up binary number value or the count-down binary number value corresponding to the high-low level signal output by the plurality of trigger circuits is counted to a set value.

In one embodiment, the count lock circuit includes a first nand gate, a second nand gate, a fourth nor gate, an eleventh not gate, a twelfth not gate, a first selector, and a second selector;

the input end of the first nand gate is connected to the high-low level signals output by the plurality of flip-flop circuits, the output end of the first nand gate is connected to the selection signal end of the selector, the first signal end of the first selector is connected to the positive power supply, the second signal end of the first selector is connected to the positive counting control signal, the output end of the first selector is connected to the first input end of the second nand gate, the input end of the fourth nor gate is connected to the high-low level signals output by the plurality of flip-flop circuits, the output end of the fourth nor gate is connected to the input end of the eleventh not gate, the output end of the eleventh not gate is connected to the selection signal end of the second selector, the first signal end of the second selector is connected to the positive power supply, and the second signal end of the second selector is connected to the countdown control signal, the output end of the second selector is connected with the second input end of the second nand gate, the output end of the second nand gate is connected with the twelfth not gate, and the output end of the twelfth not gate is the signal output end of the count locking circuit.

In one embodiment, the plurality of flip-flop circuits includes a first flip-flop circuit, a second flip-flop circuit, and a third flip-flop circuit, a signal output terminal of the first flip-flop circuit is connected to a signal input terminal of the second flip-flop circuit and a signal input terminal of the third flip-flop circuit, respectively, and a signal output terminal of the second flip-flop circuit is further connected to a signal input terminal of the third flip-flop circuit.

A second aspect of embodiments of the present invention provides a counter including the count-up and count-down circuit as described above.

Compared with the prior art, the embodiment of the invention has the following beneficial effects: foretell count circuit just counts down receives count control signal or count down control signal and exports corresponding count trigger signal and count down trigger signal through adopting first signal processing circuit, and simultaneously, provide clock signal for each trigger circuit by second signal processing circuit, each trigger circuit switches output level according to clock signal and corresponding trigger signal forward or backward, only need set up one set of counting circuit and can accomplish count and count down, circuit structure and design cost have been simplified.

Drawings

Fig. 1 is a schematic diagram of a first structure of a forward/backward counting circuit according to an embodiment of the present invention;

FIG. 2 is an exemplary circuit schematic of a flip-flop circuit in the count up and down circuit shown in FIG. 1;

FIG. 3 is a schematic diagram of an output waveform of a flip-flop circuit in the count-up/down circuit shown in FIG. 2;

fig. 4 is a schematic diagram of a second structure of a forward/backward counting circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a third structure of a forward/backward counting circuit according to an embodiment of the present invention;

FIG. 6 is an exemplary circuit schematic of a pulse signal conversion circuit in the count up/down circuit shown in FIG. 5;

FIG. 7 is a waveform diagram of a pulse signal conversion circuit in the forward/backward counting circuit shown in FIG. 6;

FIG. 8 is a first exemplary circuit schematic of a trigger signal converting circuit in the count up/down circuit of FIG. 5;

FIG. 9 is a second exemplary circuit schematic diagram of a trigger signal converting circuit in the count up/down circuit shown in FIG. 5;

FIG. 10 is an exemplary circuit schematic of a second signal processing circuit in the count up/down circuit shown in FIG. 1;

fig. 11 is a schematic diagram illustrating a fourth structure of a forward/backward counting circuit according to an embodiment of the present invention;

FIG. 12 is an exemplary circuit schematic of a count lock circuit in the count up and down circuit shown in FIG. 11.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

A first aspect of an embodiment of the present invention provides a forward/backward counting circuit.

As shown in fig. 1, fig. 1 is a first schematic structural diagram of a forward/backward counting circuit according to an embodiment of the present invention, in this embodiment, the forward/backward counting circuit includes a first signal processing circuit 10, a second signal processing circuit 20, and a plurality of flip-flop circuits, the plurality of flip-flop circuits includes a first flip-flop circuit 31 to an nth flip-flop circuit, and output terminals of the first flip-flop circuit 31 to the nth flip-flop circuit are respectively a zeroth bit to an N-1 th bit;

the first signal processing circuit 10 is electrically connected to the second to nth flip-flop circuits 32 to 20, respectively;

the first signal processing circuit 10 is configured to convert the received count-UP control signal UP and count-DOWN control signal DOWN into a count-UP trigger signal and a count-DOWN trigger signal, respectively, and output the count-UP trigger signal and the count-DOWN trigger signal to the second flip-flop circuit 32 through the nth flip-flop circuit, where both the count-UP control signal and the count-DOWN control signal are active at a low level;

a second signal processing circuit 20 for converting the count-UP control signal UP and the count-DOWN control signal DOWN into first clock signals CLK1/CLK1B and outputting to the respective flip-flop circuit first flip-flop circuits 31, for cyclically outputting high and low level signals upon receiving the first clock signals CLK1/CLK 1B;

the second flip-flop circuit 32 to the Nth flip-flop circuit are used for outputting N-1 correspondingly inverted high-low level signals according to the first clock signal CLK1/CLK1B, the positive counting trigger signal and the high-low level signals output by the previous flip-flop circuits, wherein the N-1 correspondingly inverted high-low level signals and the high-low level signals output by the first flip-flop circuit 31 correspond to N-bit positive counting binary values; and

the first clock signal CLK1/CLK1B, the count-down trigger signal and the high-low level signals output by the previous flip-flop circuits output N-1 correspondingly inverted high-low level signals, and the N-1 correspondingly inverted high-low level signals and the high-low level signals output by the first flip-flop circuit 31 correspond to the binary value of the N-bit count-down.

In this embodiment, the forward/backward counting circuit implements binary counting, the output terminals of the first to nth flip-flop circuits 31 to N-th flip-flop circuits are respectively zero to N-1 bits, and forward counting or backward counting is implemented according to a control signal, for example, forward counting of 000 to 111 and backward counting of 111 to 000, where the flip-flop circuits need corresponding clock signals during counting.

The external device, such as a key or a touch module, outputs a count-UP control signal UP or a count-DOWN control signal DOWN, and the count-UP control signal UP and the count-DOWN control signal DOWN are converted by the first signal processing circuit 10 and then output corresponding trigger signals, wherein both the count-UP control signal UP and the count-DOWN control signal DOWN are active at a low level, an output end of the first trigger circuit 31 serves as a zero level, an output level signal of the first trigger circuit is switched between a high level and a low level and corresponds to binary numbers 1 and 0 of the zero level, the rest of the trigger circuits perform count-UP according to the count-UP trigger signal and perform count-DOWN according to the count-DOWN trigger signal, and the level signal output when each trigger circuit is initially powered UP can be at a high level or a low level.

For example, when three flip-flop circuits are included, each of the three flip-flop circuits initially outputs a level signal corresponding to the first flip-flop circuit 31 at a high level, the corresponding binary value is 111, when a countdown trigger signal is received, the output of the first flip-flop circuit 31 sequentially changes, and at the same time, the second flip-flop circuit 32 outputs a level signal that changes according to the previous time and the output level of the first flip-flop circuit 31, and the second flip-flop circuit 32 outputs a level signal that changes according to the output levels of the previous two flip-flop circuits or the previous flip-flop circuit, thereby realizing sequential counting between 111 to 000, and similarly, when a count-up trigger signal is received, the output of the first flip-flop circuit 31 sequentially changes, and at the same time, the second flip-flop circuit 32 outputs a level signal that changes according to the previous time and the output level of the first flip-flop circuit 31, the third flip-flop circuit 33 outputs a varying level signal according to the output levels of the first two flip-flop circuits or the previous flip-flop circuit, thereby realizing sequential counting between 000 to 111, and when no stop signal is set, each flip-flop circuit can count cyclically in a single direction.

The flip-flop circuits can be correspondingly provided with different circuits and numbers according to counting requirements and output change logic, and the specific structure is not limited.

In one embodiment, as shown in fig. 1, the plurality of flip-flop circuits includes a first flip-flop circuit 31, a second flip-flop circuit 32, and a third flip-flop circuit 33, a signal output terminal of the first flip-flop circuit 31 is connected to a signal input terminal of the second flip-flop circuit 32 and a signal input terminal of the third flip-flop circuit 32, respectively, and a signal output terminal of the second flip-flop circuit 32 is further connected to a signal input terminal of the third flip-flop circuit 33.

In one embodiment, as shown in fig. 2, the first flip-flop circuit 31 includes a fifth D flip-flop ZDS1, wherein a trigger signal terminal D of the fifth D flip-flop ZDS1 is connected to its own inverted phase output terminal QB, while the clock signal terminal CK/CKB is connected to the inverted phase first clock signal CLK1/CLK1B, the output level of the in-phase output terminal Q of the first flip-flop circuit 31 is cyclically switched, while the second flip-flop circuit 32 includes a sixth D flip-flop ZDS2, a third selector ZMUX3, a thirteenth inverter INV13, and a first exclusive or gate 1, the first exclusive or gate XOR1 is connected to a first signal terminal IO of the third selector ZMUX3, while being connected to a second signal terminal I1 of the third selector ZMUX3 through a thirteenth inverter INV13, a selection signal terminal S of the third selector ZMUX3 is connected to the first signal processing circuit 10, and outputs the level of the trigger signal according to the state switching level, the third flip-flop circuit 33 includes a seventh D flip-flop ZDS3, a fourth selector ZMUX4, a fifth selector ZMUX5, a fourteenth inverter INV14, a fifteenth inverter INV15, a sixteenth inverter INV16, a third NAND gate NAND3, and a second XOR gate XOR 2.

In the positive counting mode, the trigger signal terminal D of the sixth D flip-flop ZDS2 is connected to the exclusive or signal of SD0 and SD1, the trigger signal terminal D of the seventh D flip-flop ZDS3 is connected to the signal of SD0 and SD1, and then is subjected to the exclusive or operation with the signal of SD2, and when the initial level corresponds to the high level of 111 or the low level of 000, the counting in the single direction of 000 to 111 is realized.

In the countdown mode, the trigger signal end D of the sixth D flip-flop ZDS2 is connected with the exclusive OR signal of the SD0 and the SD1, the trigger signal end D of the seventh D flip-flop ZDS3 is connected with the non-signal of the SD0 and the non-signal of the SD1, and then the exclusive OR operation is carried out on the trigger signal end D and the SD2 signal, so that the counting in the single direction of 111-000 is realized.

As shown in fig. 3, fig. 3 shows waveforms of output signals of SD0, SD1, SD2, initial SD2, SD1, SD0 are all at high level after power-UP, that is, 111, MODE is a changed trigger signal, including a countdown trigger signal and a count-UP trigger signal, and assuming that the current MODE is a countdown trigger signal and at high level, at this time, in the countdown MODE, SD2, SD1, SD0 are sequentially changed to 110, 101, 100, 011, 010 with successive toggling of the countdown signal, then at time t1, the countdown control signal DOWN is stopped being input, and is changed to the count-UP control signal UP, and switched to the count-UP MODE, at this time, MODE is changed to low level, SD2, SD1, SD0 is changed from 010 to 011, 100, 101, 110, 111, when the stop signal is set, after the count reaches 111 after time t2, the subsequent count-UP control signal is no longer activated, and at time t3, the countdown control signal is again input, MODE changes to high level, a countdown MODE is entered, SD2, SD1 and SD0 change from 111 to 110, 101, 100, 011, 010, 001 and 000 in sequence, when a stop signal is set, after the count reaches 000 after time t4, the subsequent countdown control signal DOWN is not effective, and the count MODE is entered again until the next time the count control signal UP is effective, and the count is repeated.

By this way, seamless switching between forward counting and backward counting is realized, if count values of other values are required, the number of stages of the flip-flop circuit can be increased or decreased, and the input logic signals corresponding to the trigger signal ends of the D flip-flops are changed, and different requirements correspond to different flip-flop circuits and different logic signals of the trigger signal ends, which is not limited herein.

Compared with the prior art, the embodiment of the invention has the following beneficial effects: the forward and backward counting circuit receives the forward counting control signal UP or the backward counting control signal DOWN through the first signal processing circuit 10 and outputs the corresponding forward counting trigger signal and backward counting trigger signal, meanwhile, the second signal processing circuit 20 provides clock signals for each trigger circuit, each trigger circuit switches output levels forward or backward according to the clock signals and the corresponding trigger signals, only one set of counting circuit needs to be arranged to finish forward counting and backward counting, and the circuit structure and the design cost are simplified.

As shown in FIG. 4, in one embodiment, the positive countdown circuit further includes a reset circuit 40 and a clock circuit 50;

a reset circuit 40 for outputting a reset signal POR to control the first signal processing circuit 10, the second signal processing circuit 20, and the plurality of flip-flop circuits to be power-on reset;

the clock circuit 50 outputs a second clock signal CLK2 to the first signal processing circuit 10, the second signal processing circuit 20, and the plurality of flip-flop circuits.

In this embodiment, the reset circuit 40 is configured to provide a reset signal POR, so as to power on and reset internal components of each flip-flop circuit, so as to perform recounting, meanwhile, the clock circuit 50 provides a second clock signal CLK2 for each circuit, the second clock signal CLK2 is used as a reference clock signal, the reset circuit 40 may employ a corresponding switch device and a power module, the clock circuit 50 may employ a crystal oscillator unit or other circuits, the frequency of the second clock signal CLK2 may be different values such as 100HZ and 1KHZ, and is specifically set correspondingly according to counting requirements.

As shown in fig. 5, in one embodiment, the first signal processing circuit 10 includes a pulse signal conversion circuit 11 and a trigger signal conversion circuit 12;

the pulse signal conversion circuit 11 is connected with the trigger signal conversion circuit 12;

a PULSE signal conversion circuit 11, configured to convert the count-UP control signal UP and the count-DOWN control signal DOWN into a count-UP PULSE signal UP _ PULSE and a count-DOWN PULSE signal DOWN _ PULSE, respectively, and output them;

a trigger signal conversion circuit 12 for converting and outputting the count-UP trigger signal when receiving the count-UP PULSE signal UP _ PULSE, and switching and outputting the count-DOWN trigger signal when receiving the count-DOWN PULSE signal DOWN _ PULSE.

In this embodiment, since the DOWN-count control signal DOWN and the UP-count control signal UP are square wave signals, as shown in fig. 7, in order to ensure that the rear-end flip-flop circuit can receive a stable trigger signal, level signal conversion needs to be performed through the pulse signal conversion circuit 11 and the trigger signal conversion circuit 12, the square wave signal is converted into a count pulse signal, and then the count pulse signal is converted into a corresponding continuous high-low level trigger signal to the rear-end flip-flop circuit, so that the flip-flop circuit performs UP-count or DOWN-count operation according to the trigger signal, wherein each pulse signal conversion circuit and each trigger signal conversion circuit 12 may adopt a corresponding flip-flop structure, and the specific structure is not limited.

As shown in fig. 6, in one embodiment, the pulse signal conversion circuit 11 includes a first not gate INV1, a second not gate INV2, a third not gate INV3, a fourth not gate INV4, a fifth not gate INV5, a sixth not gate INV6, a first not gate NOR1, a second not gate NOR2, a first D flip-flop ZDR1, and a second D flip-flop ZDR 2;

an input end of the first not gate INV1 is configured to input the positive count control signal UP, an output end of the first not gate INV1, an input end of the second not gate INV2 and a trigger signal end of the first D flip-flop ZDR1 are interconnected, an input end of the third not gate INV3 and the positive phase clock signal end CK of the first D flip-flop ZDR1 are commonly connected to receive the second clock signal CLK2, an output end of the third not gate INV3 is connected to the inverted clock signal end CKB of the first D flip-flop ZDR1, a reset signal end R of the first D flip-flop ZDR1 is configured to receive the reset signal POR, an in-phase output end Q of the first D flip-flop ZDR1 is connected to a first input end of the first NOR gate NOR1, an output end of the second not gate INV2 is connected to a second input end of the first NOR gate 1, and an output end of the first NOR gate 1 is a first signal output end of the pulse signal conversion circuit 11;

an input terminal of the fourth not gate INV4 is configured to input the countdown control signal DOWN, an output terminal of the fourth not gate INV4, an input terminal of the fifth not gate INV5, and the trigger signal terminal D of the second D flip-flop ZDR2 are interconnected, an input terminal of the sixth not gate INV6 and the positive phase clock signal terminal CK of the second D flip-flop ZDR2 are commonly connected to receive the second clock signal CLK2, an output terminal of the sixth not gate INV6 is connected to the inverted clock signal terminal CKB of the second D flip-flop ZDR2, a reset signal terminal R of the second D flip-flop ZDR2 is configured to receive the reset signal POR, an in-phase output terminal Q of the second D flip-flop ZDR2 is connected to the first input terminal of the second not gate NOR2, an output terminal of the fifth not gate INV5 is connected to the second input terminal of the second not gate 2, and an output terminal of the second not gate 2 is the second signal output terminal NOR of the pulse signal conversion circuit 11.

In this embodiment, the UP count control signal UP is inverted and then connected to the trigger signal terminal D of the first D flip-flop ZDR1, the clock signal terminals CK and CKB of the first D flip-flop ZDR1 are connected to the second clock signal CLK2 inverted with respect to each other, as shown in fig. 7, when the second clock signal CLK2 is triggered by a rising edge, the level of the output terminal of the first D flip-flop ZDR1 is equal to the level of the signal at the trigger signal terminal at that time, and the output terminal signal remains unchanged at other times, so as to prevent false triggering or noise.

Similarly, the DOWN count control signal DOWN is inverted and then connected to the trigger signal terminal of the second D flip-flop ZDR2, and the clock signal terminals CK and CKB of the second D flip-flop ZDR2 are connected to the second clock signal CLK2 inverted to each other, according to the same principle, as shown in fig. 7, when the second clock signal CLK2 is triggered at the rising edge, the level of the output terminal of the second D flip-flop ZDR2 is equal to the level of the signal at the trigger signal terminal at that time, and the output terminal signal is maintained unchanged at other times, which can prevent false triggering or noise, and the signal generated after passing through the second D flip-flop ZDR2 is not combined with the signal of the same logic level as the DOWN count control signal DOWN to generate a DOWN count PULSE signal DOWN _ PULSE, which is used for the trigger signal conversion circuit 12 to reset the state of the normal count mode and switch to the DOWN count mode.

As shown in fig. 8, in one embodiment, the trigger signal conversion circuit 12 includes a seventh not gate INV7, an eighth not gate INV8, a third NOR gate NOR3, and a third D flip-flop ZDR 3;

an input end of a seventh not gate INV7, a positive phase clock signal end CK of the third D flip-flop ZDR3 and a second signal output end of the pulse signal conversion circuit 11 are connected, an output end of the seventh not gate INV7 is connected with a negative phase clock signal end CKB of the third D flip-flop ZDR3, a trigger signal end D of the third D flip-flop ZDR3 is connected with the positive power supply VDD, a first input end of a third NOR gate NOR3 is connected with a first signal output end of the pulse signal conversion circuit 11, a second input end of the third NOR gate NOR3 is used for receiving a reset signal POR, an output end of the third NOR gate 3 is connected with an input end of an eighth not gate INV8, an output end of the eighth not gate INV8 is connected with a reset signal end R of the third D flip-flop ZDR3, and an output end of the third D flip-flop ZDR3 is a signal output end of the pulse signal conversion circuit 12; or

As shown in fig. 9, the trigger signal conversion circuit 12 includes a seventh not gate INV7, an eighth not gate INV8, a ninth not gate INV9, a third NOR gate NOR3, and a third D flip-flop ZDR 3;

an input end of a seventh not gate INV7, a positive phase clock signal end CK of the third D flip-flop ZDR3 and a first signal output end of the pulse signal conversion circuit 11 are connected, an output end of the seventh not gate INV7 is connected to a negative phase clock signal end CKB of the third D flip-flop ZDR3, a trigger signal end D of the third D flip-flop ZDR3 is connected to the positive power supply VDD, a first input end of the third NOR gate NOR3 is connected to a second signal output end of the pulse signal conversion circuit 11, a second input end of the third NOR gate NOR3 is configured to receive a reset signal POR, an output end of the third NOR gate 3 is connected to an input end of the eighth not gate INV8, an output end of the eighth not gate INV8 is connected to a reset signal end R of the third D flip-flop ZDR3, an output end of the third D flip-flop ZDR3 is connected to the ninth INV gate 9, and an output end of the ninth not gate INV9 is a signal output end of the trigger signal conversion circuit 12.

In the present embodiment, either of the above two configurations can be selected according to the reset state, as shown in fig. 9, when the input terminal of the seventh not gate INV7, the non-inverting clock signal terminal CK of the third D flip-flop ZDR3 and the first signal output terminal of the PULSE signal conversion circuit 11 are connected, the first input terminal of the third NOR gate NOR3 is connected to the second signal output terminal of the PULSE signal conversion circuit 11, at this time, the generated positive count PULSE signal UP _ PULSE and its inverted signal are used as the clock signal of the third D flip-flop ZDR3, when the positive count control signal UP is active, the clock signal terminal thereof is high, the signal output from the output terminal of the third D flip-flop ZDR3 is high of the positive power supply signal of the trigger signal terminal D, the MODE signal is changed to low, that is switched to the positive count MODE, and if the generated DOWN count PULSE signal DOWN _ PULSE controls the third D flip-flop ZDR3 to reset, the signal output from the output terminal of the third D flip-flop ZDR3 is reset to low level, and the MODE signal changes to high level, i.e., enters a DOWN-counting MODE, so as to realize the switching between the forward-counting state and the DOWN-counting state controlled by the forward-counting control signal UP and the DOWN-counting control signal DOWN.

As shown in fig. 8, when the input terminal of the seventh not gate INV7, the non-inverting clock signal terminal CK of the third D flip-flop ZDR3, and the second signal output terminal of the PULSE signal conversion circuit 11 are connected, the first input terminal of the third NOR gate NOR3 is connected to the first signal output terminal of the PULSE signal conversion circuit 11, at this time, the generated DOWN-count PULSE signal DOWN _ PULSE and its inverted signal are used as the clock signal of the third D flip-flop ZDR3, when the DOWN-count control signal is active, its signal terminal is at a high level, the output terminal of the third D flip-flop ZDR3 outputs a signal of a high level of the positive power VDD signal of the trigger signal terminal D, the MODE signal becomes a high level, that is, the DOWN-count MODE is switched, if the UP-count control signal is triggered, the UP-count PULSE signal generated controls the third D flip-flop ZDR3 to be reset, the output terminal of the third D flip-flop ZDR3 resets at a low level, namely, the counting mode is entered, so as to realize the switch of the counting state and the counting DOWN state controlled by the counting UP control signal and the counting DOWN control signal.

As shown in fig. 10, in one embodiment, the second signal processing circuit 20 includes a tenth not gate INV10 and a fourth D flip-flop ZDR 4;

an input terminal of the tenth not gate INV10 is commonly connected to the positive phase clock signal terminal CK of the fourth D flip-flop ZDR4 and is configured to receive the second clock signal CLK2, an output terminal of the tenth not gate INV10 is connected to the negative phase clock signal terminal CKB of the fourth D flip-flop ZDR4, the trigger signal terminal D of the fourth D flip-flop ZDR4 is a signal input terminal of the second signal processing circuit 20, and the in-phase output terminal Q and the negative phase output terminal QB of the fourth D flip-flop ZDR4 are signal output terminals of the second signal processing circuit 20.

In this embodiment, the UP control signal UP or the DOWN control signal DOWN is converted into the positive and negative phase first clock signal CLK1/CLK1B through the fourth D flip-flop ZDR4 and the second clock signal CLK2, and then converted into the clock signals of the D flip-flops of the flip-flop circuits.

As shown in fig. 11, in order to meet different counting requirements, in one embodiment, the count up/down circuit further includes a count lock circuit 60, and the count lock circuit 60 is electrically connected to the plurality of flip-flop circuits and the second signal processing circuit 20 respectively;

and a count lock circuit 60 for stopping outputting the count UP control signal or the count DOWN control signal DOWN when the count UP binary value or the count DOWN binary value corresponding to the high/low level signals output from the plurality of flip-flop circuits reaches a set value.

In this embodiment, it is assumed that the flip-flop circuit includes three, SD0, SD1, and SD2, which are final output signals, and are combined to generate 000, 001, 010, … …, 111(SD0 is low, and SD2 is high) by the high or low level of each of the three signals for counting, the three signals are logically operated by the count lock circuit 60, when the level is 111, the count lock circuit 60 stops outputting the UP count control signal UP or the DOWN count control signal DOWN, and when the output combination is a set value by the logical processing of the count lock circuit 60, and the UP count control signal UP or the DOWN count control signal DOWN is triggered again, the UP count control signal UP or the DOWN count control signal DOWN is not output, and no effect is exerted on the output result, that is, the maximum value of the UP count can be locked at 111, the minimum value of the DOWN count can be locked at 000, and the upper and lower limits can be locked at different values by different signal combinations, this is not further enumerated here.

As shown in fig. 12, in one embodiment, the count lock circuit 60 includes a first NAND gate NAND1, a second NAND gate NAND2, a fourth NOR gate NOR4, an eleventh NOR gate INV11, a twelfth not gate INV12, a first selector ZMUX1, and a second selector ZMUX 2;

the input terminal of the first NAND gate NAND1 is connected to the high-low level signals output from the plurality of flip-flop circuits, the output terminal of the first NAND gate NAND1 is connected to the selection signal terminal S of the selector, the first signal terminal IO of the first selector ZMUX1 is connected to the positive power supply, the second signal terminal I1 of the first selector ZMUX1 is connected to the positive count control signal UP, the output terminal of the first selector ZMUX1 is connected to the first input terminal of the second NAND gate NAND2, the input terminal of the fourth NOR gate NOR4 is connected to the high-low level signals output from the plurality of flip-flop circuits, the output terminal of the fourth NOR gate NOR4 is connected to the input terminal of the eleventh not gate INV11, the output terminal of the eleventh not gate INV11 is connected to the selection signal terminal S of the second selector ZMUX2, the first signal terminal IO of the second selector ZMUX2 is connected to the positive power supply, the second signal terminal I1 of the second selector ZMUX2 is connected to the DOWN control signal terminal S, and the output terminal of the second NAND gate NAND2 is connected to the second NAND gate 2, an output end of the second NAND gate NAND2 is connected to the twelfth not gate INV12, and an output end of the twelfth not gate INV12 is a signal output end of the count lock circuit 60.

In this embodiment, it is assumed that the flip-flop circuit includes three, SD0, SD1, and SD2, which are final output signals, and count by combining the three output signals with their respective levels being high or low to generate 000, 001, 010, … …, and 111(SD0 is low and SD2 is high), and these three signals generate a UL signal by nand combination, and when it is 111, UL is 0, the first selector ZMUX1 outputs a signal equal to positive power VDD, and when it is 000, 001, … …, and 110, UL is 1, and the output signal of the first selector ZMUX1 is a positive count control signal UP converted by a corresponding logic gate, and by such processing, when the output combination is 111, and when the positive count control signal UP is retriggered, the positive count control signal UP does not pass through, and does not affect the output result, that is the maximum value of positive count can be locked at 111.

In the same way, the DOWN count control signal DOWN makes the output combination be 000, and when the count control signal is triggered again, the count control signal can not pass through, and does not act on the output result, namely the DOWN count minimum value can be locked at 000, and the upper and lower limits can be locked at different values through different signal combinations, and the up and DOWN limit is not listed one by one.

Then, the two signals of the two selectors are combined, the twelfth inverter INV12 outputs a count control signal SW, wherein the count control signal is one of a positive count control signal UP, a negative count control signal DOWN and a positive power supply VDD generated after being converted by the corresponding logic gate, the count control signal SW is output to the second signal processing circuit 20 for further signal processing, when the signal received by the second signal processing circuit 20 is the positive count control signal UP or the negative count control signal DOWN generated after being converted by the corresponding logic gate, the first clock signal is converted and output to provide a count clock signal to each flip-flop circuit, and when the signal received by the second signal processing circuit 20 is the positive power supply VDD converted by the corresponding logic gate, the first clock signal is stopped being output, and each flip-flop circuit stops counting.

The present invention further provides a counter, which includes a forward/backward counting circuit, and the specific structure of the forward/backward counting circuit refers to the above embodiments, and since the counter employs all technical solutions of all the above embodiments, the counter at least has all beneficial effects brought by the technical solutions of the above embodiments, and details are not repeated herein.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.