阅读说明：本技术 一种新型的ldo防倒灌电流电路 (Novel LDO prevent flowing backward current circuit ) 是由 倪灿灿 于 2021-01-26 设计创作，主要内容包括：本发明提供了一种新型的LDO防倒灌电流电路,包括误差放大器EA、调整管MP、反馈电阻网络RA和RB、衬底电位选择电路BULK SEL以及负载电容CL和负载电阻RL；BULK SEL比较输入电压VIN与输出电压VOUT的大小,并输出两者中最大的电位作为衬底VPBULK的电位,当输出端电压高于输入电压时,能使得衬底寄生的二极管两端电位相等,从而消除正偏,避免了电流的倒灌以及调整管MP的损坏。(The invention provides a novel LDO (low dropout regulator) anti-backflow current circuit, which comprises an error amplifier EA, an adjusting tube MP, feedback resistor networks RA and RB, a substrate potential selection circuit BULK SEL, a load capacitor CL and a load resistor RL, wherein the adjusting tube MP is connected with the feedback resistor networks RA and RB; BULK SEL compares the magnitude of input voltage VIN and output voltage VOUT, and output the biggest electric potential in the two as the electric potential of substrate VPBULK, when output voltage is higher than input voltage, can make the parasitic diode both ends electric potential of substrate equal to eliminate the forward bias, avoided the backward flow of current and the damage of adjustment tube MP.)

1. The utility model provides a novel LDO prevent flowing backward current circuit which characterized in that: the device comprises an error amplifier EA, an adjusting tube MP, feedback resistor networks RA and RB, a substrate potential selection circuit BULK SEL, a load capacitor CL and a load resistor RL; the input voltage VIN is connected with the source electrode of the power tube MP, and the drain electrode of the power tube MP is the output voltage VOUT; a negative feedback voltage FB obtained after VOUT is subjected to voltage division through a feedback resistor network RA and a feedback resistor network RB is connected to an inverting input end of an error amplifier EA, and a non-inverting input end of the error amplifier EA is connected with a reference voltage VREF; the output end of the error amplifier EA is connected with the grid electrode of the power tube MP, a substrate potential selection circuit BULK SEL is connected with the substrate of the power tube MP, and the BULK SEL compares the VIN and the VOUT and outputs the maximum potential of the VIN and the VOUT as the potential of the substrate VPBULK; the power supply voltage of the error amplifier EA is VPBULK;

the substrate potential selection circuit BULK SEL comprises a voltage comparator, a waveform shaping circuit and a level selection circuit; the voltage comparator compares the input VIN and VOUT, after the input VIN and VOUT are shaped by the waveform shaping circuit, the maximum potential of the VIN and VOUT is selected by the level selection circuit to be used as VPBULK to be output.

2. The novel LDO anti-backflow current circuit according to claim 1, wherein: the voltage comparator comprises M1-M10 and R1-R3, the waveform shaping circuit comprises M11-M17, and the level selection circuit comprises M18, M19, R4 and R5; wherein M3, M4, M5, M6, M10, M14, M15, M17 and M19 are NMOS tubes, M1, M2, M7, M8, M9, M11, M12, M13, M16 and M18 are PMOS tubes, and R1-R5 are resistors; the substrates of M3 and M4 and the sources and substrates of M5, M6, M10, M14, M15, M17 and M19 are grounded; the sources and the substrates of M9, M11, M12, M13 and M16 are connected with the output VPBULK; one end of the resistor R1 is connected with VIN, and the other end is connected with the source and the substrate of M1; one end of the resistor R2 is connected with VOUT, and the other end is connected with the sources and the substrate of M2 and M7; the gates of M1, M2 and M7 are connected and connected to the drain of M1, and the drain of M1 is connected with the drain of M3; the drain electrode of the M2 is connected with the drain electrodes of the M4 and the M8 and the gate electrodes of the M9 and the M10; the gates of M3 and M4 are connected to BIAS1, the gates of M5 and M6 are connected to BIAS2, and BIAS1 and BIAS2 are externally supplied biases; the source of M3 is connected with the drain of M5, and the source of M4 is connected with the drain of M6; the drain of M7 is connected with the source and substrate of M8, the gate of M8 is connected with the gates of M11 and M14, the drain of M10 and the resistor R3, and the other end of the resistor R3 is connected with the drain of M9; the drain of M11 is connected with the drains of M12 and M14 and the gates of M13 and M15; the gate of M12 is connected with the drains of M13 and M15 and the gates of M16, M17 and M19; the drain of M16 is connected with the drain of M17 and the gate of M18; one end of the resistor R4 is connected with VIN, and the other end is connected with the drain electrode of M18; one end of the resistor R5 is connected with VOUT, and the other end is connected with the drain electrode of the M19; the sources and substrates of M18, M19 are connected and connected to the output VPBULK.

Technical Field

The invention relates to the field of circuit design, in particular to a novel LDO (low dropout regulator) anti-backflow current circuit.

Background

An LDO is a dc buck type linear regulator that can maintain a stable output voltage even when an input voltage or a load current varies. The conventional LDO structure is shown in fig. 1, and its operation principle is: VOUT is (R1+ R2)/R2 VREF, and when the load changes, for example, the load current becomes large, VOUT decreases, VFB decreases, and via the error amplifier EA, VEA decreases, thereby adjusting the adjustment transistor MPASS, so that the current increases, VOUT voltage increases, and via this negative feedback loop, VOUT voltage is finally restored.

When the general LDO linear voltage regulator provides voltage for an output load, the VIN power voltage of the regulating tube is always higher than the output voltage VOUT of the regulating tube. Therefore, the parasitic diode between the drain electrode of the adjusting tube and the substrate is always in a reverse bias state, and the leakage condition cannot occur. However, with the requirements of applications such as portable electronic devices and industrial electronic products, the situation that the VIN input voltage of one of the LDOs is lower than the output voltage thereof, or the input VIN is short-circuited to ground or floating, etc. may be encountered during switching of multiple power supply voltage domains. In this case, a forward bias is applied to the parasitic diode, and a reverse current is generated, which may adversely affect the circuit performance and damage the transistor.

Disclosure of Invention

In order to solve the technical problem, the invention provides a novel LDO (low dropout regulator) anti-backflow current circuit.

A novel LDO backflow prevention current circuit comprises an error amplifier EA, an adjusting tube MP, feedback resistor networks RA and RB, a substrate potential selection circuit BULK SEL, a load capacitor CL and a load resistor RL; the input voltage VIN is connected with the source electrode of the power tube MP, and the drain electrode of the power tube MP is the output voltage VOUT; a negative feedback voltage FB obtained after VOUT is subjected to voltage division through a feedback resistor network RA and a feedback resistor network RB is connected to an inverting input end of an error amplifier EA, and a non-inverting input end of the error amplifier EA is connected with a reference voltage VREF; the output end of the error amplifier EA is connected with the grid electrode of the power tube MP, a substrate potential selection circuit BULK SEL is connected with the substrate of the power tube MP, and the BULK SEL compares the VIN and the VOUT and outputs the maximum potential of the VIN and the VOUT as the potential of the substrate VPBULK; the power supply voltage of the error amplifier EA is VPBULK;

the substrate potential selection circuit BULK SEL comprises a voltage comparator, a waveform shaping circuit and a level selection circuit; the voltage comparator compares the input VIN and VOUT, after the input VIN and VOUT are shaped by the waveform shaping circuit, the maximum potential of the VIN and VOUT is selected by the level selection circuit to be used as VPBULK to be output.

Preferably, the voltage comparator comprises M1-M10 and R1-R3, the waveform shaping circuit comprises M11-M17, and the level selection circuit comprises M18, M19, R4 and R5; wherein M3, M4, M5, M6, M10, M14, M15, M17 and M19 are NMOS tubes, M1, M2, M7, M8, M9, M11, M12, M13, M16 and M18 are PMOS tubes, and R1-R5 are resistors; the substrates of M3 and M4 and the sources and substrates of M5, M6, M10, M14, M15, M17 and M19 are grounded; the sources and the substrates of M9, M11, M12, M13 and M16 are connected with the output VPBULK; one end of the resistor R1 is connected with VIN, and the other end is connected with the source and the substrate of M1; one end of the resistor R2 is connected with VOUT, and the other end is connected with the sources and the substrate of M2 and M7; the gates of M1, M2 and M7 are connected and connected to the drain of M1, and the drain of M1 is connected with the drain of M3; the drain electrode of the M2 is connected with the drain electrodes of the M4 and the M8 and the gate electrodes of the M9 and the M10; the gates of M3 and M4 are connected to BIAS1, the gates of M5 and M6 are connected to BIAS2, and BIAS1 and BIAS2 are externally supplied biases; the source of M3 is connected with the drain of M5, and the source of M4 is connected with the drain of M6; the drain of M7 is connected with the source and substrate of M8, the gate of M8 is connected with the gates of M11 and M14, the drain of M10 and the resistor R3, and the other end of the resistor R3 is connected with the drain of M9; the drain of M11 is connected with the drains of M12 and M14 and the gates of M13 and M15; the gate of M12 is connected with the drains of M13 and M15 and the gates of M16, M17 and M19; the drain of M16 is connected with the drain of M17 and the gate of M18; one end of the resistor R4 is connected with VIN, and the other end is connected with the drain electrode of M18; one end of the resistor R5 is connected with VOUT, and the other end is connected with the drain electrode of the M19; the sources and substrates of M18, M19 are connected and connected to the output VPBULK.

The invention has the beneficial effects that: the maximum value of the input voltage VIN and the output voltage VOUT is selected by the substrate potential selection circuit BULK SEL to be used as the substrate voltage of the adjusting tube MP, when the output end voltage is higher than the input voltage, the potentials at two ends of the diode parasitic on the substrate can be equal, so that the forward bias is eliminated, and the backward flow of the current and the damage of the adjusting tube MP are effectively avoided.

Drawings

The invention will be further described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of a conventional LDO;

FIG. 2 is an overall circuit block diagram of an embodiment of the present invention;

FIG. 3 is a circuit diagram of BULK SEL in the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by those skilled in the art without any creative work based on the embodiments of the present invention belong to the protection scope of the present invention.

The invention provides a novel LDO (low dropout regulator) anti-backflow current circuit, which has the overall structure shown in figure 2 and mainly comprises an error amplifier EA, an adjusting tube MP, feedback resistor networks RA and RB, a substrate potential selection circuit BULK SEL, a load capacitor CL and a load resistor RL. The input voltage VIN is connected to the source of the power transistor MP, and the drain of the power transistor MP is the output voltage VOUT. A negative feedback voltage FB obtained after VOUT is subjected to voltage division through the feedback resistor networks RA and RB is connected to the inverting input end of the error amplifier EA, the non-inverting input end of the error amplifier EA is connected with the reference voltage VREF, and the output end of the error amplifier EA is connected with the grid electrode of the power tube MP. FB is equal to VREF, and when the load CL or RL changes, the gate voltage of the adjusting tube MP can be adjusted through the negative feedback loop of FB and EA, so that the output voltage value is stabilized.

The substrate potential selection circuit BULK SEL is connected to the substrate of the power transistor MP, and the BULK SEL can compare VIN and VOUT and output the maximum potential of the two as the potential of the substrate VPBULK (the power supply voltage of the error amplifier EA is VPBULK). When VIN is the highest potential in the circuit, the parasitic diode between the drain of the power transistor MP and the substrate is always in reverse bias, and no leakage occurs. When the potential of VOUT is higher than VIN, BULK SEL can be quickly switched to the potential of VOUT as substrate VPBULK, thereby eliminating the forward bias between VOUT and the parasitic diode of the substrate, and meanwhile, the influence of electric leakage and the like can not be generated when VIN and the parasitic diode of the substrate are in a reverse bias state.

The substrate potential selection circuit BULK SEL has a structure as shown in fig. 3, and includes a voltage comparator, a waveform shaping circuit, and a level selection circuit. The voltage comparator comprises M1-M10 and R1-R3, the waveform shaping circuit comprises M11-M17, and the level selection circuit comprises M18, M19, R4 and R5; wherein M3, M4, M5, M6, M10, M14, M15, M17 and M19 are NMOS tubes, M1, M2, M7, M8, M9, M11, M12, M13, M16 and M18 are PMOS tubes, and R1-R5 are resistors. The input VIN and VOUT are compared by a voltage comparator, after being shaped by a waveform shaping circuit, the maximum potential of the two is selected by a level selection circuit to be output as VPBULK.

The substrates of M3 and M4, and the sources and substrates of M5, M6, M10, M14, M15, M17, and M19 are all grounded. The sources and substrates of M9, M11, M12, M13, M16 are connected to the output VPBULK. One end of the resistor R1 is connected with VIN, and the other end is connected with the source and the substrate of M1; one end of the resistor R2 is connected with VOUT, and the other end is connected with the source and the substrate of M2 and M7. The gates of M1, M2 and M7 are connected to the drain of M1, and the drain of M1 is connected to the drain of M3. The drain of M2 is connected to the drains of M4, M8 and the gates of M9, M10. The gates of M3 and M4 are connected to BIAS1, the gates of M5 and M6 are connected to BIAS2, and BIAS1 and BIAS2 are externally supplied biases. The source of M3 is connected to the drain of M5, and the source of M4 is connected to the drain of M6. The drain of M7 is connected to the source and substrate of M8, the gate of M8 is connected to the gates of M11 and M14, the drain of M10 and resistor R3, and the other end of resistor R3 is connected to the drain of M9. The drain of M11 is connected with the drains of M12 and M14 and the gates of M13 and M15; the gate of M12 is connected with the drains of M13 and M15 and the gates of M16, M17 and M19; the drain of M16 is connected to the drain of M17 and the gate of M18. One end of the resistor R4 is connected with VIN, and the other end is connected with the drain electrode of M18; one end of the resistor R5 is connected with VOUT, and the other end is connected with the drain of M19. The sources and substrates of M18, M19 are connected and connected to the output VPBULK.

Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention.