阅读说明：本技术 包括电平移位器的设备 (Device comprising a level shifter ) 是由 克拉斯-简·德兰根 安东尼乌斯·马蒂纳斯·杰可布斯·黛安娜 费雷德里克·范登恩德 于 2020-10-22 设计创作，主要内容包括：一种设备,设备包括：第一电压域电路,第一电压域电路包括被配置成提供第一数字输出信号的第一电路组件；第二电压域电路,第二电压域电路包括第二电路组件；电平移位器布置,电平移位器布置被配置成接收第一数字输出信号,并基于第一数字输出信号而以升高的高状态的电压电平生成第二数字输出信号,并向第二电路组件提供第二数字输出信号；其中电平移位器布置包括至少一个级,至少一个级包括耦合到CMOS反相器布置的一个或多个二极管连接式PMOS晶体管的布置,至少一个级中的第一级的CMOS反相器布置被配置成接收第一数字输出信号,且至少一个级中的最后一级的CMOS反相器布置被配置成输出第二数字输出信号。(An apparatus, the apparatus comprising: a first voltage domain circuit comprising a first circuit component configured to provide a first digital output signal; a second voltage domain circuit comprising a second circuit component; a level shifter arrangement configured to receive the first digital output signal, and to generate a second digital output signal at a boosted high state voltage level based on the first digital output signal, and to provide the second digital output signal to the second circuit component; wherein the level shifter arrangement comprises at least one stage comprising an arrangement of one or more diode-connected PMOS transistors coupled to a CMOS inverter arrangement, the CMOS inverter arrangement of a first stage of the at least one stage being configured to receive the first digital output signal and the CMOS inverter arrangement of a last stage of the at least one stage being configured to output the second digital output signal.)

1. An apparatus, comprising:

a first voltage domain circuit comprising first circuit components configured to provide a first digital output signal, wherein the first voltage domain circuit is configured to receive a first supply voltage, and wherein the first digital output signal has a high state and a low state, and a voltage of the high state is based on the first supply voltage;

a second voltage domain circuit comprising second circuit components, wherein the second voltage domain circuit is configured to receive a second supply voltage that is greater than the first supply voltage;

a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal at the elevated voltage level of the high state based on the first digital output signal, wherein the level shifter arrangement is configured to provide the second digital output signal for input to the second circuit component;

wherein the level shifter arrangement comprises at least one stage comprising an arrangement of one or more diode-connected PMOS transistors, a source terminal of at least one of the one or more diode-connected PMOS transistors being configured to be coupled to the second supply voltage, and a drain terminal of at least one of the one or more diode-connected PMOS transistors being coupled to a CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference;

the CMOS inverter arrangement of a first stage of the at least one stage is configured to receive the first digital output signal, and the CMOS inverter arrangement of a last stage of the at least one stage is configured to output the second digital output signal.

2. The apparatus of claim 1, wherein the level shifter arrangement comprises at least two stages, including a first stage and a second stage;

wherein the first stage comprises a first arrangement of one or more diode-connected PMOS transistors, a source terminal of at least one of the one or more diode-connected PMOS transistors configured to be coupled to the second supply voltage, and a drain terminal of at least one of the one or more diode-connected PMOS transistors coupled to a first CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference; and is

Wherein the second stage comprises a second arrangement of one or more diode-connected PMOS transistors, a source terminal of at least one of the one or more diode-connected PMOS transistors configured for coupling to the second supply voltage and a drain terminal of at least one of the one or more diode-connected PMOS transistors coupled to a second CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference;

wherein the first CMOS inverter arrangement is configured to receive the first digital output signal and provide a first intermediate digital output signal to the second CMOS inverter arrangement of the second stage, wherein the second CMOS inverter arrangement is configured to receive the intermediate digital output signal and provide the second digital output signal to the second circuit component; and is

Wherein the first and second arrangements of diode-connected PMOS transistors are configured such that a voltage drop provided by the first arrangement is greater than a voltage drop provided by the second arrangement.

3. The apparatus of any preceding claim, wherein the arrangement of one or more diode-connected PMOS transistors comprises one of:

a plurality of diode-connected PMOS transistors connected in series; and

a plurality of diode-connected PMOS transistors connected in parallel.

4. The apparatus of claim 3, wherein the arrangement comprises a plurality of diode-connected PMOS transistors connected in series, and wherein at least one or more of the diode-connected PMOS transistors has a separate n-well.

5. The apparatus of claim 2, wherein the first arrangement comprises a plurality of diode-connected PMOS transistors connected in series, and the second arrangement comprises one or more diode-connected PMOS transistors connected in series, and the difference in voltage drop is provided by a greater number of diode-connected PMOS transistors connected in series in the first arrangement relative to a number of diode-connected PMOS transistors connected in series in the second arrangement.

6. The apparatus of claim 2, wherein the first arrangement comprises one or more diode-connected PMOS transistors connected in parallel, and the second arrangement comprises a plurality of diode-connected PMOS transistors connected in parallel, and the difference in voltage drop is provided by a greater number of diode-connected PMOS transistors connected in parallel in the second arrangement relative to the number of diode-connected PMOS transistors connected in parallel in the first arrangement.

7. The apparatus of any of claims 2 to 4, wherein the level shifter arrangement comprises at least three stages, and the voltage drop of the diode-connected PMOS transistor arrangement of each of the at least three stages gradually and monotonically decreases from the first stage receiving the first digital output signal to a last stage of the at least three stages providing the second digital output signal for the second circuit component.

8. The apparatus of claim 6, wherein each of the diode-connected PMOS transistors of the first and second arrangements has a same unit size.

9. The apparatus of any preceding claim, wherein the level shifter arrangement comprises:

a high trigger level first stage comprising an arrangement of the one or more diode-connected PMOS transistors, a source terminal of at least one of the one or more diode-connected PMOS transistors configured to be coupled to the second supply voltage and a drain terminal of at least one of the one or more diode-connected PMOS transistors coupled to a high trigger level CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference;

the high trigger level CMOS inverter arrangement of the high trigger level first stage configured to receive the first digital output signal and provide a high trigger level output signal;

a low trigger level first stage comprising an arrangement of one or more diode-connected PMOS transistors, a source terminal of at least one of the one or more diode-connected PMOS transistors configured to be coupled to the second supply voltage and a drain terminal of at least one of the one or more diode-connected PMOS transistors coupled to a low trigger level CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference;

the low trigger level CMOS inverter arrangement of the low trigger level first stage is also configured to receive the first digital output signal and provide a low trigger level output signal;

wherein the high-trigger level CMOS inverter arrangement and the low-trigger level CMOS inverter arrangement each comprise a PMOS transistor having a source terminal for coupling directly or indirectly to a respective arrangement of one or more diode-connected PMOS transistors, and a drain terminal for connecting directly or indirectly to a drain terminal of an NMOS transistor, and wherein the source terminal of the NMOS transistor is for coupling directly or indirectly to the reference voltage;

wherein in the high trigger level CMOS inverter arrangement, a width-to-length ratio of the PMOS transistor is greater than a width-to-length ratio of the NMOS transistor, and in the low trigger level CMOS inverter arrangement, a width-to-length ratio of the NMOS transistor is greater than a width-to-length ratio of the PMOS transistor;

a latch configured to receive the high trigger level output signal and the low trigger level output signal and to combine the high trigger level output signal and the low trigger level output signal to generate a combined digital signal; and

a last stage comprising a CMOS logic inverter (M15/M16) configured to receive the combined digital signal and output the second digital signal.

10. A wireless communication apparatus, characterized in that it comprises a device according to any of the preceding claims.

Technical Field

The present disclosure relates to an apparatus having circuit components operating in different voltage domains. In particular, the present disclosure relates to a device having a level shifter for receiving a digital signal from one voltage domain and shifting its voltage level to control a second voltage domain.

Background

The circuit arrangement may have one or more components operating in a first supply voltage domain and one or more components operating in a second supply voltage domain different from the first supply voltage domain. Ensuring that a digital signal can cross from a first supply voltage domain to a second supply voltage domain while ensuring that components in the domains operate within desired operating parameters can be difficult.

Disclosure of Invention

According to a first aspect of the present disclosure, there is provided an apparatus comprising:

a first voltage domain circuit comprising first circuit components configured to provide a first digital output signal, wherein the first voltage domain circuit is configured to receive a first supply voltage, and wherein the first digital output signal has a high state and a low state, and a voltage of the high state is based on the first supply voltage;

a second voltage domain circuit comprising second circuit components, wherein the second voltage domain circuit is configured to receive a second supply voltage that is greater than the first supply voltage;

a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal at the elevated voltage level of the high state based on the first digital output signal, wherein the level shifter arrangement is configured to provide the second digital output signal for input to the second circuit component;

wherein the level shifter arrangement comprises at least one stage comprising an arrangement of one or more diode-connected PMOS transistors, a source terminal of at least one of the one or more diode-connected PMOS transistors being configured to be coupled to the second supply voltage, and a drain terminal of at least one of the one or more diode-connected PMOS transistors being coupled to a CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference;

the CMOS inverter arrangement of a first stage of the at least one stage is configured to receive the first digital output signal, and the CMOS inverter arrangement of a last stage of the at least one stage is configured to output the second digital output signal.

In one or more examples, the one or more CMOS inverter arrangements of the level shifter include a PMOS transistor, wherein the first terminal includes a source terminal of the PMOS transistor, a drain terminal directly or indirectly connected to a drain terminal of an NMOS transistor, and wherein the source terminal of the NMOS transistor is for direct or indirectly coupling to a reference voltage, the CMOS inverter arrangement having an input including gate terminals of the PMOS and NMOS transistors and an output including a node between the drain terminal of the PMOS transistor and the drain terminal of the NMOS transistor.

In one or more examples, the CMOS inverter arrangement of the last stage of the at least one stage is configured to output the second digital output signal from a node between a PMOS transistor and an NMOS transistor of the CMOS inverter arrangement.

In one or more examples, the CMOS inverter arrangement of any stage prior to the last stage is configured to provide an output from a node between a PMOS transistor and an NMOS transistor of the CMOS inverter arrangement.

In one or more embodiments, the level shifter arrangement includes at least two stages, including a first stage and a second stage;

wherein the first stage comprises a first arrangement of one or more diode-connected PMOS transistors, a source terminal of at least one of the one or more diode-connected PMOS transistors configured to be coupled to the second supply voltage, and a drain terminal of at least one of the one or more diode-connected PMOS transistors coupled to a first CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference; and is

Wherein the second stage comprises a second arrangement of one or more diode-connected PMOS transistors, a source terminal of at least one of the one or more diode-connected PMOS transistors configured for coupling to the second supply voltage and a drain terminal of at least one of the one or more diode-connected PMOS transistors coupled to a second CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference;

wherein the first CMOS inverter arrangement is configured to receive the first digital output signal and provide a first intermediate digital output signal to the second CMOS inverter arrangement of the second stage, wherein the second CMOS inverter arrangement is configured to receive the intermediate digital output signal and provide the second digital output signal to the second circuit component; and is

Wherein the first and second arrangements of diode-connected PMOS transistors are configured such that a voltage drop provided by the first arrangement is greater than a voltage drop provided by the second arrangement.

In one or more examples, the level shifter arrangement includes at least one additional stage following the at least one stage, the at least one additional stage comprises a CMOS inverter arrangement without one or more diode-connected PMOS transistor arrangements, the CMOS inverter arrangement of the additional stage comprises a PMOS transistor having a source terminal for coupling to receive the second supply voltage, a drain terminal connected directly or indirectly to a drain terminal of an NMOS transistor, and wherein the source terminal of the NMOS transistor is for coupling directly or indirectly to the reference voltage, the CMOS inverter arrangement of the additional stage has an input comprising gate terminals of the PMOS transistor and the NMOS transistor and an output comprising a node between the drain terminal of the PMOS transistor and the drain terminal of the NMOS transistor.

In one or more examples, the first intermediate output signal is output from a node between a PMOS transistor and an NMOS transistor of the CMOS inverter arrangement.

In one or more examples, there is an even number of stages. In one or more examples, each stage is configured to raise a trip voltage level of the CMOS inverter arrangement of the respective stage to the second supply voltage relative to the CMOS inverter arrangement of the preceding stage by the arrangement of one or more diode-connected PMOS transistors in each stage.

In one or more embodiments, the arrangement of one or more diode-connected PMOS transistors includes one of:

a plurality of diode-connected PMOS transistors connected in series; and

a plurality of diode-connected PMOS transistors connected in parallel.

In one or more embodiments, the arrangement includes a plurality of diode-connected PMOS transistors connected in series, and wherein at least one or more of the diode-connected PMOS transistors has a separate n-well.

In one or more embodiments, the first arrangement comprises a plurality of diode-connected PMOS transistors connected in series and the second arrangement comprises one or more diode-connected PMOS transistors connected in series, and the difference in voltage drop is provided by a greater number of diode-connected PMOS transistors connected in series in the first arrangement relative to the number of diode-connected PMOS transistors connected in series in the second arrangement.

In one or more embodiments, the first arrangement comprises one or more diode-connected PMOS transistors connected in parallel, and the second arrangement comprises a plurality of diode-connected PMOS transistors connected in parallel, and the difference in voltage drop is provided by a greater number of diode-connected PMOS transistors connected in parallel in the second arrangement relative to the number of diode-connected PMOS transistors connected in parallel in the first arrangement.

In general, and in one or more examples, each arrangement of one or more diode-connected PMOS transistors of each stage comprises a chain of diode-connected PMOS transistors, wherein a first diode-connected PMOS transistor in the chain or a first parallel-connected plurality of diode-connected PMOS transistors in the chain has one or more source terminals for coupling to the second supply voltage, and one or more drain terminals for coupling to zero, one or more subsequent diode-connected PMOS transistors in the chain or a subsequent parallel-connected plurality of diode-connected PMOS transistors in the chain, and then to the first terminal of the CMOS inverter arrangement.

In one or more embodiments, the level shifter arrangement comprises at least three stages, and the voltage drop of the diode-connected PMOS transistor arrangement of each of the at least three stages gradually and monotonically decreases from the first stage receiving the first digital output signal to a last stage of the at least three stages providing the second digital output signal for the second circuit component.

In one or more embodiments, each of the diode-connected PMOS transistors of the first and second arrangements has the same unit size.

In one or more embodiments, the level shifter arrangement comprises:

a high trigger level first stage comprising an arrangement of the one or more diode-connected PMOS transistors, a source terminal of at least one of the one or more diode-connected PMOS transistors configured to be coupled to the second supply voltage and a drain terminal of at least one of the one or more diode-connected PMOS transistors coupled to a high trigger level CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference;

the high trigger level CMOS inverter arrangement of the high trigger level first stage configured to receive the first digital output signal and provide a high trigger level output signal;

a low trigger level first stage comprising an arrangement of one or more diode-connected PMOS transistors, a source terminal of at least one of the one or more diode-connected PMOS transistors configured to be coupled to the second supply voltage and a drain terminal of at least one of the one or more diode-connected PMOS transistors coupled to a low trigger level CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference;

the low trigger level CMOS inverter arrangement of the low trigger level first stage is also configured to receive the first digital output signal and provide a low trigger level output signal;

wherein the high-trigger level CMOS inverter arrangement and the low-trigger level CMOS inverter arrangement each comprise a PMOS transistor having a source terminal for coupling directly or indirectly to a respective arrangement of one or more diode-connected PMOS transistors, and a drain terminal for connecting directly or indirectly to a drain terminal of an NMOS transistor, and wherein the source terminal of the NMOS transistor is for coupling directly or indirectly to the reference voltage;

wherein in the high trigger level CMOS inverter arrangement, a width-to-length ratio of the PMOS transistor is greater than a width-to-length ratio of the NMOS transistor, and in the low trigger level CMOS inverter arrangement, a width-to-length ratio of the NMOS transistor is greater than a width-to-length ratio of the PMOS transistor;

a latch configured to receive the high trigger level output signal and the low trigger level output signal and to combine the high trigger level output signal and the low trigger level output signal to generate a combined digital signal; and

a final stage comprising a CMOS logic inverter configured to receive the combined digital signal and output the second digital signal.

In one or more embodiments, the first stage includes a switch configured to short one of the diode-connected PMOS transistors of the first arrangement, the switch being controlled by an output of the second stage.

In one or more embodiments, the switch comprises a transistor having source and drain terminals coupled to short the one of the diode-connected PMOS transistors of the first arrangement, and a gate terminal coupled to the second CMOS inverter arrangement to receive the second digital output signal.

In one or more embodiments, the first CMOS inverter arrangement comprises a PMOS transistor connected in series with an NMOS transistor, and wherein the PMOS transistor of the first CMOS inverter arrangement has a connection between its source terminal and its back gate terminal.

In one or more embodiments, the level shifter arrangement includes an NMOS transistor for high voltage protection having a drain terminal for receiving the first digital output signal and a source terminal for providing the first digital output signal to the CMOS inverter arrangement of a first stage of the at least one stage, wherein a gate of the NMOS transistor for high voltage protection is coupled to receive the second supply voltage.

In one or more embodiments, the NMOS transistor for high voltage protection comprises a double diffused metal oxide semiconductor DMOS transistor.

According to a second aspect of the present disclosure, there is provided a wireless communication device comprising an apparatus according to any preceding claim. The wireless communication device may comprise part of a communication device, such as a mobile phone or a base station.

While the disclosure is susceptible to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. However, it is to be understood that other embodiments beyond the specific embodiments described are possible. The intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims.

The above discussion is not intended to represent each example embodiment, or every implementation, within the scope of the present or future claim sets. The detailed description that follows and the drawings also illustrate various example embodiments. Various example embodiments may be more completely understood in consideration of the following detailed description in connection with the accompanying drawings.

Drawings

One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 illustrates an example embodiment of first and second voltage domain circuits and a first digital output signal to be passed therebetween;

FIG. 2 shows a first example embodiment illustrating the use of a first example arrangement of diode-connected PMOS transistors to receive a first digital output signal;

FIG. 3 shows a second example embodiment illustrating the use of a second example arrangement of diode-connected PMOS transistors to receive a first digital output signal;

fig. 4 shows a third example embodiment with an additional stage for implementing hysteresis based on the arrangement of either of fig. 2 and 3;

FIG. 5 shows a fourth example embodiment based on the arrangement of either of FIGS. 2 and 3 with an alternative arrangement for implementing hysteresis without a separate stage;

FIG. 6 shows a fifth exemplary embodiment illustrating increased high voltage protection that may be applied in any of the other embodiments;

FIG. 7 shows a sixth exemplary embodiment illustrating increased high voltage protection that may be applied in any of the other embodiments; and

fig. 8 shows an apparatus, e.g. a wireless communication apparatus, comprising the device of any of the previous embodiments.

Detailed Description

In some electronic devices, digital signaling must cross from a first power domain to a second power domain. Thus, digital signaling generated by a first circuit component powered by a first power domain needs to be efficiently received by a second digital circuit component powered by a second power domain. It may also be important that the voltage level of the digital signaling does not result in poor characteristics of the second circuit component. In other words, it may be desirable that the voltage level of the digital signaling is complementary to the logic high and/or logic low trigger level of the digital logic of the second circuit component.

Fig. 1 shows a device 100 comprising a first voltage domain circuit 101, the first voltage domain circuit 101 comprising a first circuit component 102 configured to provide a first digital output signal at an output terminal 103. The first voltage domain circuit 101 includes: a voltage supply terminal 104 for receiving a first power supply voltage from a power supply line 105; and a voltage reference terminal 106 for coupling to a reference voltage on line 107, such as ground. The first circuit component 102 comprises a digital logic component, which in this example is shown as a logic inverter. It should be appreciated that the first circuit component 102 may include any single digital logic component or arrangement of multiple digital logic components (e.g., "and," "or," "not," or the like, or combinations thereof). In one or more examples, the first circuit component 102 includes a CMOS based digital logic component. It should be appreciated that the first digital output signal provided at the output terminal 103 has a high state and a low state, and the voltage of the high state is based on (e.g., substantially equal to) the first supply voltage. Thus, although the first circuit component 102 may be configured to generate logic high and logic low signals using the first supply voltage, there may be losses and voltage drops across the logic. Thus, the first digital output signal has logic high and logic low states whose voltages depend on the first supply voltage of the first power domain circuit 101.

Fig. 1 also shows a second voltage domain circuit 108 comprising a second circuit component 109. The second voltage domain circuit 108 includes: a voltage supply terminal 110 for receiving a second power supply voltage from a power supply line 111; and a voltage reference terminal 112 for coupling to a reference voltage on line 107, such as ground. The second circuit component 109 comprises a digital logic component, which in this example is shown as a logic inverter. In one or more examples, the second circuit component 109 includes a CMOS based digital logic component. It should be appreciated that the second circuit component 109 may include any single digital logic component or arrangement of multiple digital logic components (e.g., "and," "or," "not," or the like, or combinations thereof). The second voltage domain circuit 108 comprises an input 113 for receiving the first digital output signal. The second circuit component 109 may be configured to operate based on a logic high or a logic low received at the input 113. The second supply voltage configured to power the digital logic of the second circuit assembly 109 is greater than the first supply voltage to power the digital logic of the first circuit assembly 102. Thus, there may be a difference between the voltage range considered to be a logic high in the first voltage domain circuitry 101 as compared to the voltage range considered to be a logic high in the second voltage domain circuitry 108. In one or more instances, an undesirable result of such a difference may be the occurrence of a cross current, shown by arrow 114, from the second voltage supply to ground through the digital logic of the second circuit assembly 109.

In general, the second circuit component 109 includes an arrangement of one or more transistors configured to form a digital logic circuit, such as the aforementioned logic inverter. The logic inverter may include a PMOS transistor having a source terminal for coupling directly or indirectly to the second supply voltage, a drain terminal connected directly or indirectly to a drain terminal of the NMOS transistor, and wherein the source terminal of the NMOS transistor is for coupling directly or indirectly to the reference voltage, wherein the first circuit component is configured to provide the first digital output signal to the gate terminals of both the PMOS transistor and the NMOS transistor, and the output signal of the second circuit component is provided from a node between the drain terminal of the PMOS transistor and the drain terminal of the NMOS transistor.

In general, the first circuit component 102 includes an arrangement of one or more transistors configured to form a digital logic circuit, such as the aforementioned logic inverter. The logic inverter may include a PMOS transistor having a source terminal for coupling directly or indirectly to the first supply voltage, a drain terminal for connecting directly or indirectly to a drain terminal of the NMOS transistor, and wherein the source terminal of the NMOS transistor is for coupling directly or indirectly to the reference voltage, wherein the first circuit component is configured to provide the first digital output signal from a node between the drain terminal of the PMOS transistor and the drain terminal of the NMOS transistor.

Fig. 2 shows the second voltage domain circuitry 108 in more detail and includes a first example embodiment in which the second voltage domain circuitry 108 includes a level shifter arrangement 200. The level shifter arrangement 200 is configured to receive the first digital output signal at the input 113 and to provide or generate a second digital output signal at the output 201 for reception by the second circuit component 109. The second circuit assembly 109 is shown as a CMOS inverter arrangement. The second digital output signal may be considered a modified version of the first digital output signal.

The second digital output signal is based on the first digital output signal in terms of the data content of the reproduced logic high and logic low signals, but the voltage levels representing logic high and logic low in the second digital output signal may be different. In particular, the second digital output signal may have a raised (e.g., average) voltage level of the high state compared to a (e.g., average) voltage level of the high state in the first digital output signal.

Accordingly, the level shifter arrangement 200 may be configured to provide the second digital output signal for input to the second circuit component 109, and in one or more examples, the occurrence of the crossover current 114 may be overcome or reduced.

The level shifter arrangement 200 comprises at least one stage. In the example fig. 2, three stages 201, 202 and 203 are shown. A first stage of the one or more stages 201, 202 and 203, which in this example comprises the first stage 201, is configured to receive the first digital output signal from the input 113. Said first digital output signal is then passed in sequence from stage to stage, i.e. from the first stage 201 to the second stage 202, in said first stage 201 said first digital output signal may be referred to as a first intermediate digital output signal; first from the second stage, where the first digital output signal may be referred to as a second intermediate digital output signal, to the third stage 203, and the second digital output signal is output from the last stage of the one or more stages 201, 202 and 203, which in this example includes the third stage 203. It should be appreciated that in examples where the level shifter arrangement 200 includes a single stage, the first and last stages include the same single stage.

In general, each of the stages 201, 202, 203 comprises a structure similar in that the stage comprises an arrangement 204, 205, 206 of one or more diode-connected PMOS transistors coupled in series between the voltage supply terminal 110 and the voltage reference terminal 112, and a CMOS inverter arrangement 207, 208, 209. Thus, in one or more examples, the source terminal 210 of one of the one or more diode-connected PMOS transistors 220, 240, or 260, referred to as a first diode-connected PMOS transistor, is coupled to receive the second supply voltage from the supply line 111. In one or more examples, a drain terminal 211 of one of the one or more diode-connected PMOS transistors 224, 242, or 260, referred to as a last diode-connected PMOS transistor, is coupled to a respective CMOS inverter arrangement 207, 208, 209. Thus, the CMOS inverter arrangement 207, 208, 209 has a first terminal 212 coupled to said drain terminal 211 and a second terminal 213 coupled to the voltage reference terminal 112 for receiving a reference voltage.

In one or more examples, it is the CMOS inverter arrangement 207 of the first stage 201 that receives the first digital output signal from the input 113. The first digital output signal is then passed between the CMOS inverter arrangements 207, 208, 209 of each stage to the last CMOS inverter arrangement 209 of the third stage 203 and the second digital output signal is output therefrom.

In one or more examples, the CMOS inverter arrangement 207, 208, 209 of each stage 201, 202, 203 of the level shifter 200 includes a PMOS transistor 214, 215, or 216 and an NMOS transistor 217, 218, or 219 coupled through their respective drain terminals. The first terminal 212 comprises the source terminal of the PMOS transistor 214, 215 or 216 and the second terminal 213 comprises the source terminal of the NMOS transistor 217, 218 or 219.

The CMOS inverter arrangements 207, 208, 209 each have an input 225, 245, 265 for receiving a first digital signal from the input 113 or a previous stage 201, 202, 203. The inputs 225, 245, 265 are split to couple to the gate terminals of the PMOS 214, 215 or 216 and NMOS transistor 217, 218 or 219 of the respective CMOS inverter arrangement. The CMOS inverter arrangement 207, 208, 209 has an output 226, 246, 266, which output 226, 246, 266 comprises a node between a drain terminal of the respective PMOS transistor 214, 215 or 216 and a drain terminal of the respective NMOS transistor 217, 218 or 219.

Thus, in general, the CMOS inverter arrangement 207 comprises PMOS and NMOS transistors with drain terminals connected, and the first stage 201 of the at least one stage is configured to receive the first digital output signal at gate terminals of the PMOS and NMOS transistors. The CMOS inverter arrangement 209 of the last stage 203 of the at least one stage is configured to output the second digital output signal from an output 266, the output 266 comprising a node between the PMOS216 and the NMOS transistor 219 of the CMOS inverter arrangement.

Turning now to the arrangement of one or more diode-connected PMOS transistors 204, 205, 206, as will be understood by those skilled in the art, a diode-connected PMOS transistor comprises a p-channel MOSFET having a connection between its gate terminal and its drain terminal. In general, the arrangements 204, 205, 206 each comprise a chain of diode-connected PMOS transistors, wherein a first diode-connected PMOS transistor in the chain has a source terminal for coupling to a second supply voltage, and a drain terminal for coupling to zero, one or more subsequent diode-connected PMOS transistors in the chain, and then to the first terminal 212 of the respective CMOS inverter arrangement. It is to be appreciated that in other examples, the arrangements 204, 205, 206 may have additional connections, for example from the second power source 111, and/or may have other components coupled to the arrangements.

The first arrangement 204 of diode-connected PMOS transistors comprises three diode-connected PMOS transistors 220, 222, 224 connected in series. The second arrangement 205 of diode-connected PMOS transistors comprises two diode-connected PMOS transistors 240, 242 connected in series. The third arrangement 206 of diode-connected PMOS transistors comprises one diode-connected PMOS transistor 260.

In one or more examples, the first arrangement 204 and the second arrangement 205 of diode-connected PMOS transistors are configured such that the voltage drop provided by the first arrangement 204 is greater than the voltage drop provided by the second arrangement 205. Likewise, the second arrangement 205 and the third arrangement 206 of diode-connected PMOS transistors may be configured such that the voltage drop provided by the second arrangement 205 is greater than the voltage drop provided by the third arrangement 206.

In this example, the difference in voltage drop is provided by a greater number (two) of diode-connected PMOS transistors 220, 222, 224 (three) connected in series in the first arrangement 204 relative to the number (two) of diode-connected PMOS transistors 240, 242 connected in series in the second arrangement 205. Similarly, the difference in voltage drop is provided by a greater number (one) of diode-connected PMOS transistors 240, 242 (two) connected in series in the second arrangement 205 relative to the number of diode-connected PMOS transistors 260 connected in series in the third arrangement 206.

By using an arrangement 204, 205, 206 of diode-connected PMOS transistors on top of a respective CMOS inverter arrangement 207, 208, 209, the stage effectively lowers the supply voltage of the CMOS inverter arrangement by the threshold voltage (e.g., V for each diode-connected PMOS transistor used in the stage_th) And thereby effectively reduce the trip voltage level of the CMOS inverter arrangement. It should be appreciated that the trip voltage level is a characteristic of the CMOS inverter arrangement that defines the point at which the CMOS inverter arrangement switches states. Thereby, the different stages 201, 202, 203 gradually increase the supply voltage. Such a "diode-based grading" may be used to perform a level shift from the lower power domain 101 to the higher power domain 108. In one or more examples, each stage is configured to raise a trip voltage level of the CMOS inverter arrangement of the respective stage to the second supply voltage relative to the CMOS inverter arrangement of the preceding stage by the arrangement of one or more diode-connected PMOS transistors in each stage. This arrangement may also reduce the DC current in at least the second circuit component. One or more of diode-connected PMOS arranged in a graded mannerThe arrangement reduces the effective local voltage across each respective CMOS inverter arrangement and may thereby reduce or minimize quiescent current consumption.

The embodiment of fig. 2 shows "series tapering". The number of diode-connected PMOS transistors needed to convert from the first supply voltage at input 113 to the second supply voltage of second circuit 108 can be determined by dividing the voltage difference (i.e., first supply voltage-second supply voltage) by a threshold voltage, which, as will be known to those skilled in the art, includes the voltage at which the inversion layer of diode-connected PMOS transistors is formed, or in other words, the voltage at which the transistors are on.

In one or more examples, two or more of the diode-connected PMOS transistors may have separate n-wells. This has been found to reduce the bulk effect. A separate n-well may be used to lower the threshold voltage of the diode-connected PMOS transistors of the respective arrangements 204, 205, 206, thereby shifting up the trip voltage level of the respective CMOS inverter arrangements 207, 208, 209. It will be appreciated that the voltage present between the n-well and source terminals affects the threshold voltage, and thus the trip voltage level (in combination with the width/length scaling of the diode-connected PMOS transistor).

In one or more examples, there is an even number of stages. In one or more examples, there are an odd number of stages.

The use of an arrangement of diode-connected PMOS transistors may be advantageous because the arrangement may not be affected by body effects. For example, if NMOS transistors are used instead, a large Vgs voltage may occur. In addition, the level shifter of this embodiment or any other embodiment may only require the second supply voltage, thereby simplifying layout.

In the example of fig. 2, the arrangement 204, 205, 206 of diode-connected PMOS transistors comprises series-connected diode-connected PMOS transistors. The example embodiment of fig. 3 shows an arrangement of diode-connected PMOS transistors as including diode-connected PMOS transistors connected in parallel.

Example fig. 3 shows a level shifter 300 having three stages (a first stage 301, a second stage 302, and a third stage 303) similar to the stages of fig. 2. Similar to the example fig. 2, the first stage includes a first arrangement 304 of diode-connected PMOS transistors connected in series to the CMOS inverter arrangement 307 between the second voltage supply 111 and the reference voltage 107. The second stage comprises a second arrangement 302 of diode-connected PMOS transistors connected in series to a second CMOS inverter arrangement 308 between the second voltage supply 111 and the reference voltage 107. The third and last stage comprises a third arrangement 306 of diode-connected PMOS transistors connected in series to the CMOS inverter arrangement 309 between the second voltage supply 111 and the reference voltage 107. As in the previous example, the first CMOS inverter arrangement 307 receives the first digital output signal from the input 113 and the last CMOS inverter arrangement 308 outputs the second digital control signal at the output 201 to the second circuit component 109. The structure and operation of the CMOS inverter arrangements 307, 308 and 309 are the same as in the previous example embodiments.

In the example fig. 3, the arrangements 304, 305, and 306 differ from the example fig. 2. Each arrangement 304, 305, 306 has a different number of diode-connected PMOS transistors connected in parallel. Specifically, the latter stage has a larger number of diode-connected PMOS transistors connected in parallel than the former stage. These differently sized parallel arrangements thus have different current capacities, and therefore the voltage drop across the arrangement can be graded across the stages 301, 302, 303. In one or more examples, the first arrangement 304 and the second arrangement 305 are configured such that the voltage drop provided by the first arrangement 204 is greater than the voltage drop provided by the second arrangement 205. Likewise, the second arrangement 205 and the third arrangement 206 are configured such that the voltage drop provided by the second arrangement 205 is greater than the voltage drop provided by the third arrangement 206.

In the example fig. 3, it will be appreciated that the source terminals of the parallel-connected diode-connected set of PMOS transistors will be configured to be coupled to the power supply line 111. Likewise, the drain terminals of the parallel-connected groups of diode-connected PMOS transistors will be configured to be coupled to first terminals of the respective CMOS inverter arrangements 307, 308, 309.

Using multiple diode-connected PMOS transistors in parallel effectively doubles the width, and thus doubles the total current capacity, of the diode-connected PMOS transistors. This will in turn reduce the required overdrive voltage so that the trip level of the CMOS inverter arrangement of the respective stage will be shifted up. Those skilled in the art will appreciate that the overdrive voltage comprises an additional voltage (overdrive voltage) above the threshold voltage required to maintain the predetermined amount of current.

In the example of fig. 3, the CMOS inverter arrangements 307, 308, 309 of each stage use different sized diode-connected PMOS arrangements 304, 305, 306 by using diode-connected PMOS transistors of a unit size, e.g., width (W)/length (L) 1/5, and placing multiple diode-connected PMOS transistors in parallel. In the present example, the first arrangement 304 may comprise one diode-connected PMOS transistor with a W/L ratio of 1/5. Therefore, the diode-connected PMOS transistor 320 represents a single unit-sized diode-connected PMOS transistor. The second arrangement 305 may be constructed of five unit-sized (W/L ratio of 1/5) diode-connected PMOS transistors in parallel. Thus, the diode-connected PMOS transistor 340 represents a parallel-connected group of five unit-sized diode-connected PMOS transistors. The third arrangement 306 may be constructed of twenty-five unit-sized (W/L ratio of 1/5) diode-connected PMOS transistors in parallel. Thus, diode-connected PMOS transistor 360 represents a parallel-connected group of twenty-five unit-sized diode-connected PMOS transistors. Using unit-sized PMOST diodes may allow for simplified back-end layout design. It should be appreciated that a different number of diode-connected PMOS transistors connected in parallel may be used in other examples. Although in this example the parallel connected arrangements 304, 305, 306 are embodied by a different number of diode connected PMOS transistors connected in parallel, it will be appreciated that it may be equivalent to provide an arrangement with an increased W/L ratio from the first stage 301 to each subsequent stage 302, 303.

In one or more examples, the level shifters 200, 300 may include different combinations of groups of diode-connected PMOS transistors connected in parallel and chains of diode-connected PMOS transistors connected in series. Whichever layout of diode-connected PMOS transistors is used in each of the arrangements 204, 205, 206, 304, 305, 306, the arrangement may be selected to provide a reduced voltage drop and an increased trip voltage level across the associated CMOS inverter arrangement of the stages 201, 202, 203.

In further embodiments, the principles of the first and second exemplary embodiments may be applied. The example embodiment of fig. 4 includes an example of increasing hysteresis. Hysteresis is typically added to the input buffer of the digital logic circuit to suppress interference caused by noise superimposed on the slowly varying signal.

To implement hysteresis, two different levels are required, where a first level defines a transition from a low state to a high state and the other level defines a transition from a high state to a low state, where hysteresis comprises a difference. These levels may be achieved using two separate CMOS inverter arrangements, each connected to receive the first digital signal.

The level shifter arrangement 400 of example fig. 4 includes two first stages 401A and 401B. The two first stages include a high trigger level first stage 401A and a low trigger level first stage 401B. In this example, there is a second stage 402A for the high trigger level first stage 401A. There is no second stage associated with the low trigger level first stage 401B. However, in other embodiments, the high trigger level stage may have at least one, two, or more stages, and the low trigger level stage may have at least one, two, or more stages.

The high trigger level first stage 401A includes an arrangement 404A of one or more diode-connected pmos (DPMOS) transistors, which in this example, arrangement 404A includes first and second series-connected DPMOS 420, 421 (although other arrangements are possible). The source terminal of the first DPMOS 420 is configured to be coupled to a second supply voltage and the drain terminal of the second DPMOS transistor 421 is coupled to the high trigger level CMOS inverter arrangement 407A. As in the previous example, the high trigger level CMOS inverter arrangement 407A has a first terminal coupled to the drain terminal of the second DPMOS421 and a voltage reference terminal for coupling to the voltage reference line 107. The high trigger level CMOS inverter arrangement 407A of the high trigger level first stage 401A is configured to receive the first digital output signal from the input 113 and provide a high trigger level output signal at 410. In accordance with the principles herein, one or more stages may be included through which the first digital output signal passes before becoming the second digital output signal provided for the second component 109.

In this example, the high trigger level CMOS inverter arrangement 407A of the high trigger level first stage 401A provides an intermediate high trigger level signal at 411 that is passed to the second high trigger level CMOS inverter arrangement 408A of the second high trigger level stage 402A. Thus, it is the second high trigger level CMOS inverter arrangement 408A that outputs the high trigger level output signal at 410.

Level shifter 400 includes a low-trigger level first stage 401B that includes, consistent with all embodiments, an arrangement 404B of one or more DPMOS transistors 422 and a low-trigger level CMOS inverter arrangement 407B. The source terminal of DPMOS transistor 422 is configured to be coupled to second supply voltage 111, and the drain terminal of DPMOS transistor 422 (since there is only one transistor in this stage, rather than a chain of two or more transistors) is coupled to low trigger level CMOS inverter arrangement 407B. The low trigger level CMOS inverter arrangement 407B has a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference.

The low trigger level CMOS inverter arrangement 407B of the low trigger level first stage 401B is also configured to receive the first digital output signal from the input 113 and provide the low trigger level output signal as an output at 412.

The high-and low-trigger-level CMOS inverter arrangements 407A, 408A, 407B may each include a PMOS transistor 413, 415 having a source terminal for coupling directly or indirectly to the respective arrangement of one or more DPMOS transistors 404A, 405A, 404B, and a drain terminal connected directly or indirectly to the drain terminal of the NMOS transistor 414, 416, and wherein the source terminal of the NMOS transistor is for coupling directly or indirectly to a reference voltage at 107. As in the previous example, the inputs to the high and low trigger level CMOS inverter arrangements 407A, 408A, 407B may comprise the gate terminals of the constituent PMOS and NMOS transistors, and the output comprises the node between the connected drain terminals.

In the high trigger level CMOS inverter arrangement 407A of at least the first stage 401A, the width to length ratio (e.g., 10/1) of the PMOS transistor 413 is greater than the width to length ratio (e.g., 2/2) of the NMOS transistor 414. Thus, PMOS 413 may be considered strong, while NMOS 414 may be considered weak.

In the low trigger level CMOS inverter arrangement 407B, the width-to-length ratio (e.g., 10/1) of the NMOS transistor 416 is greater than the width-to-length ratio (e.g., 2/2) of the PMOS transistor 415. Thus, PMOS 415 may be considered weak, while NMOS 416 may be considered strong.

The difference in strength between the PMOS and NMOS in the low-trigger level CMOS inverter arrangement 407B and the high-trigger level CMOS inverter arrangement 407A provides different trip voltage levels for implementing hysteresis. In addition, the DPMOS transistors of arrangements 404A and 404B may be scaled differently to support different trigger levels. Thus, the aspect ratio of the DPMOS transistors of arrangement 404A may be greater than the aspect ratio of the DPMOS transistors of arrangement 404B.

Level shifter 400 additionally includes a latch 417 to combine the high trigger level output signal at 410 with the low trigger level output signal at 412 to provide a combined digital signal at 418. The combined digital signal at 418 is received by a logic inverter 419, the logic inverter 419 being further configured to and output an inverted version of the combined digital signal, the inverted version comprising the second digital signal, for receipt by the second circuit component 109. In other examples, the second circuit component 109 may be connected to the output 437 and two or more inverters may be scaled to drive a particular load at 437. In this example, two inverters with increased current drive capability or "strength" may be used.

In this example and one or more examples, the level shifter arrangement includes a high trigger level second stage 402A. However, in one or more examples, the second stage may be replaced by a logic inverter, such as a CMOS logic inverter. Thus, the embodiment of fig. 4 may enable logical inversion of the output of the high trigger level first stage 401A, whether implemented as a stage (and thus comprising serially connected DPMOS transistors and a CMOS inverter arrangement between the second supply and the reference voltage) or as a CMOS logic inverter. Thus, the second stage 402A or alternate logic inverter is used to invert the signal polarity of the output from the high trigger level CMOS inverter arrangement 407A so that the high trigger level signal is in phase with the first digital output signal at terminal 113, while the low trigger level output signal from the low trigger level CMOS inverter arrangement 407B is out of phase with the first digital output signal at terminal 113.

In the example of fig. 4, latch 417 includes a first branch 430 and a second branch 431. Each branch includes a terminal coupled at one end to the second voltage supply at line 111, and a terminal coupled at the other end to the voltage reference at line 107. The first branch 430 includes a PMOS transistor 432 and the second branch includes a PMOS transistor 433. Because the gate terminal of PMOS 432 is coupled to the drain terminal of PMOS 433 and the gate terminal of PMOS 433 is coupled to the drain terminal of PMOS 432, the PMOS transistors 432, 433 of each branch are cross-coupled.

Branches 430 and 431 each include an NMOS transistor. A first NMOS transistor 434 is provided in the first branch 430 to receive a low trigger level output signal at its gate terminal, and a second NMOS 435 is provided in the second branch 431 to receive a high trigger level output signal at its gate terminal. Providing a combined digital signal from node 436 of one of the first and second branches; in this case, the one branch is the second branch 431. Thus, the node 436 is between one of the cross-coupled PMOS transistors 432 or 431 and a respective one of the first or second NMOS transistors 434 or 436 of the same branch 430, 431.

The use of latch 417 may be advantageous because latch 417 not only combines two signals into a single output, but also generates a full-swing output signal to reduce the need for multiple stages as provides the aforementioned tapering.

In one or more embodiments, one or more of the first series-connected DPMOS 420, the second series-connected DPMOS421, and the PMOS of the CMOS inverter arrangement 407A may have a back-gate terminal coupled to receive the second supply voltage. It should be appreciated that in fig. 4, connection 438 provides a second supply voltage to the second DPMOS421 and the back gate terminal of the PMOS transistor 413. In one or more embodiments, one or more of the first series-connected DPMOS 423, the second series-connected DPMOS 424, and the PMOS 415 of the CMOS inverter arrangement 407B may have a back-gate terminal coupled to receive the second supply voltage.

Example the embodiment of fig. 4 may advantageously provide hysteresis. However, with the example embodiment of FIG. 5, hysteresis may be achieved without the complexity of high and low trigger levels.

Example fig. 5 shows a level shifter 500 having three stages including a first stage 501, a second stage 502, and a third stage 503. Each stage 501-503 comprises an arrangement 508, 512, 514 of one or more DPMOS transistors coupled in series with a CMOS inverter arrangement 516, 517, 518 between the second voltage supply 111 and a reference voltage, i.e., ground 107. The level shifter 500 also optionally includes one or more CMOS logic inverters-three CMOS logic inverters in this example, including 504, 505, 506-before providing the second output signal at output 507.

In general, it should be appreciated that the level shifter 500 of fig. 5 may have at least two stages 501, 502, 503 and zero, at least one, or at least two CMOS logic inverters 504, 505, 506.

DPMOS arrangement 508 of first stage 501 includes a first DPMOS transistor 510 and a second DPMOS transistor 511 (which may indicate a plurality of parallel-connected DPMOS transistors as in the previous example). The DPMOS arrangement 512 of the second stage 502 includes a single DPMOS transistor 513 (or a plurality of parallel-connected DPMOS transistors). The DPMOS arrangement 514 of the third stage 503 comprises a single DPMOS transistor 515 (or a plurality of parallel-connected DPMOS transistors).

In this example, hysteresis is provided by the presence of a switch 520, the switch 520 being configured to short circuit the one or more diode-connected PMOS transistors 510, 511 of the first arrangement 508 by selectively providing an alternative current path that can be switched on and off. In this example, the switch 520 is configured to selectively short the second DPMOS 511. The switches are controlled by the output of the CMOS inverter arrangement of the second stage 502. Such an arrangement may advantageously provide hysteresis with reduced complexity.

The switch 520 may comprise a transistor, such as a PMOS transistor, with a source terminal coupled to the source terminal of one of the DPMOS transistors 511 and a drain terminal coupled to the drain terminal of the same DPMOS transistor 511. The gate terminal of the switch 510 is coupled to the output of the second CMOS inverter arrangement 517 at 521 to receive the second digital output signal or an intermediate digital output signal between the second and third stages, depending on the number of stages provided.

In one or more examples, the back gate terminal of the second DPMOS transistor 511 (i.e., the transistor or transistors shorted by the switch) may be coupled to the second supply voltage at line 111. In one or more examples, the back gate terminal of switch 520 may be coupled to the second supply voltage at line 111. A connection 528 is shown that provides a back gate connection.

In general, for either embodiment, the back-gate terminal of at least one of the DPMOS transistors may be coupled at 111 to a second supply voltage, which may advantageously be used to control the trigger level of the CMOS inverter arrangements 516, 517, 518.

In one or more examples, the first CMOS inverter arrangement 516 includes a PMOS transistor 522 connected in series with an NMOS transistor 523, and wherein the PMOS transistor 522 has a connection 524 between its source terminal and its back gate terminal. Such a connection 524 may be provided to reduce the effects of body effects.

Thus, in use, the first CMOS inverter arrangement 516 receives the first digital output signal at the gate terminals of its constituent PMOS and NMOS transistors 522, 523. The output from the node between the connected drain terminals is used to drive the second CMOS inverter arrangement 517. The second CMOS inverter arrangement 517 in turn drives a third CMOS inverter arrangement 518. In this example, the third CMOS inverter arrangement is the last stage and its output is provided to drive three CMOS inverters 504, 505, 506 which are sized to properly drive the particular load connected at 507 (which may be considered an additional stage of the level shifter). As mentioned, hysteresis is achieved using a switch 520, which switch 520 shorts the DPMOS 511 and is driven by the output of the second CMOS inverter arrangement 517. Thus, when the voltage of the first output signal at 525 begins to be low, DPMOS transistor 511 is shorted and provides a higher trigger or trip level than when the first output signal at 525 is high. In the second state, when the first output signal at 525 is high, switch 520 is open and DPMOS 511 is not shorted, thus providing a lower trigger or trip level.

Thus, the selective shorting of the first DPMOS arrangement 508 provides hysteresis.

Example fig. 6 shows a further embodiment comprising one stage 601 and three CMOS inverters 602, 603 and 604. Stage 601 has the same general structure as in the previous embodiment.

However, in the example of fig. 6, the level shifter arrangement 600 includes an NMOS transistor 605 for high voltage protection. The NMOS transistor 605 has a drain terminal 606 for receiving the first digital output signal, and a source terminal 607 for providing the first digital output signal to the CMOS inverter arrangement 608 of the first stage 601 after the first digital output signal passes through the NMOS 605. The gate terminal 609 of the NMOS transistor 605 is coupled to receive the second supply voltage at line 111.

The NMOS transistor 605 for high voltage protection may comprise a double diffused metal oxide semiconductor DMOS transistor. In one or more examples, the NMOS transistor includes one of a VDMOS (vertical double diffused metal oxide semiconductor) and LDMOS (lateral double diffused metal oxide semiconductor) transistor.

It should be appreciated that any of the embodiments described herein may include the NMOS transistor 605 for high voltage protection. Using NMOS transistor 605 can produce a very large input voltage range. The NMOS transistor 605 will limit the voltage at the gate terminals of the PMOS and NMOS of the first CMOS inverter arrangement 608 and may thereby avoid damaging the gate oxides of these components. It will be appreciated that due to the threshold voltage of the NMOS transistor 605, the voltage at the gate terminals of the PMOS and NMOS of the first CMOS inverter arrangement 608 will remain well below the second supply voltage. In one or more examples, additional components or arrangements may be added to avoid quiescent current flow in the first stage 601, for example, by using serially connected DPMOS in the first DPMOS arrangement 610.

Example fig. 7 is substantially the same as example fig. 6, however, in this example, two stages 701, 702 and two CMOS inverters 703 and 704 are provided.

It has been found that using NMOS transistor 605 does not prevent operation at small input voltages and that series-connected DPMOS transistors 710 can effectively prevent quiescent current consumption during such operating conditions. Thus, a level shifter 600 having NMOS transistors for high voltage protection and at least one or at least two stages 601, 701, 702 may provide an "input buffer" with a truly wide input voltage range.

It should be appreciated that the level shifters 200, 300, 400, 500, 600, 700 may be considered "input buffers" that facilitate the passage of digital signaling from different voltage domains and provide for modification of the voltage levels of the digital signaling.

Example fig. 8 illustrates a wireless communication apparatus 800 comprising a device of any of embodiments 108, 300, 400, 500, 600 as described herein.

It is to be understood that any components that are said to be coupled may be directly or indirectly coupled or connected. In the case of indirect coupling, additional components may be disposed between the two components that are said to be coupled.

In this specification, example embodiments have been presented in terms of selected sets of details. However, those of ordinary skill in the art will understand that many other example embodiments may be practiced that include different selected sets of these details. It is intended that the appended claims cover all possible example embodiments.