阅读说明：本技术 一种用于小数分频锁相环中的改进型脉冲吞咽分频器及分频方法 (Improved pulse swallowing frequency divider and frequency dividing method for fractional frequency division phase-locked loop ) 是由 江金光 严培辉 于 2021-01-29 设计创作，主要内容包括：本发明涉及一种用于小数分频锁相环中的改进型脉冲吞咽分频器及分频方法,该结构包含一个4/5预分频器、一个可编程计数器和一个吞咽计数器,通过一个负载信号,实现了可编程计数器和吞咽计数器的同步设置功能。本发明避免了现有技术中存在的SR锁存器故障、分频比错误等问题,且MC延迟τ-(MC)非常低,最大输入频率可达7.04GHz,同时,受益于分频电路结构和TSPC结构的DFF,本发明的功耗也更低,非常适合高频低功耗的应用场景。(The invention relates to an improved pulse swallowing frequency divider and a frequency dividing method for a fractional frequency division phase-locked loop, the structure comprises an 4/5 prescaler, a programmable counter and a swallowing counter, and the synchronous setting function of the programmable counter and the swallowing counter is realized through a load signal. The invention avoids the problems of SR latch failure, frequency dividing ratio error and the like in the prior art, and MC delays tau MC The frequency divider has the advantages that the frequency divider is very low, the maximum input frequency can reach 7.04GHz, and meanwhile, the frequency divider has the benefit of DFF of a frequency dividing circuit structure and a TSPC structure, so that the power consumption is lower, and the frequency divider is very suitable for application scenes of high frequency and low power consumption.)

1. An improved pulse swallow frequency divider for use in a fractional division phase locked loop, comprising: comprises an 4/5 prescaler, a pulse counter and a swallow counter; the 4/5 prescaler, the pulse counter and the swallow counter are sequentially connected to form a closed loop, and the pulse counter and the swallow counter are synchronously arranged through a shaped narrow pulse signal.

2. An improved pulse swallow frequency divider for use in a fractional division phase locked loop, as claimed in claim 1, wherein: 4/5 the prescaler comprises three D flip-flops DFF0, DFF1 and DFF 2; an input signal CLK is input into DDF0, whose output signal qb is then connected to the d-port of DFF1, while a clock signal is input intoThe port c of the DFF1, the output port q of the DFF1 are connected to the clock port c of the DFF2, and the last three DFFs are connected through a three-input NAND gate; the three DFFs adopt true single-phase clock structures to reduce power consumption, each D trigger has the same structure and comprises 5 PMOS (P-channel metal oxide semiconductor) tubes and 6 NMOS (N-channel metal oxide semiconductor) tubes which are connected, wherein an input clock signal CLK (clock) is connected to one PMOS tube and one output NMOS tube, an input signal is controlled through a D0 port, and an output signal is output through a qb port; when MC is 0, the input D1 of DFF0 is set to high level, representing a divide-by-two D flip-flop; input d1 of DFF0 is qb in case MC is 1₁And q is₂Controlling; when qb₁1 and q₂When 1, the output of DFF0 remains high for two clock cycles.

3. An improved pulse swallow frequency divider for use in a fractional division phase locked loop, as claimed in claim 1, wherein: 4/5 the prescaler has a mixed mode of synchronous logic and asynchronous logic, including that when MC is 0, the synchronous logic unit divides the input signal by two, then through the asynchronous divide-by-two circuit, divides the input signal by four; when MC is 1, the output signal is fed back to the input, and the synchronous logic unit will become divide by three, and the total divide ratio is divide by five.

4. An improved pulse swallow frequency divider for use in a fractional division phase locked loop, as claimed in claim 1, wherein:

the swallow counter comprises a pulse generator, a B counter, an SR latch and a DFF trigger; the pulse generator outputs a shaped pulse signal, then inputs the pulse signal into the B counter and the SR latch, the B counter outputs a Bout signal to the SR latch, the SR latch outputs an SR _ Q signal, and the signal finally outputs an MC signal through the DFF trigger;

the pulse generator includes: the delay circuit comprises a PMOS (P-channel metal oxide semiconductor) tube, an NMOS (N-channel metal oxide semiconductor) tube, a three-input NAND gate and 7 NOT gate delay units; after the input signal passes through the PMOS tube, the voltage passes through the NAND gate, the voltage is conducted by using the NAND gate to control the voltage signal, and when the voltage signal passes through the NAND gate, the voltage signal passes through the NOT gate delay unit D1 and then is output;

the B counter includes: the two counting units are input into an input port c of the other counting unit through an output port q of one counting unit;

the SR latch includes: two-input NOR gates, the outputs of which are connected with each other, the inputs of which are connected to Bout and pulse respectively, and the output of which is connected to SR _ Q.

5. An improved pulse swallow frequency divider for use in a fractional division phase locked loop, as claimed in claim 1, wherein: the pulse generator module is used for reshaping the LOAD signal and generating a narrow pulse signal to set the B counter; the output port of the pulse generator is inserted between the delay unit D1 and the delay unit D2, and the input pulse signal only passes through the NAND gate and the delay unit D1, so that the response time of the pulse generator is reduced.

6. An improved pulse swallow frequency divider for use in a fractional division phase locked loop as claimed in claim 4, wherein: when the frequency divider works at the highest frequency, the pulse width is not more than one-fourth period of the PSO signal, and the pulse too wide can cause wrong frequency dividing ratio and reduce the working speed of the frequency divider; too narrow a pulse may cause the SR latch to malfunction, requiring the width of the pulse signal to be adjusted to a suitable range.

7. An improved pulse swallowing frequency dividing method for a fractional-n PLL, comprising: the method comprises the following steps:

step 1, after an input signal CLK is subjected to frequency pre-division by 4/5, a clock signal PSO is output and is respectively input into a counter A, a counter B, a trigger DFF1 and a trigger DFF 2; in the 4/5 prescaler, when MC is 0, the synchronous logic unit divides the input signal by two, and then the total frequency division ratio is 4 through an asynchronous frequency division circuit; when MC is 1, the output signal is fed back to the input end, the synchronous logic unit is changed into three-frequency division, and the total frequency division ratio is 5;

step 2, a PSO signal is input into the counter A and then outputs an Aout signal, then the trigger DFF1 outputs a LOAD signal after being triggered by a clock signal PSO, the signal is divided into three parts, one part is fed back to the counter A for reloading the value of the counter A, the count value of the counter A is reset to zero, one part is input into the pulser, and the last part is taken as an output signal;

step 3, after the LOAD signal is input into the pulser, shaping the LOAD signal by the pulser to change the input LOAD signal into a narrow pulse signal; one part of the signal is input into the counter B, and the other part of the signal is input into the SR latch; the counter B outputs a Bout signal under the triggering of the pulse signal and the PSO clock signal; then the SR latch is triggered by the pulse signal and the Bout signal and outputs an SR _ Q signal; the SR _ Q signal is input to a flip-flop DFF2, which outputs a control signal MC, which is used to control 4/5 the prescaler to divide the CLK input signal by either 4 or 5, starting from the clock signal PSO.

Technical Field

The invention relates to an improved pulse swallowing frequency divider and a frequency dividing method for a fractional frequency division phase-locked loop.

Background

In recent years, the design of fractional-n frequency synthesizers has become a popular research field, and they are widely used in devices requiring high-precision frequency sources, such as Global Navigation Satellite System (GNSS) radio receivers, high-precision base stations, and mobile radio transceiver chips. The frequency divider is an important component of a fractional-n frequency synthesizer, and has higher performance requirements, so that it is very necessary to design a fractional frequency divider with higher operating speed and lower power consumption. The operating speed of the pulse swallow frequency divider is limited by the delay time of the mode control signal, and in order to improve the operating speed, the first method is to reduce the size of the delay time by re-timing the mode control signal through a D trigger, however, since the setting and resetting of the mode control signal are triggered by different signals, the structure has an inherent frequency dividing ratio offset. The second category of approaches solves this problem by a single signal triggering the mode control signal, with the attendant problems of possible SR latch failure, increased delay time, etc. The third category of approaches avoids the problems in the second category of approaches by eliminating the SR latch, but increases the complexity and power consumption of the circuit.

Disclosure of Invention

In order to solve the problems in the existing method and obtain a pulse swallowing frequency divider with fast work and low power consumption, the invention provides an improved pulse swallowing frequency divider used in a fractional division phase-locked loop, which is characterized in that: comprises an 4/5 prescaler, a pulse counter and a swallow counter; the 4/5 prescaler, the pulse counter and the swallow counter are sequentially connected to form a closed loop, and the pulse counter and the swallow counter are synchronously arranged through a shaped narrow pulse signal.

In the above-mentioned improved pulse swallow frequency divider for fractional division phase-locked loop, the 4/5 prescaler comprises three D flip-flops, DFF0, DFF1 and DFF 2; an input signal CLK is input into DDF0, an output signal qb of the input signal is connected with a d port of DFF1, a clock signal is input into a c port of DFF1, an output port q of DFF1 is connected with a clock port c of DFF2, and finally, the three DFFs are connected through a three-input NAND gate; the three DFFs adopt true single-phase clock structures to reduce power consumption, each D trigger has the same structure and comprises 5 PMOS (P-channel metal oxide semiconductor) tubes and 6 NMOS (N-channel metal oxide semiconductor) tubes which are connected, wherein an input clock signal CLK (clock) is connected to one PMOS tube and one output NMOS tube, an input signal is controlled through a D0 port, and an output signal is output through a qb port; when MC is 0, the input D1 of DFF0 is set to high level, representing a divide-by-two D flip-flop; input d1 of DFF0 is qb in case MC is 1₁And q is₂Controlling; when qb₁1 and q₂When 1, the output of DFF0 remains high for two clock cycles.

In one of the above improved pulse swallow frequency dividers for fractional division phase locked loops, the 4/5 prescaler has a mixed mode of synchronous logic and asynchronous logic, including when MC is 0, the synchronous logic unit divides the input signal by two, and then divides the input signal by four through an asynchronous divide-by-two circuit; when MC is 1, the output signal is fed back to the input, and the synchronous logic unit will become divide by three, and the total divide ratio is divide by five.

In an improved pulse swallow frequency divider for use in a fractional division phase locked loop as described above,

the swallow counter comprises a pulse generator, a B counter, an SR latch and a DFF trigger; the pulse generator outputs a shaped pulse signal, then inputs the pulse signal into the B counter and the SR latch, the B counter outputs a Bout signal to the SR latch, the SR latch outputs an SR _ Q signal, and the signal finally outputs an MC signal through the DFF trigger;

the pulse generator includes: the delay circuit comprises a PMOS (P-channel metal oxide semiconductor) tube, an NMOS (N-channel metal oxide semiconductor) tube, a three-input NAND gate and 7 NOT gate delay units; after the input signal passes through the PMOS tube, the voltage passes through the NAND gate, the voltage is conducted by using the NAND gate to control the voltage signal, and when the voltage signal passes through the NAND gate, the voltage signal passes through the NOT gate delay unit D1 and then is output;

the B counter includes: the two counting units are input into an input port c of the other counting unit through an output port q of one counting unit;

the SR latch includes: two-input NOR gates, the outputs of which are connected with each other, the inputs of which are connected to Bout and pulse respectively, and the output of which is connected to SR _ Q.

In an improved pulse swallow frequency divider for use in a fractional division phase locked loop as described above, the pulse generator module is adapted to reshape the LOAD signal and generate a narrow pulse signal to set the B counter; the output port of the pulse generator is inserted between the delay unit D1 and the delay unit D2, and the input pulse signal only passes through the NAND gate and the delay unit D1, so that the response time of the pulse generator is reduced.

In the improved pulse swallowing frequency divider used in the fractional-N phase-locked loop, when the frequency divider works at the highest frequency, the pulse width is not greater than one-fourth period of the PSO signal, and the pulse width is too wide, which can cause wrong frequency dividing ratio and reduce the working speed of the frequency divider; too narrow a pulse may cause the SR latch to malfunction, requiring the width of the pulse signal to be adjusted to a suitable range.

An improved pulse swallowing frequency dividing method for a fractional-n PLL, comprising: the method comprises the following steps:

step 1, after an input signal CLK is subjected to frequency pre-division by 4/5, a clock signal PSO is output and is respectively input into a counter A, a counter B, a trigger DFF1 and a trigger DFF 2; in the 4/5 prescaler, when MC is 0, the synchronous logic unit divides the input signal by two, and then the total frequency division ratio is 4 through an asynchronous frequency division circuit; when MC is 1, the output signal is fed back to the input end, the synchronous logic unit is changed into three-frequency division, and the total frequency division ratio is 5;

step 2, a PSO signal is input into the counter A and then outputs an Aout signal, then the trigger DFF1 outputs a LOAD signal after being triggered by a clock signal PSO, the signal is divided into three parts, one part is fed back to the counter A for reloading the value of the counter A, the count value of the counter A is reset to zero, one part is input into the pulser, and the last part is taken as an output signal;

step 3, after the LOAD signal is input into the pulser, shaping the LOAD signal by the pulser to change the input LOAD signal into a narrow pulse signal; one part of the signal is input into the counter B, and the other part of the signal is input into the SR latch; the counter B outputs a Bout signal under the triggering of the pulse signal and the PSO clock signal; then the SR latch is triggered by the pulse signal and the Bout signal and outputs an SR _ Q signal; the SR _ Q signal is input to a flip-flop DFF2, which outputs a control signal MC, which is used to control 4/5 the prescaler to divide the CLK input signal by either 4 or 5, starting from the clock signal PSO.

Compared with the prior art, the improved pulse swallow frequency divider for the fractional frequency division phase-locked loop is designed, the problems of SR latch failure, wrong frequency division ratio and the like in the prior art are solved, the MC delay time is very low, the maximum input frequency can reach 7.04GHz, and meanwhile, the DFF of a frequency division circuit structure and a TSPC structure is benefited, so that the power consumption of the improved pulse swallow frequency divider is lower, and the improved pulse swallow frequency divider is very suitable for application scenes of high frequency and low power consumption.

Drawings

Fig. 1 is a structural schematic diagram of an improved pulse swallowing frequency divider.

Fig. 2 is a timing diagram of an improved pulse swallow frequency divider.

Fig. 3(a) is a block diagram of the 4/5 prescaler architecture.

Fig. 3(b) is a state diagram of the 4/5 prescaler (when MC is 0).

Fig. 3(c) is a state diagram of the 4/5 prescaler (when MC is 1).

Fig. 4 is a schematic diagram of a proposed swallowing counter.

Fig. 5 is a schematic diagram of a pulse generator.

Figure 6 is a micrograph of a fractional division phase locked loop chip based on an improved pulse swallow frequency divider.

Fig. 7 is a simulation result of the pulse swallow frequency divider.

FIG. 8 is a graph of test and simulation power consumption versus input frequency.

Detailed Description

Fig. 1 and fig. 2 are a structure and a timing diagram of an improved pulse swallow frequency divider, which comprises an 4/5 prescaler, a programmable counter (a) and a swallow counter (B), and the synchronous setting function of the pulse counter and the swallow counter is realized through a LOAD (LOAD) signal. If the falling edge of the LOAD (LOAD) arrives later than the rising edge of the PSO, as shown in process (r) in fig. 2, it will cause the B counter to count incorrectly. To solve this problem, the present invention contemplates a pulse generator inserted between DFF1 and the B counter to reshape the LOAD (LOAD) to generate a pulse signal. As can be seen from the red-circle portion in fig. 2, the falling edge of the pulse signal comes earlier than the rising edge of the PSO.

The GNSS receiver is manufactured by adopting a 0.18 mu mCMOS process and applied to the GNSS receiver. The active area of the phase-locked loop is 0.64mm²The area of the pulse swallowing frequency division circuit is 0.054mm 2. At the process cornerAnd at a temperature of 27 ℃, the device can work at a frequency of 7.04 GHz. At a minimum input frequency of 0.5GHz, the power consumption for the test and simulation was 0.72mW and 0.51mW, respectively. The power consumption for the test and simulation was 7.59mW and 6.53mW at the maximum operating frequency of 7.04 GHz.

In the conventional architecture, the falling edge of Aout may arrive earlier than Bout, resulting in an erroneous division ratio of the divider. And the traditional structure is improved in the improved pulse swallowing frequency divider. First, the pulse signal resets the Bout signal and a time interval Δ t is generated between the pulse signal and the falling edge of the Bout signal, as shown in blue process (c) of fig. 2. It ensures that the falling edge of the pulse always arrives later than Bout. Second, the setting and resetting of MC is triggered by a single Bout signal, as shown in processes (c) and (c) of fig. 2. Thus, the total frequency-division ratio is PA + B. This offset-free architecture greatly simplifies the interface logic between the sigma-delta modulator and the pulse swallow counter in a fractional-N phase-locked loop. Thirdly, the structure adopts a new MC scheme of a D trigger, as shown in FIG. 2, the timing sequence margin of the MC is increased, the delay time is greatly reduced, and the working speed of the frequency divider is greatly improved. This feature is superior to previous retiming structures.

Fig. 3 has 3 diagrams in common, in which (a) is a structural block diagram of 4/5 prescaler, and (b) and (c) are a state diagram when MC is 0 and a state diagram when MC is 1 in this order. The 4/5 prescaler in this design has a hybrid mode of synchronous logic and asynchronous logic. When MC is 0, the synchronous logic unit divides the input signal by two, and then through an asynchronous divide-by-two circuit, a total division ratio of 4 is obtained. When MC is 1, the output signal is fed back to the input, and the synchronous logic unit will become divide by three, with a total division ratio of 5.

4/5 the prescaler comprises 3 DFFs (D flip-flops) DFF0, DFF1 and DFF 2. These DFF implementations use a True Single Phase Clock (TSPC) architecture to reduce power consumption. The output of the DFF is defined as qb₀,q₁And q is₂The divider state is defined as: "qb₀q₁q₂", the next state is by qb₀ ⁺＝qb₀’,q₁ ⁺＝qb₀And q is₂ ⁺＝qb₂*q₁+q₂*q₁' to calculate. When MC is 0, the input d1 of DFF0 is set high, representing a two-frequency-division DFF, as shown in fig. 3 (a). Output signal PSO q₂', is q₂The opposite phase of (c). As shown in fig. 3(b), the hatched state represents a state where PSO is 1. Input d1 of DFF0 is qb in case MC is 1₁And q is₂And (5) controlling. When qb₁1 and q_2＝1The output of DFF0 remains high for two clock cycles. As shown in the state diagram of fig. 3(c), the state transitions to one cycle five times. The 4/5 frequency divider can operate at an input clock frequency of up to 7.04 GHz.

Fig. 4 is a schematic diagram of a swallow counter according to the present invention, which is composed of a pulse generator, a B counter, an SR latch and a DFF. The pulse generator module is used to reshape the LOAD signal and generate a narrow pulse signal to set the B counter. If the pulse width is too wide, the falling edge of the pulse signal may arrive later than the rising edge of the PSO signal, which may result in an erroneous division ratio and reduce the operating speed of the divider. Therefore, when the divider is operating at the highest frequency, the pulse width cannot be greater than one-quarter of the period of the PSO signal. On the other hand, if the pulse width is too narrow, it may cause the falling edge of the pulse signal to arrive earlier than the Bout signal, resulting in SR latch failure. Therefore, it is necessary to adjust the width of the pulse signal to a suitable range.

Fig. 5 is a schematic diagram of a pulse generator, and in order to reduce the pulse response time, the present invention inserts the output port of the pulse between delay cells D1 and D2, as shown in fig. 6. In this circuit the pulse signal only passes through NAND and D1, significantly reducing the response time of the pulse generator.

FIG. 6 is a micrograph of a fractional-N PLL chip based on an improved pulse swallow frequency divider, which is fabricated using a 0.18 μm CMOS process and used in a GNSS receiver. Wherein the active area of the phase-locked loop is 0.64mm²While the circuit area of the pulse swallowing frequency divider is only 0.054mm²。

Fig. 7 is a simulation of a pulsed swallow divider that can operate at 7.04GHz at a fast process corner at a temperature of 27 c, with neither failure of the SR latch nor an unwanted divide ratio observed in the simulation.

Fig. 8 is a graph of power consumption versus input frequency measured and simulated at a division ratio of 59. The power consumption of the measurement and simulation results was 0.72mW and 0.51mW, respectively, at a minimum input frequency of 0.5 GHz. In general, as the input frequency increases, the power consumption also increases. In the present structure, however, the power consumption of the measurement result and the simulation result was only 7.59mW and 6.53mW even if the input frequency was as high as 7.04 GHz.

TABLE 1 Performance parameters

Table 1 shows the performance parameters of the present invention. MC delay tau of proposed structure_MCVery low, only 120ps, maximum input frequency f_in；maxCan reach 7.04 GHz. Furthermore, with the benefit of the frequency divider circuit configuration and the TSPC configuration DFF, the power consumption is also very low, only 7.59 mW. In conclusion, the invention is very suitable for application scenes with high frequency and low power consumption.