阅读说明：本技术 一种峰值保护电路 (Peak protection circuit ) 是由 仝兴孚 于 2021-01-22 设计创作，主要内容包括：本发明公开了一种峰值保护电路,包括控制单元和逆变单元,还包括采样检测单元和定时启动单元,所述控制单元上设置有输入端、输出端和参考电压端,所述采样检测单元和定时启动单元均与输入端电连接,所述输出端与逆变单元电连接,所述逆变单元与采样检测单元电连接,所述输出端还与定时启动单元电连接,所述定时启动单元与参考电压端电连接,能对逆变电路的过流和瞬间的高峰值进行检测,超过设定的基准电压后,可以有效停止逆变输出,对电路进行保护,而且具有定时自启功能,具有安全高效的有益效果。(The invention discloses a peak protection circuit, which comprises a control unit, an inversion unit, a sampling detection unit and a timing start unit, wherein the control unit is provided with an input end, an output end and a reference voltage end, the sampling detection unit and the timing start unit are both electrically connected with the input end, the output end is electrically connected with the inversion unit, the inversion unit is electrically connected with the sampling detection unit, the output end is also electrically connected with the timing start unit, the timing start unit is electrically connected with the reference voltage end, can detect the overcurrent and instantaneous high peak value of the inversion circuit, can effectively stop inversion output after the set reference voltage is exceeded, protects the circuit, has a timing self-start function, and has the advantages of safety and high efficiency.)

1. A peak protection circuit comprising a control unit (21) and an inverter unit (20), characterized in that: still include sampling detection unit (17) and timing start unit (18), be provided with input (19), output (22) and reference voltage end (16) on control unit (21), wherein, sampling detection unit (17) and timing start unit (18) all are connected with input (19) electricity, output (22) are connected with contravariant unit (20) electricity, contravariant unit (20) are connected with sampling detection unit (17) electricity, output (22) still are connected with timing start unit (18) electricity, timing start unit (18) are connected with reference voltage end (16) electricity.

2. The peak protection circuit of claim 1, wherein: input (19) are including reverse input end (1) and syntropy input end (2), reverse input end (1) is connected with sampling detecting element (17) electricity, sampling detecting element (17) are including sampling resistor (R0), detecting diode (D23), first current-limiting resistor (R64), integrating capacitor (C52) and integrating resistor (R63), inverter unit (20) are connected with power ground through sampling resistor (R0), inverter unit (20) still are connected with detecting diode (D23), detecting diode (D23) are connected with reverse input end (1) electricity through first current-limiting resistor (R64), integrating capacitor (C52) and integrating resistor (R63).

3. The peak protection circuit of claim 2, wherein: the output end (22) comprises a PWM output end (24) and a compensation output end (9), wherein the PWM output end (24) is electrically connected with the inverter unit (20), the compensation output end (9) is electrically connected with the timing starting unit (18), the timing starting unit (18) comprises a timing capacitor (C51), a first voltage-dividing resistor (R61) and a second voltage-dividing resistor (R62), wherein one end of the first voltage-dividing resistor (R61) is electrically connected with one end of the timing capacitor (C51), one end of the timing capacitor (C51) is electrically connected with the equidirectional input end (2), the other end of the timing capacitor (C51) is electrically connected with the compensation output end (9), one end of the first voltage-dividing resistor (R61) is also electrically connected with the reference voltage end (16) through the second voltage-dividing resistor (R62), and the other end of the first voltage-dividing resistor (R61) is electrically connected with the ground.

4. The peak protection circuit of claim 3, wherein: the PWM output end (24) comprises a first PWM output end (14) and a second PWM output end (11), the inverter unit (20) comprises an upper bridge inverter unit (15) and a lower bridge inverter unit (26), the first PWM output end (14) is electrically connected with the upper bridge inverter unit (15), and the second PWM output end (11) is electrically connected with the lower bridge inverter unit (26).

5. The peak protection circuit of claim 4, wherein: the upper bridge inverter unit (25) and the lower bridge inverter unit (26) respectively comprise an inverter circuit (37), a bootstrap circuit (33) and an inverter circuit, wherein the inverter circuit (37) is electrically connected with the inverter circuit through the bootstrap circuit (33), and the inverter circuit (37) are electrically connected with the PWM output end (24).

6. The peak protection circuit of claim 5, wherein: the inverter circuit (37) comprises an inverter triode (41), a second current-limiting resistor (42), a third current-limiting resistor (43) and a fourth current-limiting resistor (40), wherein the base of the inverter triode (41) is electrically connected with the PWM output end (24) through the second current-limiting resistor (42), the base of the inverter triode (41) is also electrically connected with the emitter of the inverter triode (41) through the third current-limiting resistor (43), the emitter of the inverter triode (41) is electrically connected with a power supply, a first power supply (38) and a backflow prevention diode (39) are arranged on the collector of the inverter triode (41), and the first power supply (38) is electrically connected with the collector of the inverter triode (41) through the backflow prevention diode (39) and the fourth current-limiting resistor (40).

7. The peak protection circuit of claim 6, wherein: the bootstrap circuit (33) comprises a bootstrap capacitor (35) and a voltage stabilizing diode (34), the inverter bridge circuit comprises a driving MOS tube (48), a conversion MOS tube (31), an accelerating diode (46), a fifth current limiting resistor (45), a sixth current limiting resistor (44), a seventh current limiting resistor (36), a first biasing resistor (47), a second biasing resistor (32), a decoupling capacitor (29) and an output anti-backflow diode (28), wherein one end of the bootstrap capacitor (35) is electrically connected with the anti-backflow diode (39), the other end of the bootstrap capacitor (35) is electrically connected with the anode of the output anti-backflow diode (28), the anode of the output anti-backflow diode (28) is electrically connected with the source electrode of the conversion MOS tube (31), and the source electrode of the conversion MOS tube (31) is electrically connected with the gate of the conversion MOS tube (31) through the voltage stabilizing diode (34) and the second biasing resistor (32), the cathode of the voltage stabilizing diode (34) is connected with the grid of the conversion MOS tube (31), the grid of the conversion MOS tube (31) is electrically connected with the collector of the phase inversion triode (41) through a seventh current limiting resistor (36), a second power supply (30) is arranged on the drain of the conversion MOS tube (31), the second power supply (30) is connected with the decoupling capacitor (29) in a bypass mode, and the second power supply (30) and the decoupling capacitor (30) are both connected with the drain of the conversion MOS tube (31).

8. The peak protection circuit of claim 7, wherein: the cathode of the output anti-backflow diode (28) is connected with the drain of the driving MOS tube (48), the drain of the driving MOS tube (48) is electrically connected with the output end (27) of the inverter unit, the source of the driving MOS tube (48) is electrically connected with the sampling resistor (R0) and the detection diode (D23) respectively, the source of the driving MOS tube (48) is connected with the gate of the driving MOS tube (48) through a first bias resistor (47), and the gate of the driving MOS tube (48) is electrically connected with the PWM output end (24) through an accelerating diode (46), a fifth current-limiting resistor (45) and a sixth current-limiting resistor (44).

9. The peak protection circuit of claim 8, wherein: the control unit (21) is further provided with a power input end, a control end and a soft start end (8), the soft start end (8) is provided with a soft start circuit (23), the soft start circuit (23) comprises a discharge triode (Q11), a third voltage dividing resistor (RR), a fourth voltage dividing Resistor (RA), an eighth current limiting resistor (R45) and a second timing capacitor (C18), one end of the fourth voltage dividing Resistor (RA) is electrically connected with a reference voltage end (16), the other end of the fourth voltage dividing Resistor (RA) is electrically connected with an emitter of the discharge triode (Q11) through the third voltage dividing resistor (RR) and a second timing capacitor (C18), an emitter of the discharge triode (Q11) is connected with the ground, a third voltage dividing resistor (RR) and a second timing capacitor (C18) are further connected in parallel between the emitter and a collector of the discharge triode (Q11), and the collector of the discharge triode (Q11) is electrically connected with the soft start end (8), the base electrode of the discharge triode (Q11) is electrically connected with the source electrode of the driving MOS tube (48) through an eighth current limiting resistor (R45).

10. The peak protection circuit of claim 9, wherein: the power input end comprises a high-level end (15), a ground end (12) and a PWM power supply end (13), the high-level end (15) and the PWM power supply end (13) are both electrically connected with a first power supply (38), the ground end (12) is electrically connected with the ground, a filter capacitor (C110) is arranged between the high-level end (15) and the ground end (12), the high-level end (15) is electrically connected with the ground end (12) through the filter capacitor (C110), the control end comprises a synchronization end (3), an oscillator output end (4), an oscillation capacitor access end (5), an oscillation resistor access end (6), a discharge end (7) and a locking control end (10), wherein the synchronization end (3) and the oscillator output end (4) are in a suspension state, a third timing capacitor (C17) is arranged on the oscillation capacitor access end (5), and a timing resistor (R50) is arranged on the oscillation resistor access end (6), the discharging end (7) is provided with a discharging resistor (R51), the oscillating capacitor access end (5) is connected with the ground through a third timing capacitor (C17), the oscillating resistor access end (6) is connected with the ground through a timing resistor (R50), the discharging end (7) is connected with the ground through a discharging resistor (R51) and a third timing capacitor (C17), and the locking control end is connected with the ground.

Technical Field

The invention belongs to the technical field of electronic equipment, and particularly relates to a peak protection circuit.

Background

The inverter is a converter which converts direct current electric energy into constant frequency, constant voltage or frequency and voltage regulation alternating current. The existing inverter is composed of an inverter bridge, control logic and a filter circuit, the output end of the inverter bridge is connected with a load end, working voltage is provided for the load, if the load connected into the inverter bridge has a fault or has a short circuit, the inverter bridge can be abnormal, the output can be cut off after the existing inverter bridge protection circuit has the fault, but after the fault is eliminated, the inverter cannot be started automatically, the working efficiency is lower, in addition, the phenomenon that the peak voltage of the output end of the inverter is too large can occur at a certain time point in the working process of the inverter, the large peak voltage can also cause the inverter bridge to work abnormally, and the peak detection protection is lacked in the existing inverter.

Disclosure of Invention

To solve the above technical problem, the present invention provides a peak protection circuit.

The specific scheme of the invention is as follows:

the utility model provides a peak value protection circuit, includes the control unit and the contravariant unit, still includes sampling detection unit and timing start unit, last input, output and the reference voltage end of being provided with of control unit, wherein, sampling detection unit and timing start unit all are connected with the input electricity, the output is connected with the contravariant unit electricity, the contravariant unit is connected with the sampling detection unit electricity, the output still is connected with timing start unit electricity, timing start unit and reference voltage end electricity are connected.

The input includes reverse input and syntropy input, the reverse input is connected with the sampling detection unit electricity, the sampling detection unit includes sampling resistor R0, detecting diode D23, first current-limiting resistor R64, integral capacitor C52 and integrating resistor R63, the inverter unit passes through sampling resistor R0 and is connected with power ground, the inverter unit still is connected with detecting diode D23, detecting diode D23 is connected with the reverse input electricity through first current-limiting resistor R64, integrating capacitor C52 and integrating resistor R63.

The output end comprises a PWM output end and a compensation output end, wherein the PWM output end is electrically connected with the inverter unit, the compensation output end is electrically connected with the timing starting unit, the timing starting unit comprises a timing capacitor C51, a first voltage-dividing resistor R61 and a second voltage-dividing resistor R62, wherein one end of the first voltage-dividing resistor R61 is electrically connected with one end of the timing capacitor C51, one end of the timing capacitor C51 is electrically connected with the equidirectional input end, the other end of the timing capacitor C51 is electrically connected with the compensation output end, one end of the first voltage-dividing resistor R61 is also electrically connected with the reference voltage end 16 through the second voltage-dividing resistor R62, and the other end of the first voltage-dividing resistor R61 is electrically connected with the ground.

The PWM output end comprises a first PWM output end and a second PWM output end, the inverter unit comprises an upper bridge inverter unit and a lower bridge inverter unit, the first PWM output end is electrically connected with the upper bridge inverter unit, and the second PWM output end is electrically connected with the lower bridge inverter unit.

The upper bridge inverter unit and the lower bridge inverter unit respectively comprise an inverter circuit, a bootstrap circuit and an inverter circuit, wherein the inverter circuit is electrically connected with the inverter circuit through the bootstrap circuit, and the inverter circuit are electrically connected with the PWM output end.

The inverter circuit comprises an inverter triode, a second current-limiting resistor, a third current-limiting resistor and a fourth current-limiting resistor, wherein the base of the inverter triode is electrically connected with the PWM output end through the second current-limiting resistor, the base of the inverter triode is also electrically connected with the emitter of the inverter triode through the third current-limiting resistor, the emitter of the inverter triode is electrically connected with a power supply, a first power supply and a backflow prevention diode are arranged on the collector of the inverter triode, and the first power supply is electrically connected with the collector of the inverter triode through the backflow prevention diode and the fourth current-limiting resistor.

The bootstrap circuit comprises a bootstrap capacitor and a voltage stabilizing diode, the inverter bridge circuit comprises a driving MOS tube, a conversion MOS tube, an accelerating diode, a fifth current limiting resistor, a sixth current limiting resistor, a seventh current limiting resistor, a first biasing resistor, a second biasing resistor, a decoupling capacitor and an output anti-backflow diode, wherein one end of the bootstrap capacitor is electrically connected with the anti-backflow diode, the other end of the bootstrap capacitor is electrically connected with the anode of the output anti-backflow diode, the anode of the output anti-backflow diode is electrically connected with the source electrode of the conversion MOS tube, the source electrode of the conversion MOS tube is electrically connected with the grid electrode of the conversion MOS tube through the voltage stabilizing diode and the second biasing resistor, the cathode of the voltage stabilizing diode is connected with the grid electrode of the conversion MOS tube, the grid electrode of the conversion MOS tube is electrically connected with the collector electrode of the phase inversion triode through the seventh current limiting resistor, and the drain electrode of the conversion MOS, the second power supply is connected with a decoupling capacitor bypass, and both the second power supply and the decoupling capacitor are connected with the drain electrode of the conversion MOS tube.

The negative pole of output anti-return diode is connected with the drain electrode of drive MOS pipe, the drain electrode of drive MOS pipe is connected with inverter unit's output electricity, the source electrode of drive MOS pipe with respectively with sampling resistor R0 and detection diode D23 electricity be connected, the source electrode on the drive MOS pipe is connected with the grid on the drive MOS pipe through first biasing resistance, the grid on the drive MOS pipe through accelerating diode, fifth current-limiting resistance and sixth current-limiting resistance with the PWM output electricity is connected.

The control unit is also provided with a power input end, a control end and a soft start end, the soft start end is provided with a soft start circuit, the soft start circuit comprises a discharge triode Q11, a third voltage-dividing resistor RR, a fourth voltage-dividing resistor RA, an eighth current-limiting resistor R45 and a second timing capacitor C18, one end of the fourth voltage-dividing resistor RA is electrically connected with a reference voltage end, the other end of the fourth voltage-dividing resistor RA is electrically connected with an emitting electrode of a discharge triode Q11 through a third voltage-dividing resistor RR and a second timing capacitor C18, the emitting electrode of the discharge triode Q11 is connected with the ground, a third voltage-dividing resistor RR and a second timing capacitor C18 are further connected in parallel between the emitting electrode and the collecting electrode of the discharge triode Q11, the collector of the discharge triode Q11 is electrically connected with the soft start end, and the base of the discharge triode Q11 is electrically connected with the source of the drive MOS tube through an eighth current limiting resistor R45.

The power input end comprises a high-level end, a ground end and a PWM power supply end, the high-level end and the PWM power supply end are both electrically connected with a first power supply, the ground end is electrically connected with the ground, a filter capacitor C110 is arranged between the high-level end and the ground end, the high-level end is electrically connected with the ground end through the filter capacitor C110, the control end comprises a synchronization end, an oscillator output end, an oscillation capacitor access end, an oscillation resistor access end, a discharge end and a locking control end, wherein the synchronization end and the oscillator output end are in a suspended state, the oscillation capacitor access end is provided with a third timing capacitor C17, the oscillation resistor access end is provided with a timing resistor R50, the discharge end is provided with a discharge resistor R51, the oscillation capacitor access end is connected with the ground through the third timing capacitor C17, and the oscillation resistor access end is connected with the ground through the timing resistor R50, the discharge end is connected with the ground through a discharge resistor R51 and a third timing capacitor C17, and the locking control end is connected with the ground.

The invention discloses a peak value protection circuit, which collects the value of current passing through an MOS tube in an inverter unit through a sampling resistor, the sampling resistor converts the current value into a sampling voltage value, a control unit controls the output of PWM waveform through the value of the sampling voltage value so as to control the operation or stop of the inverter unit, a reference voltage is arranged on the control unit, the sampling voltage is compared with the reference voltage, if the sampling voltage exceeds the reference voltage value, the control unit stops the output of the PWM waveform so as to stop the inverter unit, thus when the current flowing through the MOS tube in the inverter unit is too large, the MOS tube can stop operating, the MOS tube is effectively protected, and the safety of the circuit is improved; moreover, the detection diode, the integral capacitor and the integral resistor are matched to extract a voltage peak value on the output end of the inversion unit, if the voltage peak value exceeds a reference voltage value, the control unit stops PWM output, so that the inversion unit stops working, the damage to equipment caused by overhigh peak voltage at the moment of electrifying is prevented, and the safety is further improved;

in addition, the circuit is also provided with a timing starting unit, the control unit stops outputting PWM waves due to high peak value or large current, the voltage at two ends of a timing capacitor in the timing starting unit can be charged by a timing capacitor through reference voltage in the control unit, when the timing capacitor is charged to meet the starting voltage, the circuit starts inverting output from the start, and meanwhile, a soft starting circuit on the control unit can accelerate the start of the circuit, so that the circuit has the advantages of improving the safety performance of the circuit and improving the working efficiency.

Drawings

Fig. 1 is a block diagram of the overall architecture of the present invention.

Fig. 2 is a schematic circuit configuration diagram of the control unit, the sampling detection unit, and the timing start unit.

Fig. 3 is a schematic circuit diagram of the inverter unit.

Fig. 4 is a schematic circuit diagram of the upper bridge inverter unit and the lower bridge inverter unit.

Fig. 5 is a schematic diagram of the general structure of the peak protection circuit.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It is understood that the described embodiments are merely some implementations, rather than all implementations, and that all other embodiments that can be derived by one of ordinary skill in the art based on the described embodiments are intended to be within the scope of the present invention.

As shown in fig. 1, a peak protection circuit includes a control unit 21 and an inverter unit 20, and further includes a sampling detection unit 17 and a timing start unit 18, where the control unit 21 is provided with an input end 19, an output end 22 and a reference voltage end 16, where the sampling detection unit 17 and the timing start unit 18 are both electrically connected to the input end 19, the output end 22 is electrically connected to the inverter unit 20, the inverter unit 20 is electrically connected to the sampling detection unit 17, the output end 22 is further electrically connected to the timing start unit 18, and the timing start unit 18 is electrically connected to the reference voltage end 16. In the present embodiment, the control unit 21 is an IC chip, and the IC chip is preferably SG 3525.

As shown in fig. 2, the input terminal 19 includes an inverting input terminal 1 and a non-inverting input terminal 2, the inverting input terminal 1 is electrically connected to the sampling detection unit 17, the sampling detection unit 17 includes a sampling resistor R0, a detector diode D23, a first current limiting resistor R64, an integrating capacitor C52 and an integrating resistor R63, the inverter unit 20 is connected to the ground via a sampling resistor R0, the inverter unit 20 is further connected to a detector diode D23, and the detector diode D23 is electrically connected to the inverting input terminal 1 via a first current limiting resistor R64, an integrating capacitor C52 and an integrating resistor R63.

In this embodiment, the resistance of the sampling resistor R0 is preferably 0.1 ohm, and the sampling resistor is a non-inductive resistor and has the characteristics of low resistance and high precision. The sampling resistor R0 can collect the magnitude of the current flowing through the MOS transistor in the inverter unit 20.

The detection diode D23 performs half-wave rectification on the ac signal output by the inverter unit 20, the half-wave rectified signal charges the integrating capacitor C52 to maintain the peak value of the rectified pulsating dc signal, so as to obtain a relatively smooth dc signal, the amplitude of the smooth dc signal at this time is the peak value of the ac signal output by the inverter unit 20 instantaneously, and the peak value is input to the value control unit 21.

The output end 22 includes a PWM output end 24 and a compensation output end 9, wherein the PWM output end 24 is electrically connected to the inverter unit 20, the compensation output end 9 is electrically connected to the timing start unit 18, the timing start unit 18 includes a timing capacitor C51, a first voltage-dividing resistor R61 and a second voltage-dividing resistor R62, wherein one end of the first voltage-dividing resistor R61 is electrically connected to one end of the timing capacitor C51, one end of the timing capacitor C51 is electrically connected to the equidirectional input end 2, the other end of the timing capacitor C51 is electrically connected to the compensation output end 9, one end of the first voltage-dividing resistor R61 is also electrically connected to the reference voltage end 16 through the second voltage-dividing resistor R62, and the other end of the first voltage-dividing resistor R61 is electrically connected to ground.

As shown in fig. 2 to 3, the PWM output terminal 24 includes a first PWM output terminal 14 and a second PWM output terminal 11, and the inverter unit 20 includes an upper bridge inverter unit 25 and a lower bridge inverter unit 26, wherein the first PWM output terminal 14 is electrically connected to the upper bridge inverter unit 25, and the second PWM output terminal 11 is electrically connected to the lower bridge inverter unit 26. Since the phases of the PWM waveforms output by the first PWM output terminal 14 and the second PWM output terminal 11 are different by 180 degrees, the upper bridge inverter unit 25 and the lower bridge inverter unit 26 can alternately operate under the driving of the first PWM output terminal 14 and the second PWM output terminal 11.

In this embodiment, the voltage at the reference voltage terminal 16 is preferably 5V, the voltage at the 5V is divided by the first voltage dividing resistor R61 and the second voltage dividing resistor R62, the voltage across the divided first voltage dividing resistor R61 is 1.1V, since one end of the first voltage dividing resistor R61 is connected to the unidirectional input terminal 2 of the control unit, and the other end of the first voltage dividing resistor R61 is connected to the ground, the voltage at the unidirectional input terminal 2 is also 1.1V, the control unit 21 includes a comparator, the inverting input terminal 1 and the unidirectional input terminal 2 are two input terminals of the comparator, the voltage at the unidirectional input terminal 2 is 1.1V, the 1.1V is a reference voltage in the control unit 21, and if the input voltage at the inverting input terminal 1 exceeds 1.1V, the control unit 21 stops the PWM output and the compensation output.

In a normal operating state, the compensation output terminal 9 outputs 5V voltage, and since one end of the timing capacitor C51 is electrically connected to the equidirectional input terminal 2, the other end of the timing capacitor C51 is electrically connected to the compensation output terminal 9, and the voltage at the equidirectional input terminal 2 is 1.1V, a voltage difference between two ends of the timing capacitor C51 is 3.9V in the normal operating state.

If the input voltage value at the inverting input terminal 1 exceeds the reference voltage value at the non-inverting input terminal 2, that is, exceeds 1.1V, the control unit 21 stops outputting the PWM wave, at this time, the inverter unit 20 stops operating due to lack of PWM driving, and at the same time, the output voltage at the compensation output terminal 9 is also reduced from 5V to 0V, and since the voltage across the capacitor does not suddenly change, when the voltage at the compensation output terminal 9 changes from 5V to 0V, the voltage at the non-inverting input terminal 2 changes from 1.1V to-3.9V, so that the voltage across the timing capacitor C51 is still 3.9V.

At the moment when the voltage at the equidirectional input end 2 becomes-3.9V, the reference voltage end 16 starts to charge the timing capacitor C51 through the second voltage-dividing resistor R62, so that the voltage at the equidirectional input single end 2 gradually rises to the reference voltage value, namely 1.1V, at this time, the timing capacitor C51 is in a charged state, so that the voltage at the equidirectional input end 2 is boosted to 1.1V from-3.9V, and the time instant control unit 21 is started again at the timing time from-3.9V to 1.1V.

After the control unit is started again, the compensation output end 9 of the control unit 21 outputs a voltage value of 5V again, the PWM output end outputs PWM waves to the inverter unit 20, the sampling resistor R0 samples the current in the inverter unit 20, the detection diode D23, the first current limiting resistor R64, the integrating capacitor C52 and the integrating resistor R63 extract peak values, and extract the peak values to the reverse input end 1, the control unit 21 compares the voltage value at the reverse input end 1 with the voltage value at the equidirectional input end 2 again, if the voltage value at the reverse input end 1 is still greater than the reference voltage value, it indicates that there is a short circuit or a fault with an excessive peak value in the inverter unit 20, the control unit 21 stops the PWM output and the voltage output at the compensation output end 9 again, at this time, the timing capacitor C51 enters the timing charging state again, until the voltage value at the reverse input end 1 is less than the reference voltage value at the equidirectional input end 1.1V after the control unit 21 is started, the control unit normally outputs the PWM wave and compensates the 5V voltage at the output end 9, so that the inverter unit 20 normally works, the control unit 21 comprises a comparator and a PWM generator, when the voltage at the reverse input end 1 is higher than the voltage value at the equidirectional input end 2, the comparator outputs a low level signal, so that the PWM generator does not output the PWM wave any more, if the voltage at the reverse input end 1 is lower than the voltage at the equidirectional input end 2, the comparator outputs a high level signal, and the PWM wave is normally output.

As shown in fig. 3 to 4, each of the upper bridge inverter unit 25 and the lower bridge inverter unit 26 includes an inverter circuit 37, a bootstrap circuit 33, and an inverter circuit, wherein the inverter circuit 37 is electrically connected to the inverter circuit through the bootstrap circuit 33, and the inverter circuit 37 are electrically connected to the PWM output terminal 24.

Because the upper bridge inverter unit 25 is connected to the first PWM output terminal 14, the lower bridge inverter unit 26 is connected to the second PWM output terminal 11, and the phases of the PWM waveforms output from the first PWM output terminal 14 and the second PWM output terminal 11 are different by 180 degrees, the upper bridge inverter unit 25 and the lower bridge inverter unit 26 can alternately operate.

Specifically, as shown in fig. 3, if the PWM wave output from the first PWM output terminal 14 turns on the driving MOS transistor Q5 in the upper bridge inverter unit 25, the PWM wave output from the second PWM output terminal 11 turns off the driving MOS transistor Q6 in the lower bridge inverter unit 26, and due to the inverter circuit, the gate voltage of the switching MOS transistor Q7 in the upper bridge inverter unit 25 is turned off at a low level, the gate voltage of the switching MOS transistor Q8 in the lower bridge inverter unit 26 is turned on at a high level, after the switching, the voltage at the drain D of the switching MOS transistor Q8 in the lower bridge inverter unit 26 is transmitted to the output terminal 27 of the inverter unit through the source S of the switching MOS transistor Q8, and the driving MOS transistor Q5 in the upper bridge inverter unit 25 is turned on, so that the drain D1 in the driving MOS transistor Q5 is turned on with the source S1 of the driving MOS transistor, and thus the output terminal 27 of the inverter unit connected with the drain D1 in the driving transistor Q5 in fig. 3 is at a low level, the output 27 of the inverter unit connected to the source S of the switching MOS transistor Q8 is at a high level.

If the PWM wave output from the first PWM output terminal 14 turns off the driving MOS transistor Q5 in the upper bridge inverter unit 25, the PWM wave output from the second PWM output terminal 11 turns on the driving MOS transistor Q6 in the lower bridge inverter unit 26, and due to the inverter circuit, the conversion MOS transistor Q7 in the upper bridge inverter unit is turned on, the conversion MOS transistor Q8 in the lower bridge inverter unit is turned off, and at this time, the conversion MOS transistor Q7 in the upper bridge inverter unit and the driving MOS transistor Q6 in the lower bridge inverter unit are matched to invert the level signals at both ends of the output terminal 27 of the inverter unit.

Thus, as the PWM waves at the first PWM output terminal 14 and the second PWM output terminal 11 are continuously output, the output 27 of the inverter unit outputs an alternating voltage signal, which has the same amplitude as the voltage value of V4 connected to the drain of the switching MOS transistor.

As shown in fig. 4, the inverter circuit 37 includes an inverter transistor 41, a second current limiting resistor 42, a third current limiting resistor 43, and a fourth current limiting resistor 40, wherein a base of the inverter transistor 41 is connected to the first PWM output terminal 14 or the second PWM output terminal 11 through the second current limiting resistor 42, the base of the inverter transistor 41 is further electrically connected to an emitter of the inverter transistor 41 through the third current limiting resistor 43, the emitter of the inverter transistor 41 is electrically connected to a power ground, a first power supply 38 and a backflow prevention diode 39 are disposed on a collector of the inverter transistor 41, the first power supply 38 is electrically connected to a collector of the inverter transistor 41 through the backflow prevention diode 39 and the fourth current limiting resistor 40, and the base of the inverter transistor is connected to the emitter such that a phase of the collector output terminal of the inverter transistor is inverted by 180 degrees compared to the base.

The bootstrap circuit 33 includes a bootstrap capacitor 35 and a zener diode 34, the inverter bridge circuit includes a driving MOS transistor 48, a converting MOS transistor 31, an accelerating diode 46, a fifth current limiting resistor 45, a sixth current limiting resistor 44, a seventh current limiting resistor 36, a first biasing resistor 47, a second biasing resistor 32, a decoupling capacitor 29, and an output anti-backflow diode 28, wherein one end of the bootstrap capacitor 35 is electrically connected to the anti-backflow diode 39, the other end of the bootstrap capacitor 35 is electrically connected to an anode of the output anti-backflow diode 28, an anode of the output anti-backflow diode 28 is electrically connected to a source of the converting MOS transistor 31, a source of the converting MOS transistor 31 is electrically connected to a gate of the converting MOS transistor 31 through the zener diode 34 and the second biasing resistor 32, a cathode of the zener diode 34 is connected to the gate of the converting MOS transistor 31, a gate of the converting MOS transistor 31 is electrically connected to a collector of the inverting triode 41 through the seventh current limiting resistor 36, a second power supply 30 is arranged on the drain electrode of the conversion MOS tube 31, the second power supply 30 is connected with a decoupling capacitor 29 in a bypass mode, the second power supply 30 and the decoupling capacitor 30 are both connected with the drain electrode of the conversion MOS tube 31, and the decoupling capacitor 30 can remove noise interference in the second power supply. The zener diode 34 plays a role of voltage stabilization protection between the gate and the source of the switching MOS transistor 31, and protects the PN junction of the switching MOS transistor 31 from breakdown.

The inverter circuit 37 inverts the waveform signal at the collector output terminal of the inverter transistor 41, so that only one MOS transistor in the inverter circuit is turned on, specifically, if there is a PWM wave output to the inverter unit, the PWM wave is divided into two paths for transmission, as shown in fig. 4, one path of the PWM wave passes through the driving MOS transistor 48, so that the driving MOS transistor 48 becomes a conducting state, and the other path of the PWM wave passes through the second current limiting resistor 42 and is transmitted to the base of the inverter transistor 41, and since the base of the inverter transistor 41 and the emitter of the inverter transistor are in a connected state, the phase of the collector output signal at the inverter transistor 41 is inverted 180 degrees, the PWM signal of the 180 degrees is inverted, and the switching MOS transistor 31 in fig. 4 cannot be turned on due to the inversion of the level signal.

Moreover, since the first power supply 38 charges the bootstrap capacitor 35 through the anti-reflux diode 39 when the driving MOS transistor 48 is turned on and the inverter transistor 41 is turned on, at the next time of the PWM signal, the driving MOS transistor 48 and the inverter transistor 41 are both turned off, at this time, the accumulated charging voltage across the bootstrap capacitor 35 causes the switching MOS transistor 31 to be turned on through the fourth current-limiting resistor 40 and the seventh current-limiting resistor 36, and the voltage at the drain of the switching MOS transistor 31 flows to the output terminal 27 of the inverter unit through the source of the switching MOS transistor 31 and the output anti-reflux diode 28, thereby completing the primary conversion of the voltage signal.

The cathode of the output anti-backflow diode 28 is connected to the drain of the driving MOS tube 48, the drain of the driving MOS tube 48 is electrically connected to the output 27 of the inverter unit, the source of the driving MOS tube 48 is electrically connected to the sampling resistor R0 and the detection diode D23, the source of the driving MOS tube 48 is connected to the gate of the driving MOS tube 48 through the first bias resistor 47, and the gate of the driving MOS tube 48 is electrically connected to the PWM output 24 through the acceleration diode 46, the fifth current-limiting resistor 45 and the sixth current-limiting resistor 44. The accelerating diode 46 can make the driving MOS transistor 48 have the technical effects of fast turn-off and slow turn-on, so as to protect the driving MOS transistor and reduce the risk of short circuit.

As shown in fig. 2, the control unit 21 is further provided with a power input terminal, a control terminal and a soft start terminal 8, the soft start terminal 8 is provided with a soft start circuit 23, the soft start circuit 23 comprises a discharge triode Q11, a third voltage dividing resistor RR, a fourth voltage dividing resistor RA, an eighth current limiting resistor R45 and a second timing capacitor C18, one end of the fourth voltage-dividing resistor RA is electrically connected with the reference voltage end 16, the other end of the fourth voltage-dividing resistor RA is electrically connected with the emitting electrode of the discharge triode Q11 through the third voltage-dividing resistor RR and the second timing capacitor C18, the emitting electrode of the discharge triode Q11 is connected with the ground, the third voltage-dividing resistor RR and the second timing capacitor C18 are further connected in parallel between the emitting electrode and the collecting electrode of the discharge triode Q11, the collector of the discharge triode Q11 is electrically connected to the soft start terminal 8, and the base of the discharge triode Q11 is electrically connected to the source of the driving MOS transistor 48 through an eighth current limiting resistor R45.

The soft start terminal 8 can accelerate the start of the control unit 21, the constant current source is disposed in the control unit 21 and can charge the second timing capacitor C18, and when the second timing capacitor C18 is charged to a predetermined voltage value, the control unit 21 can start to operate, but in this embodiment, the second timing capacitor C18 can also charge the second timing capacitor C18 through the reference voltage terminal 16 and the fourth voltage-dividing resistor RA, so as to accelerate the charging time of the second timing capacitor C18, that is, shorten the start time of the control unit 21, and improve the operating effect.

If an overcurrent occurs in the inverter unit 20, the base electrode voltage of the discharging triode Q11 is increased, so that the discharging triode Q11 is turned on, at this time, the second timing capacitor C18 starts to discharge through the collector and emitter of the discharging triode Q11, and when the second timing capacitor C18 discharges to a certain state, the control unit 21 also stops working, thereby further protecting the circuit.

The power input end comprises a high-level end 15, a ground end 12 and a PWM power supply end 13, the high-level end 15 and the PWM power supply end 13 are both electrically connected with a first power supply 38, the ground end 12 is electrically connected with ground, a filter capacitor C110 is arranged between the high-level end 15 and the ground end 12, the high-level end 15 is electrically connected with the ground end 12 through the filter capacitor C110, the control end comprises a synchronization end 3, an oscillator output end 4, an oscillation capacitor access end 5, an oscillation resistor access end 6, a discharge end 7 and a locking control end 10, wherein the synchronization end 3 and the oscillator output end 4 are in a suspended state, the oscillation capacitor access end 5 is provided with a third timing capacitor C17, the oscillation resistor access end 6 is provided with a timing resistor R50, the discharge end 7 is provided with a discharge resistor R51, and the oscillation capacitor access end 5 is electrically connected with ground through a third timing capacitor C17, the oscillating resistor access terminal 6 is connected with the ground through a timing resistor R50, the discharging terminal 7 is connected with the ground through a discharging resistor R51 and a third timing capacitor C17, and the locking control terminal is connected with the ground. The high-level end 15, the ground end 12 and the PWM power supply end 13 provide proper voltage values for normal operation of the control unit, the locking control end is connected to ground to ensure normal start of the control unit 21, and the synchronization end 3, the oscillator output end 4, the oscillating capacitor access end 5, the oscillating resistor access end 6 and the discharge end provide clock references for PWM waves output by the control unit 21.

Fig. 5 shows an overall circuit configuration of the peak protection circuit.

The specific working process of the peak protection circuit is as follows:

during normal work, control unit 21 outputs two opposite-phase PWM signals, two opposite-phase PWM signals alternately switch on upper bridge inverter unit 25 and lower bridge inverter unit 26, upper bridge inverter unit 25 drives MOS pipe Q5 to switch on, conversion MOS pipe Q8 among lower bridge inverter unit 26 switches on, and with V4 voltage to the one end of transmitting to inverter unit output 27, when the PWM signal arrives at next moment, drive MOS pipe Q6 among lower bridge inverter unit 26 switches on conversion MOS pipe Q7 among upper bridge inverter unit 25 to switch on, conversion MOS pipe Q7 transmits V4 voltage to the other end of inverter unit output 27. The PWM signal varies periodically, so that the phase of the voltage signal at the output 27 of the inverter unit also varies alternately, and an alternating voltage is output.

If the current at the output end 27 of the inverter unit is too large, the source voltage of the driving MOS transistor Q6 or the source voltage of the driving MOS transistor Q6 is connected to the sampling detection unit 17 and the soft start circuit 23, the sampling detection unit 17 converts the current signal into a voltage signal and inputs the voltage signal into the control unit 21 for comparison, if the voltage signal exceeds the reference voltage, the control unit 26 stops outputting the PWM wave and the compensation output, and the soft start circuit 23 simultaneously discharges the second timing capacitor C18, which accelerates the speed of stopping outputting the PWM wave and the compensation wave by the control unit, after the control unit 26 does not output the PWM wave, the inverter unit 20 stops the inverter operation, effectively protecting the circuit and the compensation output 9 stops outputting, the timing start unit 18 starts charging the timing capacitor C51, so that the control unit 21 starts outputting again, while the reference voltage terminal 16 also charges the second timing capacitor C18, speeding up the start-up time of the control unit 26.

The invention can detect the overcurrent and instantaneous high peak value of the inverter circuit, can effectively stop inverter output after the set reference voltage is exceeded, protects the circuit, has the timing self-starting function and has the advantages of safety and high efficiency.

The technical means disclosed in the invention scheme are not limited to the technical means disclosed in the above embodiments, but also include the technical scheme formed by any combination of the above technical features. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and such improvements and modifications are also considered to be within the scope of the present invention.