阅读说明：本技术 基于片上系统的数据交换方法 (Data exchange method based on system on chip ) 是由 曹平 黄锡汝 张可立 李超 郑佳俊 袁建辉 岳琼申 于 2021-07-01 设计创作，主要内容包括：本发明公开了一种基于片上系统的数据交换方法,该方法包括：接收到系统处理器发送的数据写入信号后,获取先进先出存储器的状态；在所述先进先出存储器的状态为空时,获取目标存储地址中预设数量的待写入数据,以将所述待写入数据缓存至所述先进先出存储器；将所述先进先出存储器缓存的所述待写入数据以字节流的方式输出至可编程逻辑端,通过一种软硬件数据交互接口,解决了现有技术中多模块挂载同一条总线的访问要抢占片上互连总线导致数据传输效率下降的问题,通过消耗少量的物理地址空间资源和充分利用了片上互连总线的传输带宽,提高了数据的传输效率。(The invention discloses a data exchange method based on a system on chip, which comprises the following steps: after receiving a data writing signal sent by a system processor, acquiring the state of a first-in first-out memory; when the state of the first-in first-out memory is empty, acquiring a preset number of data to be written in a target memory address so as to cache the data to be written in the first-in first-out memory; the data to be written cached by the first-in first-out memory is output to a programmable logic terminal in a byte stream mode, through a software and hardware data interaction interface, the problem that in the prior art, the data transmission efficiency is reduced because a plurality of modules mount the same bus and access of the same bus needs to preempt an on-chip interconnection bus is solved, and the data transmission efficiency is improved by consuming a small amount of physical address space resources and fully utilizing the transmission bandwidth of the on-chip interconnection bus.)

1. A data exchange method based on a system on a chip is characterized in that the data exchange method comprises the following steps:

after receiving a data writing signal sent by a system processor, acquiring the state of a first-in first-out memory;

when the state of the first-in first-out memory is empty, acquiring a preset number of data to be written in a target memory address so as to cache the data to be written in the first-in first-out memory;

and outputting the data to be written cached by the first-in first-out memory to a programmable logic terminal in a byte stream mode.

2. The system-on-chip based data exchange method of claim 1, wherein the step of obtaining the status of the fifo memory upon receiving the data write signal from the system processor comprises:

acquiring the number of writing bytes from the writing operation;

determining whether the writing byte number is less than or equal to the maximum cache byte number of a first-in first-out memory;

and when the number of the written bytes is less than or equal to the maximum number of the cache bytes, acquiring the state of the first-in first-out memory after receiving a data writing signal sent by a system processor.

3. The data exchange method based on the system on chip as claimed in claim 2, wherein the step of obtaining a predetermined amount of data to be written in a target storage address to cache the data to be written in the fifo when the status of the fifo is empty comprises:

and when the state of the first-in first-out memory is empty, acquiring a preset number of data to be written in a target memory address in an interruption mode so as to cache the data to be written in the first-in first-out memory.

4. The system-on-chip based data exchange method as claimed in claim 2, wherein the step of obtaining a predetermined amount of data to be written in the target memory address to buffer the data to be written to the fifo comprises:

determining the number of writing times according to the number of writing bytes and the data bit width of the on-chip interconnection bus;

and circularly executing to-be-written data with the byte quantity in the target storage address being the bit width of the on-chip interconnection bus data according to the writing times to be written into a data writing register, so as to cache the to-be-written data in the data writing register to a first-in first-out memory until a preset quantity of the to-be-written data is obtained.

5. The system-on-chip based data exchange method according to claim 1, wherein the step of outputting the data to be written in the fifo buffer to a programmable logic terminal in a byte stream comprises:

determining a data byte splitting state in a data splitting state machine;

splitting data to be written in the first-in first-out memory into byte stream data based on the data byte splitting state and the on-chip interconnection bus data bit width;

and inputting the split byte stream data into a programmable logic terminal in sequence.

6. A data exchange method based on a system on a chip is characterized in that the data exchange method comprises the following steps:

after receiving a data reading signal sent by a system processor, acquiring the state of a first-in first-out memory;

splicing byte stream data of a programmable logic terminal based on-chip interconnection bus data bit width to obtain data to be read, and caching the spliced data to be read into a first-in first-out memory;

and when the state of the first-in first-out memory is a readable state, sending a preset amount of data to be read from the first-in first-out memory to a target memory address.

7. The system-on-chip based data exchange method of claim 6, wherein the step of obtaining the status of the fifo memory upon receiving the data read signal from the system processor comprises:

acquiring the number of read bytes from the read operation;

determining whether the number of bytes read is less than or equal to the maximum number of cache bytes of a first-in first-out memory;

and when the number of the reading bytes is smaller than or equal to the maximum number of the cache bytes, acquiring the state of the first-in first-out memory after receiving a data reading signal sent by a system processor.

8. The system-on-chip based data exchange method according to claim 6, wherein the step of splicing byte stream data of the programmable logic terminal based on the on-chip interconnection bus data bit width to obtain data to be read, so as to cache the spliced data to be read into the first-in-first-out memory comprises:

determining a data byte splicing state in a data splicing state machine;

splicing byte stream data input by a programmable logic terminal based on the data byte splicing state and the on-chip interconnection bus data bit width to obtain data to be read;

and sequentially inputting the spliced data to be read into the first-in first-out memory.

9. The system-on-chip based data exchange method of claim 6, wherein the step of sending a predetermined amount of data to be read from the fifo to a target memory address when the state of the fifo is a readable state comprises:

and sending a preset amount of data to be read from the first-in first-out memory to a target memory address in an interruption mode when the state of the first-in first-out memory is a readable state.

10. The system-on-chip based data exchange method of claim 6, wherein the step of sending a predetermined amount of data to be read from the fifo to a target memory address when the state of the fifo is a readable state comprises:

when the state of the first-in first-out memory is a readable state, determining the effective byte number of the data to be read in the first-in first-out memory;

determining the number of reading times according to the effective byte number of the data to be read and the data bit width of the on-chip interconnection bus;

and outputting the data to be read from a first-in first-out memory to a data reading register according to the read times in a circulating mode, and sending the data to be read in the data reading register to a target storage address until a preset number of data to be read are sent.

Technical Field

The invention relates to the technical field of data communication, in particular to a data exchange method based on a system on chip.

Background

With the progress of microelectronic technology and the diversification of application requirements, systems on chip with Programmable Logic have been developed at a high speed, and various relatively mature methods for exchanging data between a microprocessor (CPU) and a Programmable Logic Device (Programmable Logic terminal) of the systems on chip have appeared, wherein the existing data exchange method is to exchange data between the CPU and the Programmable Logic terminal through an on-chip interconnection bus (such as an AXI bus) and a RAM memory inside the Programmable Logic terminal, and the method accesses the RAM memory to realize data exchange based on a large continuous physical address space, and cannot provide more data exchange channels to adapt to more application occasions under the condition of the same address space resources; and a plurality of functional modules in the programmable logic terminal are directly mounted on the same on-chip interconnection bus between the CPU and the programmable logic terminal to realize data exchange between the CPU and each functional module, and the on-chip interconnection bus is seized among the functional modules to influence the data transmission efficiency.

Disclosure of Invention

The embodiment of the application provides a data exchange method based on a system on a chip, and aims to solve the problem that the efficiency of data transmission is reduced because a plurality of modules mount the same bus and access to the same bus occupies an interconnection bus on the chip

The embodiment of the application provides a data exchange method based on a system on chip, and in one embodiment, the data exchange method based on the system on chip comprises the following steps:

after receiving a data writing signal sent by a system processor, acquiring the state of a first-in first-out memory;

when the state of the first-in first-out memory is empty, acquiring a preset number of data to be written in a target memory address so as to cache the data to be written in the first-in first-out memory;

and outputting the data to be written cached by the first-in first-out memory to a programmable logic terminal in a byte stream mode.

In an embodiment, the step of acquiring the status of the fifo memory after receiving the data write signal sent by the system processor comprises:

acquiring the number of writing bytes from the writing operation;

determining whether the writing byte number is less than or equal to the maximum cache byte number of a first-in first-out memory;

and when the number of the written bytes is less than or equal to the maximum number of the cache bytes, acquiring the state of the first-in first-out memory after receiving a data writing signal sent by a system processor.

In an embodiment, the step of obtaining a preset number of data to be written in a target storage address when the fifo is empty to cache the data to be written in the fifo includes:

and when the state of the first-in first-out memory is empty, acquiring a preset number of data to be written in a target memory address in an interruption mode so as to cache the data to be written in the first-in first-out memory.

In an embodiment, the step of obtaining a preset number of data to be written in a target storage address and caching the data to be written in the fifo comprises:

determining the number of writing times according to the number of writing bytes and the data bit width of the on-chip interconnection bus;

and according to the write times, circularly executing to obtain data to be written, the number of bytes in a target storage address of which is the bit width of the on-chip interconnection bus data, so as to write the data to be written into a data writing register, and caching the data to be written in the data writing register to a first-in first-out memory until a preset number of data to be written is obtained.

In an embodiment, the step of outputting the data to be written in the fifo buffer to a programmable logic terminal in a byte stream manner includes:

determining a data byte splitting state in a data splitting state machine;

splitting data to be written in the first-in first-out memory into byte stream data based on the data byte splitting state and the on-chip interconnection bus data bit width;

and inputting the split byte stream data into a programmable logic terminal in sequence.

In one embodiment, the data exchange method includes:

after receiving a data reading signal sent by a system processor, acquiring the state of a first-in first-out memory;

splicing byte stream data of a programmable logic terminal based on-chip interconnection bus data bit width to obtain data to be read, and caching the spliced data to be read into a first-in first-out memory;

and when the state of the first-in first-out memory is a readable state, sending a preset amount of data to be read from the first-in first-out memory to a target memory address.

In one embodiment, the step of acquiring the status of the fifo memory after receiving the data read signal sent by the system processor comprises:

acquiring the number of read bytes from the read operation;

determining whether the number of bytes read is less than or equal to the maximum number of cache bytes of a first-in first-out memory;

and when the number of the reading bytes is smaller than or equal to the maximum number of the cache bytes, acquiring the state of the first-in first-out memory after receiving a data reading signal sent by a system processor.

In an embodiment, the step of splicing the byte stream data of the programmable logic terminal based on the on-chip interconnection bus data bit width to obtain the data to be read, and caching the spliced data to be read into the first-in first-out memory includes:

determining a data byte splicing state in a data splicing state machine;

splicing byte stream data input by a programmable logic terminal based on the data byte splicing state and the on-chip interconnection bus data bit width to obtain data to be read;

and sequentially inputting the spliced data to be read into the first-in first-out memory.

In one embodiment, the step of sending a predetermined amount of data to be read from the fifo to a target memory address when the state of the fifo is a readable state includes:

and when the state of the first-in first-out memory is a readable state, sending a preset amount of data to be read from the first-in first-out memory to a target memory address in an interruption mode.

In one embodiment, the step of sending a predetermined amount of data to be read from the fifo to a target memory address in an interrupt manner when the state of the fifo is a readable state includes:

when the state of the first-in first-out memory is a readable state, determining the effective byte number of the data to be read in the first-in first-out memory;

determining the number of reading times according to the effective byte number of the data to be read and the data bit width of the on-chip interconnection bus;

and outputting the data to be read from a first-in first-out memory to a data reading register according to the read times in a circulating mode, and sending the data to be read in the data reading register to a target storage address until a preset number of data to be read are sent.

The technical scheme of the data exchange method based on the system on chip provided by the embodiment of the application at least has the following technical effects or advantages:

the state of the first-in first-out memory is obtained after the data writing signal sent by the system processor is received; when the state of the first-in first-out memory is empty, acquiring a preset number of data to be written in a target memory address so as to cache the data to be written in the first-in first-out memory; and outputting the data to be written cached by the first-in first-out memory to a programmable logic terminal in a byte stream mode. After receiving a data reading signal sent by a system processor, acquiring the state of a first-in first-out memory; splicing byte stream data of a programmable logic terminal based on-chip interconnection bus data bit width to obtain data to be read, and caching the spliced data to be read into a first-in first-out memory; when the state of the first-in first-out memory is a readable state, a preset amount of data to be read is sent to a target memory address from the first-in first-out memory, the problem that the data transmission efficiency is reduced because a plurality of modules mount the same bus and access to the same bus needs to preempt an on-chip interconnection bus is solved, and the data transmission efficiency is improved by consuming a small amount of physical address space resources and fully utilizing the transmission bandwidth of the on-chip interconnection bus.

Drawings

FIG. 1 is a schematic diagram of a hardware operating environment according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of the data write function according to the present invention;

FIG. 3 is a schematic diagram of the data reading function of the present invention;

FIG. 4 is a flowchart illustrating a first embodiment of a method for exchanging data based on a system on a chip according to the present invention;

FIG. 5 is a flowchart illustrating a second embodiment of a data exchange method based on a system on a chip according to the present invention;

FIG. 6 is a flowchart illustrating a fourth embodiment of a data exchange method based on a system on a chip according to the present invention;

FIG. 7 is a flowchart illustrating a fifth embodiment of a data exchange method based on a system on a chip according to the present invention;

FIG. 8 is a flowchart illustrating a sixth embodiment of a method for exchanging data based on a system on a chip according to the present invention;

FIG. 9 is a flowchart illustrating a seventh embodiment of a system-on-chip based data exchange method according to the present invention;

FIG. 10 is a flowchart illustrating an eighth embodiment of a system-on-chip based data exchange method according to the present invention;

FIG. 11 is a flowchart illustrating a tenth exemplary embodiment of a data exchange method based on a system on a chip;

Detailed Description

For a better understanding of the above technical solutions, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

As shown in fig. 1, fig. 1 is a schematic structural diagram of a hardware operating environment according to an embodiment of the present invention.

It should be noted that, the present application is developed based on a system on chip, which integrates a microprocessor (Central Processing Unit, CPU), a Programmable Logic Device (PLD), an analog IP core, a digital IP core, etc. on a single chip, so that the system on chip has both flexible and efficient data operation and transaction Processing capabilities of the CPU and high-speed parallel Processing advantages of the PLD, and has an on-chip interconnection structure connecting the CPU end and the PLD end inside the system on chip with Programmable Logic, when in use, a general Logic resource on the PLD end can be configured and mapped to one or more peripheral devices with specific functions at the CPU end, the on-chip interconnection structure is generally an on-chip interconnection bus (including an address bus, a data bus, and a control bus) designed by a manufacturer, such as an advanced eXtensible interface bus, and in the chip, the CPU end allocates a segment of address space for the on-chip interconnection bus, data interaction with the PLD terminal can be carried out by accessing the register mode.

Specifically, fig. 1 contains 3 parts: a transmission logic interface of a programmable logic end (PLD end), a transmission logic drive of a system processor (CPU end) and an on-chip interconnection structure between the two. The on-chip interconnection structure comprises 1 on-chip interconnection structure bus, 1 read interrupt line and 1 write interrupt line. The programmable logic terminal is connected with the system processor through the on-chip interconnection structure bus and the interrupt-write line so as to write data to be written of a target storage address of the system processor into the programmable logic terminal, and the programmable logic terminal is connected with the system processor through the on-chip interconnection bus and the interrupt-read line so as to send the data to be read of the programmable logic terminal to the target storage address of the system processor.

The transmission logic interface comprises 2 functional modules: the device comprises a data writing module and a data reading module.

As shown in fig. 2, fig. 2 is a detailed structural design block diagram of a data write-in module, where the data write-in module implements an interface function of converting a data block written by a CPU end to a user logic in a programmable logic end into a byte data stream, where interface signals of the data write-in module and the CPU are 1 on-chip interconnect fabric bus with a data bit width of 32 bits and 1 write interrupt line wrirq; interface signals which are logically interconnected with a programmable logic terminal user are an 8-bit data signal data, a 1-bit data valid signal valid and a 1-bit receiving ready signal ready; the data writing module comprises 10 functional modules: the data writing method comprises a writing starting register, a writing length register, a writing data register, a writing interruption generation function, a FIFO empty detection state machine, a cache FIFO (first-in first-out memory), transmission quantity calculation, reading control, a data splitting state machine and data splitting, wherein the first-in first-out memory is used for caching data to be written from a CPU end to a user logic in a programmable logic end.

As shown in fig. 3, fig. 3 is a detailed structural diagram of a data reading module, and the data reading module implements an interface function of converting byte data stream of a programmable logic terminal into data block that can be read by a CPU terminal. The interface signals of the data reading module and the CPU end are 1 on-chip interconnection structure bus with 32-bit data bit width and 1 rdirq; the interface signals which are logically interconnected with the programmable logic terminal user are an 8-bit data signal data, a 1-bit data valid signal valid, a 1-bit data ready signal ready and a 1-bit data read request signal rdreq; the data reading module comprises 10 functional modules: the system comprises a read starting register, a read length register, a read data register, a read interrupt generation, an overtime monitoring state machine, a cache FIFO, a read length calculation, a read request control, a data splicing state machine and data splicing, wherein the first-in first-out memory is used for caching data to be read, which is read by a CPU end from user logic in a programmable logic end.

The transmission logic driver at the CPU end comprises 4 file operation functions: the device comprises xxx _ open (), xxx _ release (), xxx _ read (), xxx _ write (), wherein a xxx _ open function realizes the opening function of the device, a xxx _ release function realizes the closing function of the device, a xxx _ read function realizes the reading data function from the programmable logic terminal, and a xxx _ write function realizes the writing data function to the programmable logic terminal.

Those skilled in the art will appreciate that the system-on-chip architecture shown in fig. 2 or 3 is not meant to be limiting of the system-on-chip and may include more or fewer components than shown, or some components may be combined, or a different arrangement of components.

In addition, the present invention provides an embodiment of a data exchange method based on a system on chip, and it should be noted that although a logic sequence is shown in the flowchart, in some cases, the steps shown or described may be executed in a sequence different from that of the flowchart, and the data exchange method based on the system on chip is applied to the system on chip.

As shown in fig. 4, in a first embodiment of the present application, the method for exchanging data based on a system on chip of the present application includes the following steps:

step S110, after receiving a data writing signal sent by a system processor, acquiring the state of a first-in first-out memory;

step S120, when the state of the first-in first-out memory is empty, acquiring a preset number of data to be written in a target memory address so as to cache the data to be written in the first-in first-out memory;

step S130, outputting the data to be written buffered by the fifo to a programmable logic terminal in a byte stream manner.

In this embodiment, in order to solve the problem in the prior art that the access of multiple modules mounted on the same bus occupies the on-chip interconnection bus to reduce the data transmission efficiency, the present application provides a full-duplex data transmission channel constructed based on an on-chip interconnection structure, so as to achieve efficient and reliable bidirectional data transmission between a CPU and a PLD, specifically, two buffer FIFOs, i.e., first-in first-out memories, are added to the transmission logic interface, a system processor stores data to be written in a target storage address into one of the first-in first-out memories or stores data to be read in the other first-in first-out memory into the target storage address, a user logic in the PLD receives the data to be written in or sends the data to be read from the first-in first-out memories, so as to achieve batch data transmission of a single read/write operation, and make the time taken for reading/writing valid data occupy most of the total time taken by the read/write operation, high transmission efficiency and high transmission rate are achieved.

In this embodiment, the system processor is a processor on the CPU side, and the target storage address is a storage address allocated from a user space of an operating system. The operating system divides the virtual memory space into two parts, one part is a kernel space and the other part is a user space. The kernel space can execute the bottom layer I/O read-write operation, the user space cannot execute the bottom layer I/O read-write operation, the process running in the user space needs to access the kernel of the operating system through system call, and then the I/O read-write operation on the bottom layer hardware can be indirectly completed, therefore, the data read-write operation between the user space and the bottom layer hardware needs to be participated in the kernel space, the data transmission between the user space and the bottom layer hardware is completed, and the data read-write operation on the bottom layer hardware needs to be performed in the kernel space in the process of performing the data read-write operation on the bottom layer hardware.

In this embodiment, after receiving a data write signal sent by a kernel space of a system processor, a write start register writes data to be written into a programmable logic terminal, specifically, first, a write start register module is started, where the write start register module is used to detect in real time whether an address of an on-chip interconnect structure bus matches with the write start register and a write control signal of the bus is valid, if yes, a write start flag signal (start _ flag) is generated according to data of a current on-chip interconnect structure bus, and the write start register is used for a driver to initiate write transmission; then, acquiring the state of the first-in first-out memory, and informing a system processor to send a preset amount of data to be written from a kernel space in an interrupt mode when the state of the first-in first-out memory is empty; then, starting a write length register module, where the write length register is used to register the number of written bytes of the data to be written of the target storage address, specifically, the write length register module is used to detect in real time whether the address of the on-chip interconnection structure bus matches the write length register and the write control signal of the bus is valid, if yes, storing the data of the current on-chip interconnection structure bus in a write length register (wr _ length _ reg) and generating a write length flag signal (wr _ length _ flag), where the write length register is used to drive a program to initiate one-time write transmission of the number of bytes of the actually written data; and finally, starting a data writing register module, and storing the data to be written of the target storage address into a first-in first-out memory, specifically, the data writing register module is used for detecting whether the address of the on-chip interconnection structure bus is matched with the data writing register and a writing control signal of the bus is valid in real time, if so, storing the data of the current on-chip interconnection structure bus in the data writing register (wr _ data _ reg), and immediately inputting the data registered in the data writing register into the first-in first-out memory until a preset amount of the data to be written is stored. And simultaneously, outputting the data to be written cached by the first-in first-out memory to a programmable logic terminal in a byte stream mode in real time, and simultaneously inputting the data to be written into the first-in first-out memory and reading the data to be written out from the first-in first-out memory.

In this embodiment, as shown in fig. 2, the fifo is a fifo data buffer, and there is no external read/write address line, data is written in and read out sequentially, the fifo is used to buffer data for write-once transmission, and the data bit width of the write-in end and the read-out end of the fifo is the same as the data bit width of the on-chip interconnect fabric bus, and the buffer depth is set as required, for example, the buffer depth can be set to 1024, and the buffer depth determines the maximum number of bytes for write-once transmission (buffer depth data bit width/8), the number of bytes written in the fifo is equal to the number of bytes read from the fifo at one time, and before writing the data to be written in the fifo, the status of the fifo is ensured to be empty, that is, the fifo can buffer all the data to be written for write-once transmission, and data loss due to fifo write overflow does not occur.

In this embodiment, a FIFO empty detection state machine module is used to detect whether the FIFO empty memory is empty, and at the initial time, this module is in an idle state, and when a write start flag signal (start _ flag) is valid, this module is triggered to jump to a detection state; in the detection state, the module detects whether an empty flag signal (rdempty) of the first-in first-out memory is true, if so, the first-in first-out memory is empty, and the FIFO memory jumps back to the idle state; when the FIFO empty detection state machine module is in a detection state and detects that the empty flag signal (rdempty) of the FIFO memory is true, a write-in interrupt signal (wrirq) is generated to indicate that data is ready to be received, and a new round of system processors are started to write the data to be written in the kernel space into the preset FIFO memory.

According to the technical scheme, after a data writing signal sent by a system processor is received, the state of a first-in first-out memory is obtained, and when the state of the first-in first-out memory is empty, a preset number of data to be written in a target memory address is obtained, so that the data to be written in is cached to the first-in first-out memory; the technical means of outputting the data to be written cached in the first-in first-out memory to a programmable logic terminal in a byte stream mode solves the problem that the data transmission efficiency is reduced because a plurality of modules mount the same bus and access the same bus occupies an on-chip interconnection bus, and improves the data transmission efficiency.

As shown in fig. 5, steps S210 to S230 in the second embodiment of the present application are located before step S110 in the first embodiment, and the second embodiment includes the following steps:

step S210, acquiring the number of writing bytes from the writing operation;

step S220, determining whether the number of the written bytes is less than or equal to the maximum number of cache bytes of the first-in first-out memory;

step S230, when the number of written bytes is less than or equal to the maximum number of cached bytes, executing a step of obtaining the status of the fifo after receiving a data write signal sent by the system processor.

In this embodiment, before receiving the data write signal sent by the system processor, the user space write function at the system processor side, that is, the write operation is not executed, the user space does not start the system call of the write function, the kernel space write function corresponding to the user space is not executed, which indicates that the kernel space is in an idle state at the moment, when a user space write function at the system processor side is executed, the user space initiates a system call to write the function, then, the kernel space write function corresponding to the user space write function is started, the kernel space write function obtains the number of written bytes of the user space write function, then, judging whether the writing byte number is less than or equal to the maximum buffer byte number of the first-in first-out memory, and when the writing byte number is less than or equal to the maximum cache byte number of the first-in first-out memory, copying the data to be written of the user space writing function from the user space to the kernel space through the kernel space writing function. After the data to be written is copied, the kernel space write function writes a data write signal into a write start register in the data write module to inform the data write module of the programmable logic terminal to prepare for starting write transmission once, and then the kernel space write function enters a sleep state to wait for interruption and awakening.

According to the technical scheme, the writing byte number from the writing operation is acquired, whether the writing byte number is smaller than or equal to the maximum number of cache bytes of the first-in first-out memory or not is determined, and when the writing byte number is smaller than or equal to the maximum number of cache bytes and a data writing signal sent by a system processor is received, the data to be written in the target storage address is stored in the first-in first-out memory, so that the writing byte number written in the first-in first-out memory is judged in real time, and the situation that the data cannot be written in the first-in first-out memory when the writing byte number is large is avoided.

The following is a third embodiment of the present application, and step S121 in the third embodiment of the present application is a refinement step of step S120 in the second embodiment, and includes:

step S121, when the state of the fifo is empty, obtaining a preset number of data to be written in a target storage address in an interrupt manner, so as to cache the data to be written in the fifo.

In this embodiment, when the FIFO empty detection state machine module is in the detection state and detects that the empty flag signal of the FIFO memory is true, a write interrupt signal is generated on the write interrupt line wrirq to indicate that it is ready to receive data to be written, and after the system processor detects the write interrupt signal on the write interrupt line, the system processor notifies the kernel space write function at the system processor end in an interrupt manner to execute a data write module that sends a preset amount of data to be written to the programmable logic end, so as to cache the data to be written to the FIFO memory.

In the technical scheme of this embodiment, by adopting a technical scheme that when the state of the fifo is empty, a preset number of data to be written in a target storage address is obtained in an interrupt manner to cache the data to be written in the fifo, the transmission bandwidth utilization rate of an on-chip interconnection bus and the effective data transmission efficiency of write-once transmission are improved.

As shown in fig. 6, steps S221 to S222 in the fourth embodiment of the present application are another refinement step of step S120 in the second embodiment, and the fourth embodiment of the present application includes the following steps:

step S221, determining the number of writing times according to the number of writing bytes and the data bit width of the on-chip interconnection bus;

step S222, according to the number of times of writing, executing a loop to acquire data to be written, the number of bytes in a target storage address of which is the bit width of the on-chip interconnection bus data, so as to write the data to be written into a data writing register, and caching the data to be written in the data writing register to a first-in first-out memory until a preset number of data to be written is acquired.

In this embodiment, after the kernel space write function at the system processor end is interrupted and awakened, the kernel space write function writes the number of write bytes of the data to be written into a write length register in the data write module; determining the number of writing times according to the number of writing bytes and the data bit width of the on-chip interconnection bus, wherein the number of writing times is determined according to the number of writing bytes of the data to be written and the data bit width of the on-chip interconnection bus, if the number of data bit widths and the number of bytes of the on-chip interconnection bus is 4, the number of writing bytes can be divided by 4, the number of writing times is equal to (writing byte number/4), otherwise, the number of writing times is equal to (writing byte number/4) + 1; and then, according to the write times, circularly executing to write the data to be written, the number of the bytes written at a time of which is the bit width of the on-chip interconnection bus data, into a write data register until the preset number of the data to be written is written.

In this embodiment, the write length register module is configured to detect in real time whether an address of the on-chip interconnect structure bus matches a write length register and a write control signal of the bus is valid, and if yes, store data (i.e., a number of write bytes) of the current on-chip interconnect structure bus in a write length register (wr _ length _ reg) and generate a write length flag signal (wr _ length _ flag), where the write length register is configured to register a number of bytes of data that a driver initiates write-once transmission of actual write data; the data writing register module is used for detecting whether the address of the on-chip interconnection structure bus is matched with the data writing register in real time and the writing control signal of the bus is valid, if so, storing the data of the current on-chip interconnection structure bus, namely the data to be written in the data writing register (wr _ data _ reg), and then immediately inputting the data registered in the data writing register into the first-in first-out memory until the preset amount of the data to be written is stored.

In the technical scheme of the embodiment, a kernel space write function at a system processor end is awakened through interruption; after the kernel space write function is awakened, writing the number of writing bytes of the data to be written into a write length register; determining the number of writing times according to the number of writing bytes of the data to be written and the data bit width of the on-chip interconnection bus; and circularly executing the writing of the data to be written with the single-write byte quantity being the on-chip interconnection bus data bit width into a data writing register according to the writing times, and caching the data to be written in the data writing register into a first-in first-out memory until the preset quantity of the data to be written is obtained, so as to realize the writing of the data to be written in the target storage address into the first-in first-out memory.

As shown in fig. 7, steps S131 to S133 in the fifth embodiment of the present application are the refinement steps of step S130 in the first embodiment, and the fifth embodiment of the present application includes the following steps:

step S131, determining a data byte splitting state in a data splitting state machine;

step S132, splitting the data to be written in the first-in first-out memory into byte stream data based on the data byte splitting state and the on-chip interconnection bus data bit width;

and step S133, inputting the split byte stream data into the programmable logic terminal in sequence.

In this embodiment, as shown in fig. 2, when the write length flag signal (wr _ length _ flag) is asserted, the count register (wr _ count) loads the write length value (wr _ length _ reg), i.e. the number of bytes of the data actually written in a write transfer, and then performs count down according to some state (wr _ state) given by the data split state machine. The data splitting state machine module is used for carrying out data reading control on a first-in first-out memory and splitting control on read 4-byte (on-chip interconnection bus data bit width/8) data. The data splitting state machine has 6 states, which are an idle state, a reading state, a byte one state, a byte two state, a byte three state and a byte four state, and informs the data splitting module to split data in a wr _ state mode. The data splitting module sequentially splits 4 bytes (on-chip interconnection bus data bit width/8) data read from the first-in first-out memory into 4 1-byte data and outputs the data to user logic in the programmable logic terminal according to whether wr _ state is in a byte one state, a byte two state, a byte three state and a byte four state, and if wr _ state jumps back to an idle state from a certain byte state in advance, the remaining byte data is not output.

In this embodiment, when the data split state machine is in the idle state, if the write length flag signal (wr _ length _ flag) is active, the read state is skipped. In the read state, if the read request signal (rdreq) is active, a jump is made to the byte one state; if the count register (wr _ count) is "0", the state jumps back to the idle state. In the byte one state, if the count register (wr _ count) is not "0", then a jump is made to the byte two state, otherwise a jump is made back to the idle state (indicating that only byte one data is output and the remaining 3 bytes of data are discarded). The byte two state and the byte three state are the same as the processing mode of the byte one state. In the byte four state, if the count register (wr _ count) is not "0", the read state is jumped to, otherwise the idle state is jumped back to.

In this embodiment, when reading data from the fifo, it is necessary to first determine whether the state of the fifo is empty, and when the state of the fifo is not empty, data can be read from the fifo only, specifically, a read request signal (rdreq) at a read end of the fifo is generated by a read control module, where the read request signal (rdreq) is generated by determining an empty flag signal (rdempty) at the read end of the fifo, a ready signal ready for reception by user logic, and a state signal (wr _ state) of a data splitting state machine, and when the state of the fifo is not empty, data of the fifo is read to be written into a programmable logic end until all data of the fifo is read.

In the technical scheme of the embodiment, the data byte splitting state in the data splitting state machine is determined; splitting data to be written in the first-in first-out memory into byte stream data based on the data byte splitting state and the on-chip interconnection bus data bit width; and the technical scheme of sequentially inputting the split byte stream data into the programmable logic terminal realizes splitting the data to be written in the first-in first-out memory and sending the data to the programmable logic terminal.

As shown in fig. 8, the sixth embodiment of the present application includes the steps of:

step S310, after receiving a data reading signal sent by a system processor, acquiring the state of a first-in first-out memory;

step S320, splicing byte stream data of a programmable logic terminal based on the on-chip interconnection bus data bit width to obtain data to be read, and caching the spliced data to be read to a first-in first-out memory;

step S330, when the state of the fifo is a readable state, sending a predetermined amount of data to be read from the fifo to a target storage address.

In this embodiment, after receiving a data reading signal sent by a kernel space of a system processor, a read start register sends a pre-known amount of data to be read from a programmable logic terminal to a target storage address, where the pre-known amount indicates that a kernel space read function at the system processor reads an effective number of bytes to be read of the data to be read from a read length register in a data reading module, and the kernel space read function obtains the amount of data cached by a first-in first-out memory; specifically, firstly, a read start register module is started, the read start register module is used for detecting whether an address of an on-chip interconnection structure bus is matched with a read start register and a write control signal of the bus is valid in real time, if yes, a read start flag signal (start _ flag) is generated according to data of the current on-chip interconnection structure bus, and the read start register is used for a driving program to initiate one-time read transmission; secondly, acquiring the state of the first-in first-out memory, and when the state of the first-in first-out memory is readable, informing a kernel space read function at a system processor end in an interrupt mode to execute and acquire a predetermined amount of data to be read from the first-in first-out memory; then, starting a read length register module, wherein the read length register module is used for registering the effective number of bytes read of data to be read of the first-in first-out memory, specifically, the read length register module is used for detecting whether the address of the on-chip interconnection structure bus is matched with the read length register and a read control signal of the bus is effective in real time, and if so, sending the value of the read length register, namely the effective number of bytes read, to a data bus of the on-chip interconnection structure bus; finally, starting a data reading register module, and storing data to be read of the on-chip interconnection structure bus to a target storage address, specifically, the data reading register module is used for detecting whether the address of the on-chip interconnection structure bus is matched with a data reading register and a reading control signal of the bus is valid in real time, if so, reading one data to be read from the on-chip interconnection structure bus to the data reading register, and then immediately sending the value of the data reading register, namely the data to be read to a data bus of the on-chip interconnection structure bus; on the other hand, the kernel space read function reads the data to be read from the read data register to the kernel space until the reading of the data to be read in a preset number is finished, and after the reading of the data to be read is finished, the data to be read is copied to the target storage address of the user space from the kernel space. In parallel, byte stream data logically input by a programmable logic end user is spliced based on-chip interconnection bus data bit width to obtain data to be read, and the spliced data to be read are sequentially input into the first-in first-out memory.

In this embodiment, as shown in fig. 3, the process of the system processor reading data from the programmable logic terminal includes the following modules:

a read start register module: and detecting whether the address of the on-chip interconnection structure bus is matched with the read starting register and the write control signal of the bus is valid at any time. If yes, generating a read start flag signal (start _ flag) according to the data of the current on-chip interconnection structure bus, and then sending the read start flag signal to the overtime monitoring state machine module. The read start register is used for driving a program to initiate a read transmission.

A read length register module: and detecting whether the address of the on-chip interconnection structure bus is matched with the read length register and the read control signal of the bus is valid at any time. And if so, sending the value of the read length register to a data bus of the on-chip interconnection structure bus. The read length register is used for driving a program to initiate one-time reading and transmitting the byte number of the actual read data.

A read data register module: and detecting whether the address of the on-chip interconnection structure bus is matched with the read data register and the read control signal of the bus is valid at any time. If yes, reading out a data from the first-in first-out memory and sending the data to the data bus of the on-chip interconnection structure bus. The read data register is used for driving a program to read data needing to be transmitted from the programmable logic terminal to the CPU terminal.

First-in first-out memory: for buffering data of a read transfer. The data bit width of the write end and the read end is the same as that of the on-chip interconnection structure bus, and the cache depth is set according to the requirement (for example 1024), and the maximum byte number of one-time read transmission is determined by the depth (cache depth is data bit width of the on-chip interconnection bus/8).

The overtime monitoring state machine module: the method is used for monitoring whether one data transmission from the user logic to the first-in first-out memory is overtime or not, and if yes, the last data signal (read _ last) is read to be effective so as to finish the data transmission in advance. At the initial moment, the module is in an idle state, a read start signal (rdstart) is effective, and when a read start flag signal (start _ flag) is effective, the module is triggered to jump to a judgment state; in the judging state, judging whether the data is stored or not through the stored data number (rd _ count) of the reading end of the first-in first-out memory and the output state (read _ state) of the data splicing state machine module, if so, jumping to the detecting state, otherwise, keeping in the state; in the detection state, if the full flag signal (wrfull) of the write-in end of the first-in first-out memory is detected to be effective, the state jumps back to the idle state, if the full flag signal (wrfull) is ineffective and the data ready signal (ready) is detected to be ineffective for more than the preset time, the state jumps to the waiting state, otherwise, the state is kept in the present state; in the wait state, the read start signal (rdstart) is deactivated, which means that the reception of external data is suspended, after several clock cycles, the idle state is jumped back, and the read last data signal (read _ last) is activated.

A read request control module: for generating a read request signal (rdreq). The read request signal (rdreq) is asserted when the DATA ready signal (ready) is asserted and the full flag signal (wrfull) of the FIFO write is deasserted and the read start signal (rdstart) of the time out monitor state machine is asserted.

A read interrupt generation module: and judging whether the overtime monitoring state machine module jumps back to an idle state from other states, if so, generating a reading interrupt signal on a reading interrupt line rdirq to indicate that the data volume required by one-time reading transmission is ready.

A reading length calculation module: for calculating the effective byte number of the actual read data of one read transmission.

In the technical scheme of the embodiment, after receiving a data reading signal sent by a system processor, the state of a first-in first-out memory is acquired; splicing byte stream data of a programmable logic terminal based on-chip interconnection bus data bit width to obtain data to be read, and caching the spliced data to be read into a first-in first-out memory; when the state of the first-in first-out memory is a readable state, the technical scheme of sending a preset amount of data to be read from the first-in first-out memory to a target memory address solves the problem that in the prior art, multiple modules mount the same bus and access the on-chip interconnection bus needs to preempt, so that the data transmission efficiency is reduced, and the data transmission efficiency is improved.

As shown in fig. 9, steps S410 to S430 in the seventh embodiment of the present application are located before step S310 in the sixth embodiment, and the seventh embodiment includes the following steps:

step S410, acquiring the number of bytes read from the read operation;

step S420, determining whether the number of bytes read is less than or equal to the maximum number of cache bytes of the first-in first-out memory;

step S430, when the number of bytes read is less than or equal to the maximum number of bytes buffered, the step of obtaining the status of the fifo memory after receiving the data read signal sent by the system processor is executed.

In this embodiment, before receiving a data reading signal sent by a system processor, a user space read function at a system processor end, that is, a read operation is not executed, the user space does not start a system call of the read function, a kernel space read function corresponding to the user space read function is not executed, which indicates that the kernel space is in an idle state at this time, when the user space read function at the system processor end is executed, the user space starts the system call of the read function, then starts the kernel space read function corresponding to the user space read function, the kernel space read function obtains the number of bytes read of the user space read function, then determines whether the number of bytes read is less than or equal to the maximum number of bytes cached in a first-in first-out memory, and when the number of bytes read is less than or equal to the maximum number of bytes cached in the first-in first-out memory, the kernel space read function writes the data reading signal into a read start register in the data reading module, the data reading module at the programmable logic terminal is informed to prepare for starting one-time reading transmission, and then the kernel space reading function enters the dormancy state to wait for interruption and awakening.

According to the technical scheme, the reading byte number from the reading operation is acquired; determining whether the number of bytes read is less than or equal to the maximum number of cache bytes of a first-in first-out memory; when the number of reading bytes is less than or equal to the maximum number of cache bytes, the technical means of acquiring the state of the first-in first-out memory after receiving a data reading signal sent by a system processor realizes the limitation of the maximum number of reading bytes of one-time data reading of reading operation so as to avoid reading out the boundary.

As shown in fig. 10, steps S321 to S323 in the eighth embodiment of the present application are refinement steps of step S320 in the sixth embodiment, which includes the steps of:

step S321, determining a data byte splicing state in a data splicing state machine;

step S322, splicing byte stream data input by a programmable logic terminal based on the data byte splicing state and the on-chip interconnection bus data bit width to obtain data to be read;

and step S323, sequentially inputting the spliced data to be read into the first-in first-out memory.

In this embodiment, as shown in fig. 3, after the byte stream data in fig. 3 is logically input to the data reading module from the user, the byte stream data needs to be spliced to form data to be read, and then the data to be read is cached in the first-in first-out memory, in this process, first, the data byte splicing state in the data splicing state machine is determined; splicing byte stream data logically input by a programmable logic end user based on the data byte splicing state and the bit width of the on-chip interconnection bus to obtain data to be read; finally, the spliced data to be read are sequentially input into the first-in first-out memory; specifically, the splicing of byte stream data and the buffering of data to be read into a first-in first-out memory are performed through the following modules:

a data splicing state machine module: the data splicing method comprises the following steps of splicing 1 byte of data input by a user logic for controlling a programmable logic terminal into 4 bytes (on-chip interconnection bus data bit width/8) of data; the state machine has 4 states, which are divided into a byte one state, a byte two state, a byte three state and a byte four state, and informs the data splicing module to splice data in a read _ state mode.

A data splicing module: the method is used for splicing 1 byte data input by user logic into 4 byte data, namely data to be read, and then writing the data to be read into a first-in first-out memory. And splicing 1-byte data to 4-byte data by using the output state (read _ state) of the data splicing state machine module. When the last data signal (read _ last) is read to be valid, 4 bytes of data are written into the first-in first-out memory regardless of whether the data are spliced or not, so that the data transmission is completed in advance, therefore, the 4 bytes of data contain invalid bytes of data, and the invalid bytes of data cannot be recorded by the read length calculation module, so that the correct transmission is ensured.

In this embodiment, at the initial time, the state of the data splicing state machine module is in a byte one state; when a data valid signal (valid) input by the user logic is valid, jumping to the next state in a polling mode, otherwise, keeping in the current state; in the byte two state, byte three state, byte four state, if the data valid signal (valid) is invalid and the read last data signal (read _ last) is valid, then a jump back to the byte one state occurs.

According to the technical scheme, the data byte splicing state in the data splicing state machine is determined; splicing byte stream data input by a programmable logic terminal based on the data byte splicing state and the on-chip interconnection bus data bit width to obtain data to be read; the technical means that the spliced data to be read are sequentially input into the first-in first-out memory realizes splicing byte stream data of the user logic of the programmable logic terminal to obtain the data to be read.

The following is a ninth embodiment of the present application, and step S331 in the ninth embodiment is a refinement step of step S330 in the sixth embodiment, and includes:

in step S331, when the state of the fifo is a readable state, a predetermined amount of data to be read is sent from the fifo to a target memory address in an interrupt manner.

In this embodiment, whether the state of the fifo memory is a readable state is determined, and when the state of the fifo memory is unreadable, i.e., no data, the state of the fifo memory is always waited to be readable, where the determination of the readable state is based on: the FIFO memory caches enough data or caches partial data but the waiting reading time is overtime, specifically, whether the overtime monitoring state machine module jumps back to an idle state from other states is judged, if yes, a reading interrupt signal is generated on a reading interrupt line rdirq to indicate that the data to be read required by one-time reading transmission is ready, and after the system processor detects the reading interrupt signal on the reading interrupt line, the system processor informs a kernel space reading function at the system processor end in an interrupt mode to execute the execution of obtaining the pre-known amount of data to be read from the FIFO memory, and sends the data to be read to a target storage address.

In the technical scheme of this embodiment, when the state of the fifo memory is a readable state, a predetermined amount of data to be read is sent from the fifo memory to a target memory address in an interrupt manner, so that the transmission bandwidth utilization rate of the on-chip interconnection bus and the effective data transmission efficiency of one-time read transmission are improved.

As shown in fig. 11, steps S531 to S533 in the tenth embodiment of the present application are the refinement steps of step S330 in the sixth embodiment, which includes the steps of:

step S531, when the state of the first-in first-out memory is a readable state, determining the effective byte number of the data to be read in the first-in first-out memory;

step S532, determining the number of reading times according to the effective byte number of the data to be read and the data bit width of the on-chip interconnection bus;

step S533, according to the number of reading times, cyclically executing to output the data to be read from the fifo memory to the read data register, and sending the data to be read in the read data register to a target memory address until a predetermined number of data to be read is sent.

In this embodiment, when the state of the fifo is a readable state, the read length calculation module calculates an effective number of bytes to be read of the data to be read in the fifo, and registers the value in the read length register (rd _ length _ reg), and specifically, the read length calculation module calculates an effective number of bytes to be read of the data to be read in the fifo by detecting an output state (out _ state) of the timeout monitoring state machine module and a full flag signal (wrfull) at a write-in end of the fifo or an output state (read _ state) of the data concatenation state machine module and reading a last data signal (read _ last) and registers the value in the read length register.

In this embodiment, the read length register module is configured to detect whether an address of the on-chip interconnect structure bus matches the read length register in real time and a read control signal of the bus is valid, and if yes, send a value (i.e., an effective number of bytes read) of the read length register to the data bus of the on-chip interconnect structure bus, where the read length register is configured to register an effective number of bytes of data that the driver initiates a read transmission of actual read data; the data reading register module is used for detecting whether the address of the on-chip interconnection structure bus is matched with the data reading register in real time and the reading control signal of the bus is valid, if so, reading data to be read from the first-in first-out memory to the data reading register, and immediately sending the value of the data reading register (namely the data to be read) to the data bus of the on-chip interconnection structure bus.

In this embodiment, after the kernel space read function at the system processor is interrupted and awakened, the kernel space read function reads the effective number of bytes read from the read length register in the data read module; determining the number of reading times according to the number of effective reading bytes and the data bit width of the on-chip interconnection bus, wherein the number of reading times is determined according to the number of effective reading bytes of the data to be read and the data bit width of the on-chip interconnection bus, if the number of data bit width bytes of the on-chip interconnection bus is 4, the number of effective reading bytes can be divided by 4, the number of reading times is equal to (the number of effective reading bytes/4), otherwise, the number of reading times is equal to (the number of effective reading bytes/4) + 1; then, according to the reading times, circularly executing reading of the data to be read with the single reading byte quantity being the data bit width of the on-chip interconnection bus from a data reading register in the data reading module to the kernel space until the reading of the data to be read with the preset quantity is completed; after the data to be read is read, the kernel space read function copies the data to be read from the kernel space to a target storage address of a user space, and returns the effective number of bytes read of the data to be read to the user space read function.

In the technical scheme of the embodiment, a kernel space read function at a system processor end is awakened through interruption; after the kernel space read function is awakened, the kernel space read function reads the effective byte number of the data to be read from the read length register; determining the number of reading times according to the effective reading byte number of the data to be read and the data bit width of the on-chip interconnection bus; and circularly executing the technical scheme of reading the data to be read with the single reading byte quantity being the bit width of the on-chip interconnection bus data from the data reading register to the kernel space according to the reading times until the reading of the data to be read with the preset quantity is finished, and copying the data to be read from the kernel space to the target storage address of the user space, so that the data to be read of the programmable logic terminal is read to the target storage address.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.