阅读说明：本技术 靴带式开关 (Boot strap type switch ) 是由 黄诗雄 于 2019-10-14 设计创作，主要内容包括：本发明揭露一种靴带式开关,该开关包含第一晶体管、第二晶体管、电容及五个开关。该第一晶体管接收输入电压并且输出输出电压。该第二晶体管的第一端接收输入电压,第二端耦接电容的第一端。于第一频率相位时,电容充电。于第二频率相位时,第一晶体管的控制端及第二晶体管的控制端与电容第二端实质上等电位。第一晶体管的控制端及第二晶体管的控制端于第一频率相位结束前的预设时间内或第二频率相位开始后的预设时间内耦接电源电压。(The invention discloses a bootstrap switch, which comprises a first transistor, a second transistor, a capacitor and five switches. The first transistor receives an input voltage and outputs an output voltage. The first terminal of the second transistor receives an input voltage, and the second terminal is coupled to the first terminal of the capacitor. In the first frequency phase, the capacitor is charged. In the second frequency phase, the control end of the first transistor, the control end of the second transistor and the second end of the capacitor are substantially equal in potential. The control end of the first transistor and the control end of the second transistor are coupled with the power voltage within a preset time before the end of the first frequency phase or within a preset time after the start of the second frequency phase.)

1. A bootstrap switch, receiving an input voltage and outputting an output voltage, comprising:

a first transistor having a first terminal, a second terminal and a first control terminal, wherein the first terminal receives the input voltage and the second terminal outputs the output voltage;

a capacitor having a third terminal and a fourth terminal;

a second transistor having a fifth terminal, a sixth terminal and a second control terminal, wherein the fifth terminal receives the input voltage, the sixth terminal is electrically connected to the third terminal of the capacitor, and the second control terminal is electrically connected to the first control terminal of the first transistor;

a first switch coupled between the third terminal of the capacitor and a first reference voltage;

a second switch coupled between the fourth terminal of the capacitor and a second reference voltage;

a third switch coupled between the fourth terminal of the capacitor and the first control terminal of the first transistor;

a fourth switch coupled between the first control terminal of the first transistor and the first reference voltage; and

a fifth switch coupled between the first control terminal of the first transistor and the second reference voltage;

when the first frequency phase is carried out, the first switch, the second switch and the fourth switch are conducted, and the third switch is not conducted, so that the capacitor is charged;

wherein, in a second frequency phase, the third switch is conducted and the first switch, the second switch and the fourth switch are not conducted; and

the fifth switch is turned on within a predetermined time before the first clock phase ends or within the predetermined time after the second clock phase begins, so that the first control terminal of the first transistor and the second control terminal of the second transistor are coupled to the second reference voltage within the predetermined time.

2. The bootstrap switch of claim 1, wherein the second switch is a transistor having a seventh terminal, an eighth terminal and a third control terminal, wherein the seventh terminal is coupled to the second reference voltage, the eighth terminal is coupled to the fourth terminal of the capacitor, and the third control terminal receives a frequency.

3. The bootstrap switch of claim 1, wherein the second switch is a transistor having a seventh terminal, an eighth terminal and a third control terminal, wherein the seventh terminal is coupled to the second reference voltage, the eighth terminal is coupled to the fourth terminal of the capacitor, and the third control terminal is electrically connected to the first control terminal of the first transistor.

4. A bootstrap switch, receiving an input voltage and outputting an output voltage, comprising:

a first transistor having a first terminal, a second terminal and a first control terminal, wherein the first terminal receives the input voltage and the second terminal outputs the output voltage;

a first capacitor having a third terminal and a fourth terminal;

a second transistor having a fifth terminal, a sixth terminal and a second control terminal, wherein the fifth terminal receives the input voltage, the sixth terminal is electrically connected to the third terminal of the first capacitor, and the second control terminal is electrically connected to the first control terminal of the first transistor;

a first switch coupled between the third terminal of the first capacitor and a first reference voltage;

a third transistor having a seventh terminal, an eighth terminal, and a first substrate, wherein the seventh terminal is coupled to a second reference voltage, and the eighth terminal is coupled to the fourth terminal of the first capacitor;

a fourth transistor having a ninth terminal, a tenth terminal, and a second substrate, wherein the ninth terminal is coupled to the first control terminal of the first transistor, and the tenth terminal is coupled to the fourth terminal of the first capacitor;

a second switch coupled between the first control terminal of the first transistor and the first reference voltage; and

a second capacitor having a tenth end and a twelfth end, wherein the twelfth end is electrically connected to the first substrate and/or the second substrate;

when a first frequency phase is carried out, the first switch is conducted, the third transistor is started, the second switch is conducted, and the fourth transistor is closed so as to charge the first capacitor;

when a second frequency phase is carried out, the fourth transistor is started, the first switch is not conducted, the third transistor is closed, and the second switch is not conducted; and

the second capacitor is charged in the first frequency phase, the tenth terminal of the second capacitor is coupled to a third reference voltage in the second frequency phase, and the sum of a first voltage of the first capacitor and the input voltage is less than or equal to the sum of a second voltage of the second capacitor and the third reference voltage in the second frequency phase.

5. The bootie switch according to claim 4, wherein the third transistor is a P-type metal oxide semiconductor field effect transistor, and the first substrate is not electrically connected to the seventh terminal and the eighth terminal.

6. The bootie switch according to claim 4, wherein the fourth transistor is a P-type metal oxide semiconductor field effect transistor, and the second substrate is not electrically connected to the ninth terminal and the tenth terminal.

7. The bootstrap switch of claim 4, further comprising:

a third switch coupled between the first control terminal of the first transistor and the second reference voltage;

the third switch is turned on within a preset time before the first frequency phase ends or within the preset time after the second frequency phase begins, so that the first control end of the first transistor and the second control end of the second transistor are coupled to the second reference voltage within the preset time.

8. The bootstrap switch of claim 7, wherein the third transistor further has a third control terminal, and the third control terminal receives a frequency.

9. The bootstrap switch of claim 7, wherein the third transistor further has a third control terminal, and the third control terminal is electrically connected to the first control terminal of the first transistor.

10. A bootstrap switch having an input and an output, the switch comprising:

a first transistor coupled between the input terminal and the output terminal and having a first control terminal;

a capacitor having a first end and a second end;

a second transistor coupled between the input terminal and the first terminal of the capacitor and having a second control terminal electrically connected to the first control terminal of the first transistor; and

a plurality of switches coupled to the first control terminal of the first transistor, the second control terminal of the second transistor, the first terminal of the capacitor, the second terminal of the capacitor, a first reference voltage and a second reference voltage, and including a first portion and a second portion;

a target switch coupled between the first control terminal of the first transistor and the second reference voltage;

wherein the switches of the first portion are turned on and the switches of the second portion are turned off to charge the capacitor in a first frequency phase;

wherein, in a second frequency phase, the switches of the first part are not conducted, and the switches of the second part are conducted, so that the first control end of the first transistor and the second end of the capacitor have corresponding potentials; and

the target switch is turned on within a preset time before the first frequency phase ends or within the preset time after the second frequency phase begins, so that the first control end of the first transistor and the second control end of the second transistor are coupled to the second reference voltage within the preset time.

Technical Field

The present invention relates to a bootstrap switch (bootstrap switch), and more particularly, to a bootstrap switch having high linearity.

Background

Fig. 1 is a circuit diagram of a conventional bootstrap switch. The bootstrap switch 10 includes a switch 101, a switch 102, a switch 103, a switch 104, a switch 105, a metal-oxide-semiconductor field-effect transistor (MOSFET) (hereinafter referred to as NMOS)106, and a bootstrap capacitor (bootstrap capacitor) 107. The input VI and the output VO of the bootstrap switch 10 are coupled to the source (source) and the drain (drain) of the NMOS 106, respectively. The gate (gate) of the NMOS 106 is coupled to the voltage source V3 through the switch 105, and is coupled to one end of the bootstrap capacitor 107 and one end of the switch 101 through the switch 104. The other end of the switch 101 is coupled to a voltage source V1. The other end of the bootstrap capacitor 107 is coupled to the voltage source V2 through the switch 102, and to the source of the NMOS 106 and the input VI of the bootstrap switch 10 through the switch 103. The voltage source V1 is at a high voltage level, and the voltage sources V2 and V3 are at a ground level. The operation of the bootstrap switch 10 is well known to those of ordinary skill in the art and will not be described in detail.

The bootstrap switch can improve the linearity of the switch, however, when the switch element in the bootstrap switch is made of a transistor (such as a metal oxide semiconductor field effect transistor or a Bipolar Junction Transistor (BJT)), the parasitic capacitance of the transistor often causes the charge loss of the bootstrap capacitor in the bootstrap switch, resulting in the linearity of the bootstrap switch being not as good as expected.

Disclosure of Invention

In view of the deficiencies of the prior art, it is an object of the present invention to provide a high linearity boot strap switch.

The invention discloses a boot strap type switch. The bootstrap switch receives an input voltage and outputs an output voltage, and includes a first transistor, a capacitor, a second transistor, a first switch, a second switch, a third switch, a fourth switch, and a fifth switch. The first transistor has a first terminal, a second terminal and a first control terminal, wherein the first terminal receives the input voltage, and the second terminal outputs the output voltage. The capacitor has a third terminal and a fourth terminal. The second transistor has a fifth terminal, a sixth terminal and a second control terminal, wherein the fifth terminal receives the input voltage, the sixth terminal is electrically connected to the third terminal of the capacitor, and the second control terminal is electrically connected to the first control terminal of the first transistor. The first switch is coupled between the third terminal of the capacitor and a first reference voltage. The second switch is coupled between the fourth terminal of the capacitor and a second reference voltage. The third switch is coupled between the fourth terminal of the capacitor and the first control terminal of the first transistor. The fourth switch is coupled between the first control end of the first transistor and the first reference voltage. The fifth switch is coupled between the first control end of the first transistor and the second reference voltage. And when the first frequency phase is carried out, the first switch, the second switch and the fourth switch are conducted, and the third switch is not conducted so as to charge the capacitor. And in a second frequency phase, the third switch is conducted, and the first switch, the second switch and the fourth switch are not conducted. The fifth switch is turned on within a predetermined time before the first clock phase ends or within the predetermined time after the second clock phase begins, so that the first control terminal of the first transistor and the second control terminal of the second transistor are coupled to the second reference voltage within the predetermined time.

The invention also discloses a boot strap type switch. The bootstrap switch receives an input voltage and outputs an output voltage, and includes a first transistor, a first capacitor, a second transistor, a first switch, a third transistor, a fourth transistor, a second switch, and a second capacitor. The first transistor has a first terminal, a second terminal and a first control terminal, wherein the first terminal receives the input voltage, and the second terminal outputs the output voltage. The first capacitor has a third terminal and a fourth terminal. The second transistor has a fifth terminal, a sixth terminal and a second control terminal, wherein the fifth terminal receives the input voltage, the sixth terminal is electrically connected to the third terminal of the first capacitor, and the second control terminal is electrically connected to the first control terminal of the first transistor. The first switch is coupled between the third terminal of the first capacitor and a first reference voltage. The third transistor has a seventh terminal, an eighth terminal and a first substrate, wherein the seventh terminal is coupled to a second reference voltage, and the eighth terminal is coupled to the fourth terminal of the first capacitor. The fourth transistor has a ninth terminal, a tenth terminal and a second substrate, wherein the ninth terminal is coupled to the first control terminal of the first transistor, and the tenth terminal is coupled to the fourth terminal of the first capacitor. The second switch is coupled between the first control end of the first transistor and the first reference voltage. The second capacitor has an eleventh end and a twelfth end, wherein the twelfth end is electrically connected to the first substrate and/or the second substrate. In a first frequency phase, the first switch is turned on, the third transistor is turned on, the second switch is turned on, and the fourth transistor is turned off to charge the first capacitor. In a second frequency phase, the fourth transistor is turned on, the first switch is not turned on, the third transistor is turned off, and the second switch is not turned on. The second capacitor is charged in the first frequency phase, the tenth end of the second capacitor is coupled to a third reference voltage in the second frequency phase, and the sum of the first voltage across the first capacitor and the input voltage is less than or equal to the sum of the second voltage across the second capacitor and the third reference voltage in the second frequency phase.

The invention discloses a boot strap type switch with an input end and an output end. The bootstrap switch comprises a first transistor, a capacitor, a second transistor, a plurality of switches and a target switch. The first transistor is coupled between the input end and the output end and is provided with a first control end. The capacitor has a first terminal and a second terminal. The second transistor is coupled between the input terminal and the first terminal of the capacitor and has a second control terminal electrically connected to the first control terminal of the first transistor. The switches are coupled to the first control terminal of the first transistor, the second control terminal of the second transistor, the first terminal of the capacitor, the second terminal of the capacitor, the first reference voltage and the second reference voltage, and include a first portion and a second portion. The target switch is coupled between the first control end of the first transistor and a second reference voltage. In the first frequency phase, the switch of the first part is conducted, and the switch of the second part is not conducted, so as to charge the capacitor. And in the second frequency phase, the switch of the first part is not conducted, and the switch of the second part is conducted, so that the first control end of the first transistor and the second end of the capacitor have corresponding potentials. The target switch is turned on within a preset time before the first frequency phase ends or within a preset time after the second frequency phase begins, so that the first control end of the first transistor and the second control end of the second transistor are coupled to the second reference voltage within the preset time.

The bootstrap capacitor can be weakened by the influence of the parasitic capacitor of the transistor. Compared with the prior art, the boot strap type switch has higher linearity.

The features, practical operations and effects of the present invention will be described in detail with reference to the drawings.

Drawings

FIG. 1 is a circuit diagram of a prior art boot strap switch;

FIG. 2 is a circuit diagram of a bootstrap switch in accordance with an embodiment of the present invention;

FIG. 3 shows frequencies Φ 1, Φ 1b, Φ p1, and Φ p 2;

FIG. 4 is a waveform diagram illustrating an example of the input voltage Vin and the voltage at the control terminal of the transistor M1;

FIG. 5 is a circuit diagram of a bootstrap switch in accordance with another embodiment of the present invention;

FIG. 6 is a circuit diagram of a bootstrap switch in accordance with another embodiment of the present invention;

FIG. 7 is a circuit diagram of a bootstrap switch in accordance with another embodiment of the present invention; and

fig. 8 is a circuit diagram of a bootstrap switch in accordance with another embodiment of the present invention.

Detailed Description

In the following description, the technical terms refer to the common terms in the technical field, and some terms are explained or defined in the specification, and the explanation of the some terms is based on the explanation or the definition in the specification.

The present disclosure includes a bootstrap switch. Since some of the components included in the bootlace switch of the present invention may individually be known components, the following description will omit details of the known components without affecting the full disclosure and feasibility of the present invention.

Fig. 2 is a circuit diagram of a bootstrap switch according to an embodiment of the present invention. The bootstrap switch 100 receives an input voltage Vin via an input terminal IN and outputs an output voltage Vout via an output terminal OUT. The bootstrap switch 100 includes a switch 110, a switch 120, a switch 130, a switch 140, a switch 150, a switch 160, a switch 170, and a bootstrap capacitor C_b. The switches 110, 120, 130, 140, 150, 160 and 170 may be implemented by transistors M1, M7, M2, M3, M8, M4 and M11, respectively. Each transistor has a first terminal, a second terminal and a control terminal, and the first terminal and the second terminal are both terminals of the switch formed by the transistor. For a MOSFET, the first terminal may be one of the source or the drain, the second terminal the other, and the control terminal the gate. For a BJT, the first terminal can be one of a collector (collector) or an emitter (emitter), the second terminal is the other, and the control terminal is a base (base).

As shown in FIG. 2, in some embodiments, the control terminal of the transistor M1 and the crystalThe control terminals of the transistor M7 are electrically connected to each other, and both are further electrically connected to the first terminal of the transistor M11. The transistor M1 receives the input voltage Vin at a second terminal and outputs the output voltage Vout from a first terminal. The first terminal of the transistor M7 receives the input voltage Vin, and the second terminal of the transistor M7 is electrically connected to the bootstrap capacitor C_bThe first end of (a). A first terminal of the transistor M2 is coupled to the bootstrap capacitor C_bAnd a second terminal of the transistor M2 is coupled to a first reference voltage (ground level in the example of fig. 2). A first terminal of the transistor M3 is coupled to the bootstrap capacitor C_bAnd a second terminal of the transistor M3 is coupled to a second reference voltage (in the example of fig. 2, the power voltage VDD). A first terminal of the transistor M8 is coupled to the control terminal of the transistor M1, the control terminal of the transistor M7 and the first terminal of the transistor M11, and a second terminal of the transistor M8 is coupled to the bootstrap capacitor C_bThe second end of (a). The first terminal of the transistor M4 is coupled to the first reference voltage, and the second terminal of the transistor M4 is coupled to the control terminal of the transistor M1, the control terminal of the transistor M7 and the first terminal of the transistor M11. The first terminal of the transistor M11 is electrically connected to the control terminal of the transistor M1 and the control terminal of the transistor M7, and the second terminal of the transistor M11 is coupled to a second reference voltage (in the example of fig. 2, the power voltage VDD).

The switches 130, 140, 150, 160 are rendered conductive (transistor on) or non-conductive (transistor off) depending on the frequencies Φ 1 and Φ 1 b. Fig. 3 shows an example of frequencies Φ 1 and Φ 1b, where the frequency Φ 1 is the inverse of the frequency Φ 1 b. Under the control of the frequencies Φ 1 and Φ 1b, the bootstrap switch 100 alternately operates in the first frequency phase Ph1 (the frequency Φ 1 is low and the frequency Φ 1b is high) and the second frequency phase Ph2 (the frequency Φ 1 is high and the frequency Φ 1b is low). The switch 170 is controlled by the frequency Φ p. In some embodiments, the frequency Φ p is low for a preset time T1 after the start of the second frequency phase Ph2, as illustrated by the frequency Φ p1 of fig. 3. In other embodiments, the frequency Φ p is low for a predetermined time T1 before the end of the first frequency phase Ph1, as shown by the frequency Φ p2 of fig. 3. In other words, the switch 170 is turned on during the predetermined time T1 before and after the transition point of the first frequency phase Ph1 to the second frequency phase Ph2, so that the potentials of the control terminal of the transistor M1 and the control terminal of the transistor M7 during the predetermined time T1 are substantially equal to the second reference Voltage (VDD). In some embodiments, the preset time T1 may be designed to be the time required for the transistor M8 to be fully turned on after the second frequency phase Ph2 starts; the transistor M8 is fully turned on, which means that the first terminal and the second terminal of the transistor M8 are substantially at the same voltage level. The details of the operation of the bootstrap switch 100 will be described below.

In some embodiments, the switch 170 may also be referred to as a target switch.

Refer to fig. 2 and 3. During the first frequency phase Ph1, switch 160, switch 130, and switch 140 are conductive, and switch 150 is non-conductive. When the switch 160 is turned on, the voltages at the control terminal of the transistor M1 and the control terminal of the transistor M7 are substantially equal to the first reference voltage, such that the switches 110 and 120 are not turned on. In other words, when the switch 170 is not taken into account (i.e., the preset time T1 is not taken into account), the switches 110 and 120 are not turned on during the first frequency phase Ph 1. When the switches 130 and 140 are turned on, the bootstrap capacitor C_bThe voltages at the two ends are substantially the first reference voltage and the second reference voltage respectively. In other words, the bootstrap capacitor C_bCharging during the first frequency phase Ph1, and bootstrapping capacitor C after the end of the first frequency phase Ph1_bThe voltage Vcb is substantially equal to a voltage difference between the first reference voltage and the second reference voltage.

During the second frequency phase Ph2, switch 160, switch 130, and switch 140 are non-conductive, and switch 150 is conductive. When the switch 150 is turned on, the control terminals of the transistor M1 and the transistor M7 are substantially connected to the bootstrap capacitor C_bThe second terminal of the capacitor is at the same potential (i.e. the control terminal of the transistor M1 and the control terminal of the transistor M7 and the bootstrap capacitor C)_bHas a corresponding potential) so that the transistors M1 and M7 are formed by the bootstrap capacitor C_bUpper voltage Vcb. When the transistor M7 is turned on, the bootstrap capacitor C_bAnd the voltage at the second terminal of the transistor M1 is substantially equal to the sum of the input voltage Vin and the voltage across Vcb. When the transistor M1 is turned on, the output voltage Vout is substantially equal to the input voltage Vin, i.e., the bootstrap switch 100 is turned on.

Switch 150 is switched from a non-conducting state toDuring a predetermined time T1 before or after the conducting state, the switch 170 is turned on, so that the transistor M8 is turned on completely (i.e. the control terminal of the transistor M1 and the bootstrap capacitor C)_bBefore the second terminal of the transistor M1 and the control terminal of the transistor M7 and the first terminal of the transistor M8 substantially receive the second reference voltage due to the conduction of the switch 170. In this way, the parasitic capacitances of the transistors M1, M7, and M8 are charged by the second reference voltage before the transistor M8 is fully turned on, so the bootstrap capacitor C is used after the transistor M8 is fully turned on_bThe parasitic capacitances do not cause charge loss, and the linearity of the bootstrap switch 100 is improved. In other words, because the switch 170 is set and the on-time thereof is carefully designed, when the bootstrap switch 100 is turned on, the voltage of the control terminal of the transistor M1 is substantially equal to the sum of the input voltage Vin and the voltage across Vcb, that is, the voltage difference between the control terminal of the transistor M1 and the second terminal of the transistor M1 is substantially constant during the on-time of the bootstrap switch 100 (i.e., substantially equal to the voltage across Vcb, which does not vary with the input voltage Vin), so that the linearity of the bootstrap switch 100 can be ensured.

It should be noted that in the present embodiment, the control terminal of the transistor M7 is electrically connected to the control terminal of the transistor M1, rather than being controlled by the frequency Φ 1, such a design can avoid the situation that the transistor M7 is not completely turned on when the difference between the input voltage Vin and the high or low level of the frequency Φ 1 is smaller than the threshold voltage (threshold voltage) of the transistor M7. Incomplete turn-on of transistor M7 will result in reduced linearity of the bootstrap switch 100.

Fig. 4 shows waveforms of an example of the input voltage Vin and the voltage at the control terminal of the transistor M1. Curve 310 represents the input voltage Vin and curve 320 represents the voltage at the control terminal of transistor M1. In this example, the first reference voltage is ground, the second reference voltage is a power supply voltage VDD (═ 1.2V), and the difference between the first reference voltage and the second reference voltage is the bootstrap capacitor C_bThe cross voltage Vcb. The value of the curve 320 during the first frequency phase Ph1 is 0 (ground), while the value of the curve 320 during the second frequency phase Ph2 is the input voltage Vin plus the voltage difference Vd, in other words the voltage difference Vd is the control of the transistor M1Terminating the obtained bootstrap voltage. It can be seen that the voltage difference Vd is quite close to the voltage across Vcb, which represents the bootstrap capacitance C_bThe parasitic capacitor on the path to the control terminal of the transistor M1 is substantially fully charged within the predetermined time T1, and therefore the bootstrap capacitor C is charged during the conduction of the bootstrap switch 100_bThere is substantially no loss of charge on.

Fig. 5 is a circuit diagram of a bootstrap switch in accordance with another embodiment of the present invention. The bootstrap switch 400 is similar to the bootstrap switch 100, except that the control terminal of the transistor M3 is coupled to the control terminal of the transistor M1 and the switch 170. As such, during the second frequency phase Ph2, the voltage at the control terminal of the transistor M3 is substantially the sum of the input voltage Vin and the voltage across Vcb, rather than the voltage at the frequency Φ 1. Such a design may provide the following benefits: since the two terminals of the parasitic capacitor of the transistor M3 (the control terminal of the transistor M3 and the first terminal or the second terminal of the transistor M3) have substantially equal voltage values (i.e., the sum of the input voltage Vin and the voltage across Vcb) during the second frequency phase Ph2, the bootstrap capacitor C is turned on during the bootstrap switch 400_bThe charge on the transistor M3 is not distributed to the parasitic capacitance of the transistor M3, i.e., the voltage across Vcb is not reduced by the influence of the parasitic capacitance of the transistor M3.

Fig. 6 is a circuit diagram of a bootstrap switch in accordance with another embodiment of the present invention. In contrast to the bootstrap switch 400, the bootstrap switch 500 further includes a switch 180, a switch 185, a switch 190 and a switch 195 implemented by a transistor M10, a transistor M9, a transistor M5 and a transistor M6, respectively. The switch 180 is coupled between the control terminal of the transistor M1 and the switch 160, and the control terminal of the transistor M10 is coupled to the second reference voltage. The switch 185 is coupled between the second reference voltage and the control terminal of the transistor M8, and is controlled by the frequency Φ 1. The switch 190 is coupled to the bootstrap capacitor C_bAnd the control terminal of transistor M8, and is controlled by frequency Φ 1. The switch 195 is coupled to the bootstrap capacitor C_bAnd a control terminal of the transistor M6 is electrically connected to the control terminal of the transistor M1 and the control terminal of the transistor M7. The transistors M5, M6, M9 and M10 are used to provide the operation of the bootstrapped switch 500The overvoltage protection during the operation process is used to prolong the service life of the device, and the operation principle thereof is well known by those skilled in the art, and thus is not described herein again.

With continued reference to fig. 6. Without the switch 170, the conduction of the bootstrap switch 500 must be through the turning on of the transistor M5, the turning on of the transistor M8, the turning on of the transistors M1 and M7, resulting in the bootstrap switch 500 being turned on too slowly. However, the switch 170 solves this problem because the switch 170 can change the voltages of the control terminals of the transistor M1 and the transistor M7 in advance, so that the transistor M1 and the transistor M7 can be turned on substantially immediately after the bootstrap switch 500 enters the turn-on phase (i.e., the second frequency phase Ph 2). As such, the bootstrap switch 500 has a higher response speed.

Fig. 7 is a circuit diagram of a bootstrap switch in accordance with another embodiment of the present invention. The bootstrap switch 600 is similar to the bootstrap switch 100, except that the bootstrap switch 600 does not include the switch 170, but further includes the capacitor C_bdSwitch 610 and switch 620. Capacitor C_bdIs coupled to the first reference voltage or the third reference voltage (i.e., Vbias) through switch 610, capacitor C_bdIs coupled to a second reference voltage through a switch 620. Switches 610 and 620 are controlled by frequency Φ 1b and frequency Φ 1, respectively, such that: during the first frequency phase Ph1, the capacitance C_bdIs coupled to a first reference voltage and a second reference voltage, and a capacitor C during a second frequency phase Ph2_bdThe first terminal of the first transistor is coupled to a third reference voltage and the second terminal of the second transistor is not coupled to a second reference voltage.

It is noted that the body (bulk) of the transistor M3 is not electrically connected to the first terminal and the second terminal of the transistor M3, and the body of the transistor M8 is not electrically connected to the first terminal and the second terminal of the transistor M8. In this embodiment, the body of transistor M3 and the body of transistor M8 are both electrically connected to node Nb (i.e., capacitor C)_bdThe second terminal of transistor M3) and in other embodiments, the node Nb may be electrically connected to only one of the body of transistor M3 and the body of transistor M8, with the body not electrically connected to the node Nb electrically connecting either the first or second terminal of the same transistor。

During the first frequency phase Ph1, the capacitance C_bdCharged and capacitor C when the first frequency phase Ph1 ends_bdIs substantially equal to the difference between the second reference voltage and the first reference voltage. During the second frequency phase Ph2, the voltage Vnb of the node Nb is the sum of the cross-voltage Vcbd and the third reference voltage (i.e., Vnb ═ Vcbd + Vbias). Because the node Nb is electrically connected to the body of the transistor M3 and/or the body of the transistor M8, the capacitance C is present during the second frequency phase Ph2_bdThe charge is distributed to the parasitic capacitance of the transistor M3 and/or the parasitic capacitance of the transistor M8, in other words, the parasitic capacitances are charged. With capacitance C during the second frequency phase Ph2_bdThe benefit of charging the parasitic capacitance of transistor M3 and/or the parasitic capacitance of transistor M8 is: the parasitic capacitance of the transistor M3 and/or the parasitic capacitance of the transistor M8 do not consume the bootstrap capacitance C_bCharge on, thus bootstrapping the capacitor C_bMay be substantially fully applied to the control terminal of transistor M1.

Since the transistors M3 and M8 are P-type metal oxide semiconductor field effect transistors (PMOS for short), the capacitor C is bootstrapped during the second frequency phase Ph2_bWhen the voltage at the second terminal of the transistor M3 (or the transistor M8) varies with the input voltage Vin, the body and the drain or the source of the transistor M3 (or the transistor M8) may be forward biased, which may cause the transistor M3 (or the transistor M8) to fail to operate normally. In order to prevent the above-mentioned situation from occurring, the voltage Vnb may be designed to be equal to or greater than the bootstrap capacitor C_bI.e., Vcbd + Vbias ≧ Vin + Vcb. In the embodiment of fig. 7, Vcbd and Vcb are substantially equal (equal to the difference between the second reference voltage and the first reference voltage), so that the forward bias of the transistor M3 and/or the transistor M8 can be prevented by ensuring Vbias ≧ Vin. In some embodiments, the third reference voltage (i.e., Vbias) may be substantially equal to the second reference voltage (i.e., power supply voltage VDD), since power supply voltage VDD ≧ Vin in general.

The embodiment of fig. 7 may be combined with the embodiments of fig. 2, 5 or 6, for example, the bootlace switch 700 shown in fig. 8 is a combination of the bootlace switch 600 and the bootlace switch 100. Those skilled in the art can implement the combination of the bootstrap switch 600 and the bootstrap switch 400 and the combination of the bootstrap switch 600 and the bootstrap switch 500 according to the above disclosure, and therefore, the detailed description thereof is omitted.

The PMOS and NMOS in the aforementioned embodiments can be replaced by NMOS and PMOS, respectively, and those skilled in the art know how to adaptively adjust the phases or levels of the frequency Φ 1, the frequency Φ 1b, and the frequency Φ p, and adaptively adjust the first reference voltage, the second reference voltage, and the third reference voltage to realize the above-described implementation.

It should be noted that the shapes, sizes, proportions and the like of the elements in the drawings are illustrative only, and are not intended to be limiting, since one of ordinary skill in the art will understand the present invention.

Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.

[ notation ] to show

10. 100, 400, 500, 600, 700 bootstrap switch

101. 102, 103, 104, 105, 110, 120, 130, 140, 150, 160, 170, 180, 185, 190, 195, 610, 620 switches

106 NMOS

107、C_bBootstrap capacitor

VI input

VO output

V1, V2 and V3 voltage sources

Vin input voltage

IN input terminal

Vout output voltage

OUT output terminal

M1-M11 transistor

VDD Power supply Voltage

Vcb, Vcbd voltage step

Phi 1, phi 1b, phi p1, phi p2 frequencies

Ph1 first frequency phase

Ph2 second frequency phase

T1 preset time

310. Curve 320

Vd voltage difference

C_bdCapacitor with a capacitor element

Vbias reference voltage

And (4) Nb nodes.