阅读说明：本技术 一种基于双极性rram的非易失性触发器 (Nonvolatile trigger based on bipolar RRAM ) 是由 吴佳 李礼 吴叶楠 于 2021-03-12 设计创作，主要内容包括：本发明涉及触发器相关设备领域,尤其涉及一种基于双极性RRAM的非易失性触发器,如摘要附图所示,由PMOS晶体管1、PMOS晶体管2、PMOS晶体管3、PMOS晶体管4、PMOS晶体管5、NMOS晶体管1、NMOS晶体管2、NMOS晶体管3、NMOS晶体管4、NMOS晶体管5、限流电阻R1、限流电阻R2、限流电阻R3、限流电阻R4、参考电阻R5、反相器1、反相器2、反相器3、反相器4、阻变随机存储器RRAM组成,输入端有电源VDD、地GND、输入数据D和输入时钟PK,输出端为输出数据Q。本发明的基于双极性RRAM的非易失性触发器,解决了传统触发器在断电后数据不能保存,恢复供电后之前存储的数据不能恢复的问题。(The invention relates to the field of related equipment of triggers, in particular to a nonvolatile trigger based on bipolar RRAM (random access memory), which is shown in an abstract figure and comprises a PMOS (P-channel metal oxide semiconductor) transistor 1, a PMOS (P-channel metal oxide semiconductor) transistor 2, a PMOS transistor 3, a PMOS transistor 4, a PMOS transistor 5, an NMOS (N-channel metal oxide semiconductor) transistor 1, an NMOS transistor 2, an NMOS transistor 3, an NMOS transistor 4, an NMOS transistor 5, a current-limiting resistor R1, a current-limiting resistor R2, a current-limiting resistor R3, a current-limiting resistor R4, a reference resistor R5, an inverter 1, an inverter 2, an inverter 3, an inverter 4 and a RRAM (resistive random access memory), wherein the input end is provided with a power supply VDD (voltage. The nonvolatile trigger based on the bipolar RRAM solves the problems that the data cannot be stored after the power failure of the traditional trigger and the data stored before the power supply is recovered cannot be recovered.)

1. A nonvolatile trigger based on bipolar RRAM is composed of a PMOS transistor 1, a PMOS transistor 2, a PMOS transistor 3, a PMOS transistor 4, a PMOS transistor 5, an NMOS transistor 1, an NMOS transistor 2, an NMOS transistor 3, an NMOS transistor 4, an NMOS transistor 5, a current limiting resistor R1, a current limiting resistor R2, a current limiting resistor R3, a current limiting resistor R4, a reference resistor R5, an inverter 1, an inverter 2, an inverter 3, an inverter 4 and a resistive random access memory RRAM, wherein the input end is provided with a power supply VDD, a ground GND, input data D and an input clock PK, the output end is output data Q,

the drain of the PMOS transistor 1 is connected with the source of the PMOS transistor 2, the source of the PMOS transistor 1 is connected with a power supply VDD, the gate of the PMOS transistor 1 is connected with a signal BPK, the bulk of the PMOS transistor 1 is connected with the power supply VDD, the drain of the PMOS transistor 2 is connected with one end of a current-limiting resistor R1, the source of the PMOS transistor 2 is connected with the drain of the PMOS transistor 1, the gate of the PMOS transistor 2 is connected with input data D, the bulk of the PMOS transistor 2 is connected with the power supply VDD, the drain of the PMOS transistor 3 is connected with the source of the PMOS transistor 4, the source of the PMOS transistor 3 is connected with the power supply VDD, the gate of the PMOS transistor 3 is connected with a signal BPK, the bulk of the PMOS transistor 3 is connected with the PMOS power supply VDD, the drain of the PMOS transistor 4 is connected with one end of a current-limiting resistor R3, the source of the PMOS transistor 4 is, the body of the PMOS transistor 4 is connected with a power supply VDD;

the drain electrode of the PMOS transistor 5 is connected with a port A of an RRAM (resistive random access memory), the source electrode of the PMOS transistor 5 is connected with a power supply VDD, the gate electrode of the PMOS transistor 5 is connected with an input clock PK, the bulk of the PMOS transistor 5 is connected with the power supply VDD, the drain electrode of the NMOS transistor 1 is connected with the source electrode of the NMOS transistor 2, the source electrode of the NMOS transistor 1 is connected with a ground GND, the gate electrode of the NMOS transistor 1 is connected with a signal PK, and the bulk of the NMOS transistor 1 is connected with the ground GND;

the drain of the NMOS transistor 2 is connected with one end of a current-limiting resistor R2, the source of the NMOS transistor 2 is connected with the drain of the NMOS transistor 1, the gate of the NMOS transistor 2 is connected with input data D, the body of the NMOS transistor 2 is connected with a ground GND, the drain of the NMOS transistor 3 is connected with the source of the NMOS transistor 4, the source of the NMOS transistor 3 is connected with the ground GND, the gate of the NMOS transistor 3 is connected with a signal PK, and the body of the NMOS transistor 3 is connected with the ground GND;

the drain of the NMOS transistor 4 is connected with one end of a current limiting resistor R4, the source of the NMOS transistor 4 is connected with the drain of the NMOS transistor 3, the gate of the NMOS transistor 4 is connected with a signal BD, the body of the NMOS transistor 4 is connected with the ground GND,

the drain of the NMOS transistor 5 is connected to the port B of the RRAM, the source of the NMOS transistor 5 is connected to one end of a reference resistor R5, the gate of the NMOS transistor 5 is connected to the signal BPK, the bulk of the NMOS transistor 5 is connected to GND, one end of the current limiting resistor R1 is connected to the drain of the PMOS transistor 2, and the other end is connected to the port a of the RRAM;

one end of the current limiting resistor R2 is connected with the drain electrode of the NMOS transistor 2, the other end of the current limiting resistor R2 is connected with the port A of the RRAM, one end of the current limiting resistor R3 is connected with the drain electrode of the PMOS transistor 4, and the other end of the current limiting resistor R3 is connected with the port B of the RRAM;

one end of the current-limiting resistor R4 is connected with the drain electrode of the NMOS transistor 4, the other end of the current-limiting resistor R4 is connected with the port B of the RRAM, one end of the reference resistor R5 is connected with the source electrode of the NMOS transistor 5, the other end of the reference resistor R5 is connected with the ground GND, the input end of the inverter 1 is connected with input data D, the output end of the inverter is connected with a signal BD, and the input data D generates an inverted data signal BD through the inverter 1;

the input clock PK is connected to the input of inverter 2, signal BPK is connected to the output, input clock PK passes through inverter 2 and produces inverted clock signal BPK, RRAM's port B is connected to the input of inverter 3, and the input of inverter 4 is connected to the output, inverter 3's output is connected to the input of inverter 4, and the output connects output data Q, PMOS transistor 5's drain electrode, the other end of resistance R1 and the other end of resistance R2 are connected to RRAM's port A, NMOS transistor 5's drain electrode, the other end of resistance R3, the other end of resistance R4 and inverter 3's input are connected to RRAM's port B.

2. The bipolar RRAM-based nonvolatile flip-flop of claim 1, wherein: the inverter circuit is composed of a PMOS transistor and an NMOS transistor as shown IN the attached figure 2 of the specification, wherein the source electrode and the body of the PMOS transistor are connected with a power supply VDD, the drain electrode is connected with the drain electrode and the output end OUT of the NMOS transistor, the grid electrode is connected with an input end IN, the source electrode and the body of the NMOS transistor are connected with a ground GND, the drain electrode is connected with the drain electrode and the output end OUT of the PMOS transistor, and the grid electrode is connected with the input end IN.

3. The bipolar RRAM-based nonvolatile flip-flop of claim 1, wherein: the resistance value of the resistive random access memory RRAM in a high resistance state is not less than 100 times of the resistance value of the resistive random access memory RRAM in a low resistance state.

4. The bipolar RRAM-based nonvolatile flip-flop of claim 1, wherein: the ratio of the resistance values of the current limiting resistor R1, the current limiting resistor R2, the current limiting resistor R3 and the current limiting resistor R4 to the resistance value of the RRAM in a low resistance state is 0.05-1.

5. The bipolar RRAM-based nonvolatile flip-flop of claim 1, wherein: the ratio of the reference resistor R5 resistance to the RRAM low resistance state resistance is between 10 and 20.

Technical Field

The invention relates to the field of trigger-related equipment, in particular to a nonvolatile trigger based on a bipolar RRAM.

Background

The flip-flop is one of the most used units in a sequential logic circuit, and is widely used in the current integrated circuits, because the data of the traditional flip-flop cannot be stored after power failure and the data stored before power restoration cannot be restored after power restoration, the data which is not stored after the integrated circuits such as a microprocessor and the like are suddenly powered off can be lost,

a Resistive Random Access Memory (RRAM) is a nonvolatile memory device that stores data information by changing its own resistance, and has two ports, and a bipolar RRAM refers to a type of RRAM having the following characteristics: after the RRAM is manufactured, before a certain voltage is applied between two ports for the first time, the RRAM is in a high resistance state, the direction of the first applied voltage is in a positive voltage direction, and when a certain positive voltage is applied between the two ports of the RRAM, the resistance of the RRAM is reduced, and a low resistance state is presented; when a certain negative voltage is applied between two ports of the RRAM, the resistance of the RRAM is increased to present a high resistance state, after power failure, the resistance of the bipolar RRAM is kept unchanged,

the utility model discloses a non-volatile latch and integrated circuit based on RRAM is disclosed to utility model patent for application number 202020063538.8, this circuit has proposed a non-volatile latch based on RRAM, two these latches can constitute a flip-flop, but this circuit needs special chronogenesis to carry out the backup operation, just can keep the data of latch after writing into RRAM with the value of latch through the backup operation, the operation chronogenesis of this circuit is not compatible the operation chronogenesis of traditional CMOS latch, the transistor that needs and RRAM are many in quantity, be unfavorable for using in large-scale integrated circuit, also be unfavorable for compatible traditional CMOS integrated circuit.

Disclosure of Invention

To solve the problems set forth in the background art described above. The invention provides a bipolar RRAM-based nonvolatile trigger which has the characteristics of still storing data when power is off and keeping the stored data unchanged after power is restored.

In order to achieve the above purpose, the invention adopts the technical scheme that: a nonvolatile trigger based on bipolar RRAM comprises a PMOS transistor 1, a PMOS transistor 2, a PMOS transistor 3, a PMOS transistor 4, a PMOS transistor 5, an NMOS transistor 1, an NMOS transistor 2, an NMOS transistor 3, an NMOS transistor 4, an NMOS transistor 5, a current limiting resistor R1, a current limiting resistor R2, a current limiting resistor R3, a current limiting resistor R4, a reference resistor R5, an inverter 1, an inverter 2, an inverter 3, an inverter 4, a resistive random access memory RRAM, a power supply VDD, a ground GND, input data D and an input clock PK at the input end, and output data Q at the output end,

the drain of the PMOS transistor 1 is connected with the source of the PMOS transistor 2, the source of the PMOS transistor 1 is connected with a power supply VDD, the gate of the PMOS transistor 1 is connected with a signal BPK, the bulk of the PMOS transistor 1 is connected with the power supply VDD, the drain of the PMOS transistor 2 is connected with one end of a current-limiting resistor R1, the source of the PMOS transistor 2 is connected with the drain of the PMOS transistor 1, the gate of the PMOS transistor 2 is connected with input data D, the bulk of the PMOS transistor 2 is connected with the power supply VDD, the drain of the PMOS transistor 3 is connected with the source of the PMOS transistor 4, the source of the PMOS transistor 3 is connected with the power supply VDD, the gate of the PMOS transistor 3 is connected with a signal BPK, the bulk of the PMOS transistor 3 is connected with the PMOS power supply VDD, the drain of the PMOS transistor 4 is connected with one end of a current-limiting resistor R3, the source of the PMOS transistor 4 is, the body of the PMOS transistor 4 is connected with a power supply VDD;

the drain electrode of the PMOS transistor 5 is connected with a port A of an RRAM (resistive random access memory), the source electrode of the PMOS transistor 5 is connected with a power supply VDD, the gate electrode of the PMOS transistor 5 is connected with an input clock PK, the bulk of the PMOS transistor 5 is connected with the power supply VDD, the drain electrode of the NMOS transistor 1 is connected with the source electrode of the NMOS transistor 2, the source electrode of the NMOS transistor 1 is connected with a ground GND, the gate electrode of the NMOS transistor 1 is connected with a signal PK, and the bulk of the NMOS transistor 1 is connected with the ground GND;

the drain of the NMOS transistor 2 is connected with one end of a current-limiting resistor R2, the source of the NMOS transistor 2 is connected with the drain of the NMOS transistor 1, the gate of the NMOS transistor 2 is connected with input data D, the body of the NMOS transistor 2 is connected with a ground GND, the drain of the NMOS transistor 3 is connected with the source of the NMOS transistor 4, the source of the NMOS transistor 3 is connected with the ground GND, the gate of the NMOS transistor 3 is connected with a signal PK, and the body of the NMOS transistor 3 is connected with the ground GND;

the drain of the NMOS transistor 4 is connected with one end of a current limiting resistor R4, the source of the NMOS transistor 4 is connected with the drain of the NMOS transistor 3, the gate of the NMOS transistor 4 is connected with a signal BD, the body of the NMOS transistor 4 is connected with the ground GND,

the drain of the NMOS transistor 5 is connected to the port B of the RRAM, the source of the NMOS transistor 5 is connected to one end of a reference resistor R5, the gate of the NMOS transistor 5 is connected to the signal BPK, the bulk of the NMOS transistor 5 is connected to GND, one end of the current limiting resistor R1 is connected to the drain of the PMOS transistor 2, and the other end is connected to the port a of the RRAM;

one end of the current limiting resistor R2 is connected with the drain electrode of the NMOS transistor 2, the other end of the current limiting resistor R2 is connected with the port A of the RRAM, one end of the current limiting resistor R3 is connected with the drain electrode of the PMOS transistor 4, and the other end of the current limiting resistor R3 is connected with the port B of the RRAM;

one end of the current-limiting resistor R4 is connected with the drain electrode of the NMOS transistor 4, the other end of the current-limiting resistor R4 is connected with the port B of the RRAM, one end of the reference resistor R5 is connected with the source electrode of the NMOS transistor 5, the other end of the reference resistor R5 is connected with the ground GND, the input end of the inverter 1 is connected with input data D, the output end of the inverter is connected with a signal BD, and the input data D generates an inverted data signal BD through the inverter 1;

the input clock PK is connected to the input of inverter 2, signal BPK is connected to the output, input clock PK passes through inverter 2 and produces inverted clock signal BPK, RRAM's port B is connected to the input of inverter 3, and the input of inverter 4 is connected to the output, inverter 3's output is connected to the input of inverter 4, and the output connects output data Q, PMOS transistor 5's drain electrode, the other end of resistance R1 and the other end of resistance R2 are connected to RRAM's port A, NMOS transistor 5's drain electrode, the other end of resistance R3, the other end of resistance R4 and inverter 3's input are connected to RRAM's port B.

Further, the inverter circuit comprises a PMOS transistor and an NMOS transistor, as shown in fig. 2 in the specification. The source and the body of the PMOS transistor are connected with a power supply VDD, the drain is connected with the drain of the NMOS transistor and an output end OUT, the grid is connected with an input end IN, the source of the NMOS transistor and the body are connected with a ground GND, the drain is connected with the drain of the PMOS transistor and the output end OUT, and the grid is connected with the input end IN.

Further, the resistance value of the resistive random access memory RRAM in a high resistance state is not less than 100 times of the resistance value of the resistive random access memory RRAM in a low resistance state.

Further, the ratio of the resistance values of the current limiting resistor R1, the current limiting resistor R2, the current limiting resistor R3 and the current limiting resistor R4 to the resistance value of the RRAM in the low resistance state is between 0.05 and 1.

Further, the ratio of the reference resistor R5 to the RRAM low resistance state resistance is between 10 and 20.

The invention has the beneficial effects that:

1. the nonvolatile trigger based on the bipolar RRAM solves the problems that the data cannot be stored after the traditional trigger is powered off and the data stored before the power supply is recovered cannot be recovered.

2. The bipolar RRAM-based nonvolatile trigger can still store data after the circuit is powered off, and the data stored before power supply is restored is unchanged.

3. The bipolar RRAM-based nonvolatile trigger has a very simple structure, uses fewer transistors and RRAMs, and is favorable for being used in a large-scale integrated circuit.

4. The nonvolatile trigger based on the bipolar RRAM is basically consistent with the traditional trigger in the operation time sequence, and is beneficial to being compatible with the traditional CMOS integrated circuit.

Drawings

Fig. 1 is a schematic diagram of a bipolar RRAM-based non-volatile flip-flop topology.

Fig. 2 is a schematic diagram of an inverter circuit in an example of a specific application of the bipolar RRAM-based nonvolatile flip-flop.

Fig. 3 is a schematic diagram of an optional duty cycle adjusting circuit in a specific application example of the nonvolatile flip-flop based on the bipolar RRAM.

FIG. 4 is a block diagram of a process for initializing a write "1" of a nonvolatile flip-flop based on a bipolar RRAM.

Detailed Description

The following detailed description of the present invention is given for the purpose of better understanding technical solutions of the present invention by those skilled in the art, and the present description is only exemplary and explanatory and should not be construed as limiting the scope of the present invention in any way.

As shown in fig. 1 to 4, the specific structure of the present invention is: a nonvolatile trigger based on bipolar RRAM comprises a PMOS transistor 1, a PMOS transistor 2, a PMOS transistor 3, a PMOS transistor 4, a PMOS transistor 5, an NMOS transistor 1, an NMOS transistor 2, an NMOS transistor 3, an NMOS transistor 4, an NMOS transistor 5, a current limiting resistor R1, a current limiting resistor R2, a current limiting resistor R3, a current limiting resistor R4, a reference resistor R5, an inverter 1, an inverter 2, an inverter 3, an inverter 4, a resistive random access memory RRAM, a power supply VDD, a ground GND, input data D and an input clock PK at the input end, and output data Q at the output end,

the drain of the PMOS transistor 1 is connected with the source of the PMOS transistor 2, the source of the PMOS transistor 1 is connected with a power supply VDD, the gate of the PMOS transistor 1 is connected with a signal BPK, the bulk of the PMOS transistor 1 is connected with the power supply VDD, the drain of the PMOS transistor 2 is connected with one end of a current-limiting resistor R1, the source of the PMOS transistor 2 is connected with the drain of the PMOS transistor 1, the gate of the PMOS transistor 2 is connected with input data D, the bulk of the PMOS transistor 2 is connected with the power supply VDD, the drain of the PMOS transistor 3 is connected with the source of the PMOS transistor 4, the source of the PMOS transistor 3 is connected with the power supply VDD, the gate of the PMOS transistor 3 is connected with a signal BPK, the bulk of the PMOS transistor 3 is connected with the PMOS power supply VDD, the drain of the PMOS transistor 4 is connected with one end of a current-limiting resistor R3, the source of the PMOS transistor 4 is, the body of the PMOS transistor 4 is connected with a power supply VDD;

the drain electrode of the PMOS transistor 5 is connected with a port A of an RRAM (resistive random access memory), the source electrode of the PMOS transistor 5 is connected with a power supply VDD, the gate electrode of the PMOS transistor 5 is connected with an input clock PK, the bulk of the PMOS transistor 5 is connected with the power supply VDD, the drain electrode of the NMOS transistor 1 is connected with the source electrode of the NMOS transistor 2, the source electrode of the NMOS transistor 1 is connected with a ground GND, the gate electrode of the NMOS transistor 1 is connected with a signal PK, and the bulk of the NMOS transistor 1 is connected with the ground GND;

the drain of the NMOS transistor 2 is connected with one end of a current-limiting resistor R2, the source of the NMOS transistor 2 is connected with the drain of the NMOS transistor 1, the gate of the NMOS transistor 2 is connected with input data D, the body of the NMOS transistor 2 is connected with a ground GND, the drain of the NMOS transistor 3 is connected with the source of the NMOS transistor 4, the source of the NMOS transistor 3 is connected with the ground GND, the gate of the NMOS transistor 3 is connected with a signal PK, and the body of the NMOS transistor 3 is connected with the ground GND;

the drain of the NMOS transistor 4 is connected with one end of a current limiting resistor R4, the source of the NMOS transistor 4 is connected with the drain of the NMOS transistor 3, the gate of the NMOS transistor 4 is connected with a signal BD, the body of the NMOS transistor 4 is connected with the ground GND,

the drain of the NMOS transistor 5 is connected to the port B of the RRAM, the source of the NMOS transistor 5 is connected to one end of a reference resistor R5, the gate of the NMOS transistor 5 is connected to the signal BPK, the bulk of the NMOS transistor 5 is connected to GND, one end of the current limiting resistor R1 is connected to the drain of the PMOS transistor 2, and the other end is connected to the port a of the RRAM;

one end of the current limiting resistor R2 is connected with the drain electrode of the NMOS transistor 2, the other end of the current limiting resistor R2 is connected with the port A of the RRAM, one end of the current limiting resistor R3 is connected with the drain electrode of the PMOS transistor 4, and the other end of the current limiting resistor R3 is connected with the port B of the RRAM;

one end of the current-limiting resistor R4 is connected with the drain electrode of the NMOS transistor 4, the other end of the current-limiting resistor R4 is connected with the port B of the RRAM, one end of the reference resistor R5 is connected with the source electrode of the NMOS transistor 5, the other end of the reference resistor R5 is connected with the ground GND, the input end of the inverter 1 is connected with input data D, the output end of the inverter is connected with a signal BD, and the input data D generates an inverted data signal BD through the inverter 1;

the input clock PK is connected to the input of inverter 2, signal BPK is connected to the output, input clock PK passes through inverter 2 and produces inverted clock signal BPK, RRAM's port B is connected to the input of inverter 3, and the input of inverter 4 is connected to the output, inverter 3's output is connected to the input of inverter 4, and the output connects output data Q, PMOS transistor 5's drain electrode, the other end of resistance R1 and the other end of resistance R2 are connected to RRAM's port A, NMOS transistor 5's drain electrode, the other end of resistance R3, the other end of resistance R4 and inverter 3's input are connected to RRAM's port B.

Preferably, the inverter circuit comprises a PMOS transistor and an NMOS transistor, wherein the source and the bulk of the PMOS transistor are connected to the power supply VDD, the drain is connected to the drain and the output terminal OUT of the NMOS transistor, the gate is connected to the input terminal IN, the source and the bulk of the NMOS transistor are connected to the ground GND, the drain is connected to the drain and the output terminal OUT of the PMOS transistor, and the gate is connected to the input terminal IN.

Preferably, the resistance value in the high resistance state in the resistive random access memory RRAM is not less than 100 times of the resistance value in the low resistance state.

Preferably, the ratio of the resistance values of the current limiting resistor R1, the current limiting resistor R2, the current limiting resistor R3 and the current limiting resistor R4 to the resistance value of the RRAM in the low resistance state is between 0.05 and 1.

Preferably, the ratio of the reference resistor R5 to the RRAM low resistance state resistance is between 10 and 20.

Specifically, before the bipolar RRAM-based nonvolatile flip-flop circuit is manufactured and data is written for the first time, the internal RRAM is in a high-resistance state, since the high-resistance state resistance of the RRAM is far larger than the reference resistance R5, the node B is at a low level, the output Q is at a low level (logic "0"), and in order to ensure that data is written correctly subsequently, the flip-flop needs to be initialized by writing "1".

The initialization flow for writing "1" is as follows:

step S101: the input clock PK is set to a low level (logic "0"), and the input D is set to a high level (logic "1") or a low level (logic "0");

step S102: powering on a power supply VDD; at this time, the PMOS transistor 1 and the PMOS transistor 3 are turned off, the NMOS transistor 1 and the NMOS transistor 3 are turned off, the PMOS transistor 5 and the NMOS transistor 5 are turned on, since the RRAM high resistance state resistance is much larger than the reference resistance R5, the node B is at a low level, and the output terminal Q is at a low level;

step S103: setting input D to a high level (logic "1");

step S104: setting an input clock PK to be high level and keeping time T; at this time, since D is high (logic "1"), the PMOS transistor 1 is turned on, the PMOS transistor 2 is turned off, the NMOS transistor 1 and the NMOS transistor 2 are turned on, the PMOS transistor 3 and the PMOS transistor 4 are turned on, the NMOS transistor 3 is turned on, and the NMOS transistor 4 is turned off, so that the port a of the RRAM is grounded to GND through the current limiting resistor R2, the port B of the RRAM is connected to the power supply VDD through the current limiting resistor R3, the RRAM is changed from a high resistance state to a low resistance state, and the positive voltage is in a direction from B to a; because the low resistance state resistance of the RRAM is much larger than the current limiting resistors R2 and R3, the node B is at a high level and the output Q is at a high level (logic "1");

step S105: setting an input clock PK to be a low level, and finishing initialization; at this time, the PMOS transistor 1 and the PMOS transistor 3 are turned off, the NMOS transistor 1 and the NMOS transistor 3 are turned off, the PMOS transistor 5 and the NMOS transistor 5 are turned on, and since the RRAM low resistance state resistance is much smaller than the reference resistance R5, the node B is at a high level, and the output terminal Q is at a high level (logic "1").

By adopting the scheme, the working process of the nonvolatile trigger circuit based on the bipolar RRAM is as follows:

if the input data D is at a high level (logic "1"), when the input clock PK changes from a low level to a high level and maintains the holding time T, the PMOS transistor 1 is turned on, the PMOS transistor 2 is turned off, the NMOS transistor 1 and the NMOS transistor 2 are turned on, the PMOS transistor 3 and the PMOS transistor 4 are turned on, the NMOS transistor 3 is turned on, and the NMOS transistor 4 is turned off, so that the port a of the RRAM is grounded GND through the current limiting resistor R2, the port B of the RRAM is connected to the power supply VDD through the current limiting resistor R3, the voltage direction is B to a, and the voltage direction is the same as the positive voltage direction, the RRAM is at a low resistance state, since the low resistance state of the RRAM is much larger than the current limiting resistors R2 and R3, the node B is at a high level, and the output terminal Q; next, after the input clock PK is changed from the high level to the low level, the PMOS transistor 1 and the PMOS transistor 3 are turned off, the NMOS transistor 1 and the NMOS transistor 3 are turned off, the PMOS transistor 5 and the NMOS transistor 5 are turned on, since the RRAM is kept in the low resistance state, the resistance of the RRAM in the low resistance state is much smaller than the reference resistance R5, the node B is the high level, and the output terminal Q is the high level (logic "1");

if the input data D is at a low level (logic "0"), when the input clock PK changes from a low level to a high level and maintains the holding time T, the PMOS transistor 1 and the PMOS transistor 2 are turned on, the NMOS transistor 1 is turned on, the NMOS transistor 2 is turned off, the PMOS transistor 3 is turned on, the PMOS transistor 4 is turned off, the NMOS transistor 3 and the NMOS transistor 4 are turned on, so that the port a of the RRAM is connected to the power supply VDD through the current limiting resistor R1, the port B of the RRAM is connected to the ground GND through the current limiting resistor R4, the voltage direction is a to B, and the voltage direction is opposite to the positive voltage direction, so that the RRAM is at a high resistance state, and since the high resistance state of the RRAM is much larger than the current limiting resistors R2 and R3, the node B is at a low level, and; next, after the input clock PK is changed from the high level to the low level, the PMOS transistor 1 and the PMOS transistor 3 are turned off, the NMOS transistor 1 and the NMOS transistor 3 are turned off, the PMOS transistor 5 and the NMOS transistor 5 are turned on, since the RRAM is kept in the high resistance state, the resistance of the RRAM in the high resistance state is much larger than that of the reference resistor R5, the node B is the low level, and the output terminal Q is the low level (logic "0");

if the circuit is powered off, the resistance of the RRAM keeps unchanged, and correct output can still be recovered after the RRAM is powered on;

the high level holding time T of the input clock PK is the time for ensuring the correct transition of the RRAM resistance state; this may result in the duty cycle of the input clock PK not being 50%; in order to be more convenient to be compatible with the traditional trigger input clock with 50% duty ratio, a clock duty ratio adjusting circuit can be preferably adopted, and the input clock with 50% duty ratio is adjusted to a clock signal with high level retention time which can ensure the correct conversion of RRAM resistance state;

in a particular application, an alternative duty cycle adjustment circuit is shown in fig. 3; the input clock CK is a clock with 50% duty ratio; after the CK passes through the delay unit and the inverter, the CK and the CK output a clock PK after performing AND operation with the CK, and the high level time of the PK is the delay time of the delay unit; one of the delay cells is implemented as a series connection of N inverters, where N is an even number.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts of the present invention. The foregoing is only a preferred embodiment of the present invention, and it should be noted that there are objectively infinite specific structures due to the limited character expressions, and it will be apparent to those skilled in the art that a plurality of modifications, decorations or changes may be made without departing from the principle of the present invention, and the technical features described above may be combined in a suitable manner; such modifications, variations, combinations, or adaptations of the invention using its spirit and scope, as defined by the claims, may be directed to other uses and embodiments.