阅读说明：本技术 固态摄像元件和电子设备 (Solid-state image pickup element and electronic apparatus ) 是由 马上崇 江藤毅 于 2019-09-06 设计创作，主要内容包括：固态摄像元件(10),其包括：噪声消除信号生成电路(12),其连接到像素电源(PW),且被构造成对所生成的第一噪声消除信号(NC1)执行增益切换和极性反转以输出第二噪声消除信号(XNC1)；DA转换器(13),其被构造成生成和输出参照信号(RAMP)、并且将第二噪声消除信号(XNC1)的电流转换为电压以将转换后的电压叠加于参照信号(RAMP)上；比较器(14),参照信号(RAMP)和像素信号(VSL)经由与差分对的一个端子连接的输入电容而被输入到比较器本体部(42),所述比较器依据像素信号(VSL)及增益设定来输出反转信号；计数器(18),其将比较器(14)的反转时序转换为数字值；以及增益控制单元(15),其在改变参照信号(RAMP)的斜率及上述输入电容以执行对比较器(14)的增益控制时,输出基于上述输入电容中的改变量的增益控制信号。(A solid-state image pickup element (10) includes: a noise cancellation signal generation circuit (12) connected to the pixel power supply (PW) and configured to perform gain switching and polarity inversion on the generated first noise cancellation signal (NC1) to output a second noise cancellation signal (XNC 1); a DA converter (13) configured to generate and output a reference signal (RAMP), and convert a current of the second noise cancellation signal (XNC1) into a voltage to superimpose the converted voltage on the reference signal (RAMP); a comparator (14) to which a reference signal (RAMP) and a pixel signal (VSL) are input to a comparator main body (42) via an input capacitance connected to one terminal of the differential pair, the comparator outputting an inversion signal in accordance with the pixel signal (VSL) and a gain setting; a counter (18) that converts the inversion timing of the comparator (14) into a digital value; and a gain control unit (15) that outputs a gain control signal based on the amount of change in the input capacitance when changing the slope of the reference signal (RAMP) and the input capacitance to perform gain control of the comparator (14).)

1. A solid-state image pickup element comprising:

a pixel that outputs a pixel signal;

a noise cancellation signal generation circuit connected to a pixel power supply that supplies power to the pixels, the noise cancellation signal generation circuit being configured to:

generating a first noise removal signal for removing power supply noise of the pixel power supply; and is

Performing gain switching and polarity inversion on the first noise cancellation signal based on a gain control signal, thereby outputting a second noise cancellation signal;

a digital-to-analog converter configured to:

generating a reference signal and outputting the generated reference signal, the reference signal being a ramp signal; and is

Converting the current of the second noise cancellation signal into a voltage to superimpose the converted voltage on the reference signal;

a comparator to which the reference signal and the pixel signal are input via an input capacitance connected to one terminal of a differential pair and which outputs an inverted signal having a timing corresponding to the pixel signal and a gain setting;

a counter that converts an inverted timing of the comparator into a digital value; and

a gain control unit that outputs the gain control signal based on an amount of change in the input capacitance when changing a slope of the reference signal and the input capacitance to perform gain control of the comparator.

2. The solid-state image pickup element according to claim 1,

the comparator includes an input capacitance switching unit including:

a first capacitor connected between an input terminal and the one terminal of the differential pair;

a plurality of second capacitors each having one end connected to the one terminal of the differential pair; and

a plurality of switches for connecting the second capacitor and the first capacitor in parallel with each other.

3. The solid-state image pickup element according to claim 1,

the noise cancellation signal generation circuit includes:

a pixel power supply input unit connected to the pixel power supply;

a first noise removal signal generation unit that converts a pixel power supply voltage input via the pixel power supply input unit into a current to generate the first noise removal signal; and

a gain switching/inverting circuit that performs gain switching and polarity inversion on the first noise cancellation signal based on the gain control signal.

4. The solid-state image pickup element according to claim 3,

the gain switching/inverting circuit includes:

a first transistor group including a plurality of transistors connected in parallel to each other and capable of flowing a current amount proportional to a current amount of the first noise cancellation signal;

a second transistor group including a plurality of transistors connected in parallel with each other, connected in series with the first transistor group, and capable of flowing a predetermined constant current; and

a third transistor group connected in parallel with the first transistor group and capable of outputting the second noise cancellation signal.

5. The solid-state image pickup element according to claim 4, further comprising:

a fourth transistor group that constitutes a current mirror circuit together with the third transistor group and that is capable of adjusting a gain of the second noise cancel signal to output the adjusted gain.

6. An electronic device, comprising:

a pixel array unit in which a plurality of pixels each outputting a pixel signal are arranged in an array;

a noise cancellation signal generation circuit connected to a pixel power supply that supplies power to the pixels, the noise cancellation signal generation circuit being configured to:

generating a first noise removal signal for removing power supply noise of the pixel power supply; and is

Performing gain switching and polarity inversion on the first noise cancellation signal based on a gain control signal, thereby outputting a second noise cancellation signal;

a digital-to-analog converter configured to:

generating a reference signal and outputting the generated reference signal, the reference signal being a ramp signal; and is

Converting the current of the second noise cancellation signal into a voltage to superimpose the converted voltage on the reference signal;

a comparator to which the reference signal and the pixel signal are input via an input capacitance connected to one terminal of a differential pair and which outputs an inverted signal having a timing corresponding to the pixel signal and a gain setting;

a counter that converts an inverted timing of the comparator into a digital value;

a gain control unit that outputs the gain control signal based on an amount of change in the input capacitance when changing a slope of the reference signal and the input capacitance to perform gain control of the comparator; and

an image data processing unit that processes image data based on an output of the counter.

Technical Field

The present disclosure relates to a solid-state image pickup element and an electronic apparatus.

Background

In recent years, solid-state image pickup elements such as CMOS (Complementary Metal Oxide Semiconductor) image sensors obtained by applying Semiconductor microfabrication technology are widely used for digital cameras, smart phones, and the like.

In such an image pickup element, incident light from a subject is photoelectrically converted in a photodiode provided in a pixel, a voltage signal corresponding to the amount of charge obtained as a result is read via an amplifying transistor and a vertical signal line, and the voltage signal is Analog-to-Digital (AD) converted by a comparator (for example, see patent document 1).

Incidentally, in the above-described image pickup element, due to the characteristics of the pixel, there is a parasitic capacitance between the nodes within the pixel, and there is also noise of the pixel power supply which propagates into the vertical signal line via the amplifying transistor, thus deteriorating the image quality, and then, a noise canceling circuit for canceling the noise of the pixel power supply has been provided.

The conventional noise canceling circuit described above is configured such that: noise of a pixel power supply is acquired, the acquired noise is converted into a current having appropriate gain and frequency characteristics, the current is caused to flow into an output resistor of a D/a converter for generating a RAMP wave (RAMP wave) to restore the current to a voltage, and the noise is cancelled in a differential pair (differential pair) of a comparator.

List of cited documents

Patent document

Patent document 1: japanese patent application laid-open No. JP 2015-233184A

Disclosure of Invention

Technical problem to be solved

However, in the case of employing an Ultra Low Voltage Comparator (ULVCM) as the Comparator, the input capacitance on the pixel side and the input capacitance on the D/A converter side are different, and the pixel signal and the output signal of the D/A converter are input to the same side of the differential pair, and therefore, there are problems as follows: a configuration in which noise is cancelled in a differential pair of comparators cannot be adopted as in the conventional case.

An object of the present disclosure is to provide a solid-state image pickup element and an electronic apparatus as follows: they can remove pixel power supply noise and reduce a switching error even when an ultra-low voltage comparator is employed as a comparator, thereby suppressing deterioration of image quality.

Solution to the problem

In order to achieve the above object, a solid-state image pickup element according to the present disclosure includes: a pixel; a noise removal signal generation circuit connected to a pixel power supply that supplies power to the pixels; a DA (Digital-to-Analog) converter; a comparator; a counter; and a gain control unit. The noise cancellation signal generation circuit is configured to: generating a first noise removal signal for removing power supply noise of the pixel power supply; and performing gain switching and polarity inversion on the first noise cancellation signal based on a gain control signal, thereby outputting a second noise cancellation signal. The DA converter is configured to: generating a reference signal and outputting the generated reference signal, the reference signal being a ramp signal; and converting the current of the second noise cancellation signal into a voltage to superimpose the converted voltage on the reference signal. With the comparator, the reference signal and the pixel signal are input to a main body portion of the comparator via an input capacitance connected to one terminal of a differential pair, and the comparator outputs an inverted signal having a timing corresponding to the pixel signal and a gain setting. The counter converts the inverted timing of the comparator into a digital value. The gain control unit outputs the gain control signal based on an amount of change in the input capacitance when changing a slope of the reference signal and the input capacitance to perform gain control of the comparator.

According to the present disclosure, the noise removal signal generation circuit generates a first noise removal signal for removing power supply noise of the pixel power supply, and performs gain switching and polarity inversion on the first noise removal signal based on the gain control signal to output it as a second noise removal signal to the DA converter.

The DA converter is configured to: a current output from a variable current source controlled with a digital value is caused to flow into an output resistor, thereby generating a ramp signal as a reference signal, and the generated reference signal is output to a comparator. The second noise removal signal is output to the DA converter as a current, and it flows into an output resistor of the DA converter to be converted into a voltage, and the converted voltage is superimposed on the ramp signal and then output to the comparator.

The reference signal and the pixel signal are input to the comparator main body portion via an input capacitance connected to one terminal of the differential pair, and the comparator outputs an inverted signal having a timing corresponding to the pixel signal and the gain setting.

The counter converts the inverted timing of the comparator into a digital value, and outputs the digital value.

Meanwhile, the gain control unit outputs a gain control signal based on the amount of change in the input capacitance to the noise cancellation signal generation circuit while changing the slope of the reference signal and the input capacitance to perform gain control of the comparator.

Drawings

Fig. 1 is a diagram showing an outline of a configuration example of a solid-state image pickup element according to an embodiment.

Fig. 2 is a diagram showing a circuit configuration example of an ULV (Ultra-Low Voltage) comparator.

Fig. 3 is a diagram showing a configuration example of a PSRR (Power Supply Rejection Ratio) correction circuit.

Fig. 4 is a graph showing a relationship between the gain of the single-slope AD converter and the amplitude of a ramp (ramp) signal.

Fig. 5 is a diagram showing a relationship between the input capacitance on the ramp signal side and the input capacitance on the pixel signal side and the gain of the single-slope AD converter.

Fig. 6 is a diagram illustrating one example of a plan view of the image pickup element.

Fig. 7 is a diagram showing a configuration example of an image pickup apparatus as one of other electronic apparatuses.

Fig. 8 is a diagram showing a configuration example of an image pickup device as still another electronic apparatus.

Detailed Description

Next, preferred embodiments will be described with reference to the accompanying drawings.

Fig. 1 is a diagram showing an outline of a configuration example of a solid-state image pickup element according to an embodiment.

As the solid-state image pickup element according to the embodiment, a CCD (Charge Coupled Device) image sensor, a CMOS image sensor, and the like are cited.

As shown in fig. 1, the solid-state image pickup element 10 includes a pixel 11, a PSRR (power supply rejection ratio) correction circuit 12, a DA converter 13, an ULV (ultra low voltage) comparator 14, a gain control unit 15, and a load MOS transistor 16.

In the above configuration, each pixel 11 is connected to the power supply unit PW, and a plurality of pixels 11 (for example, in the form of an N × M matrix, N and M being integers of 2 or more) are provided in the solid-state image pickup element 10 to constitute a pixel array unit. The pixel 11 photoelectrically converts incident light to generate a pixel signal corresponding to the received light amount of the incident light.

For example, as shown in fig. 1, each pixel 11 includes a photodiode 21, a transfer transistor 22, a floating diffusion region 23, an amplification transistor 24, a selection transistor 25, and a reset transistor 26.

Next, a detailed configuration of the pixel 11 will be explained.

The number of pixels 11 corresponds to the number of pixels (N × M in the above example) for constituting a pixel array unit provided in the image pickup element described later; however, only one of them is shown in fig. 1 for convenience of explanation.

In the pixel 11, the cathode terminal of the photodiode 21 is connected to the source terminal of the transfer transistor 22 constituted by an N-channel MOS transistor, and the drain terminal of the transfer transistor 22 is connected to the gate terminal of the amplification transistor 24 constituted by an N-channel MOS transistor. Further, a drain terminal of the reset transistor 26 composed of an N-channel MOS transistor is connected to the pixel power supply GPW, and a source terminal of the reset transistor 26 is connected to a gate terminal of the amplifying transistor 24.

In other words, the drain terminal of the transfer transistor 22 and the source terminal of the reset transistor 26 are commonly connected to the gate terminal of the amplification transistor 24.

Further, the drain terminal of the amplification transistor 24 is connected to the pixel power supply GPW, and the source terminal of the amplification transistor 24 is connected to the drain terminal of the selection transistor 25.

The source terminal of the selection transistor 25 is connected to the load MOS transistor 16 as a constant current source via a corresponding vertical signal line vsl (vertical signal line).

Here, the operation of the pixel 11 will be explained.

At the time of image capturing, light that has entered the solid-state image pickup element 10 is received by the photodiode 21 to be photoelectrically converted, and charges obtained by the conversion are accumulated in the photodiode 21. Next, when a voltage is applied to the gate of the transfer transistor 22 to bring the transfer transistor 22 into a closed state (on state), the photodiode 21 and the floating diffusion region 23 are electrically connected to each other, and the charge of the photodiode 21 is transferred to the floating diffusion region 23 via the transfer transistor 22, thereby generating a signal voltage at the gate of the amplifying transistor 24.

In this state, when a voltage is applied to the gate of the selection transistor 25 connected to the vertical signal line VSL and thus the selection transistor 25 is brought into a closed state (on state), the vertical signal VSL corresponding to the gate voltage of the amplification transistor 24 is supplied to the ULV comparator 14 via the amplification transistor 24, the selection transistor 25, and the vertical signal line VSL. Hereinafter, the reference numeral VSL indicating the vertical signal line is also used as a reference numeral indicating a pixel signal supplied from the vertical signal line to the ULV comparator 14.

Here, the pixel signal VSL output from the pixel 11 is an analog signal having a voltage corresponding to the magnitude of the received-light amount of the photodiode 21.

When a voltage is applied to the gate of the reset transistor 26 of the pixel 11 and thus the reset transistor 26 is brought into a closed state (on state), the voltage of the floating diffusion region 23 is returned to the power supply voltage, and the pixel signal VSL is brought into a reset state.

The PSRR correction circuit 12 includes a gain switching/inverting circuit 31, and the gain switching/inverting circuit 31 performs gain switching under the control of the gain control unit 15 and also performs amplification and polarity inversion on the noise cancellation signal.

Here, the reason why the PSRR correction circuit 12 is provided will be explained.

In the solid-state image pickup element 10, power supply noise from the pixel power supply GPW propagates to the vertical signal line VSL via a parasitic capacitance (not shown) between nodes in the pixel, the amplification transistor 24, and the selection transistor 25.

Therefore, the above-mentioned power supply noise is superimposed on the pixel signal VSL output from the pixel 11 and then input to the ULV comparator 14, and therefore the output inversion timing of the ULV comparator 14 is shifted, and there is a possibility that a correct pixel value cannot be obtained. Therefore, the PSRR correction circuit 12 is provided to cancel (correct) power supply noise input to the ULV comparator 14, thereby obtaining a correct pixel value.

The details of the configuration of the gain switching/inverting circuit 31 will be described later.

The DA converter 13 includes: a variable current source 35 controlled by a digital value; and an output resistor 36 connected in series with the variable current source 35.

The output of the DA converter 13 in which the variable current source 35 is controlled with a Digital value is a ramp signal whose signal level changes with time, and it is used as a reference signal for Analog-to-Digital (a/D) conversion of a pixel signal output from the pixel 11.

In the above configuration, the DA converter 13, the ULV comparator 14, and the counter 18 function as the single slope AD converter 17 that converts the pixel signal VSL output from the pixel 11 from an analog signal to a digital signal.

Next, the ULV comparator 14 will be explained.

Fig. 2 is a diagram showing a circuit configuration example of the ULV comparator.

The ULV comparator 14 roughly includes an input capacitance variable unit 41, a comparator body portion 42, and a reference voltage holding capacitor 43. The input capacitance variable unit 41 includes: a pixel signal input terminal TTV to which a pixel signal VSL output from the corresponding pixel 11 is input; and a reference signal input terminal TTR to which the RAMP signal RAMP output from the DA converter 13 is input.

The ULV comparator 14 outputs an inverted signal having a timing corresponding to the pixel signal level and the gain setting based on the pixel signal VSL input via the pixel signal input terminal TTV and the RAMP signal RAMP input via the reference signal input terminal TTR. The counter 18 converts the inversion timing into a digital value to perform AD conversion. In the image data processing unit PRC of the subsequent stage, various digital processes are performed on the pixel data AD-converted by the ULV comparator 14.

The input capacitance variable unit 41 includes: a capacitor C0 having one end connected to the pixel signal input terminal TTV and the other end connected to the pixel side input terminal TIN of the comparator main body portion 42; a capacitor C1 having one end connected to the reference signal input terminal TTR and the other end connected to the pixel-side input terminal TIN of the comparator main body portion 42; a switch SW1 having one end connected to the reference signal input terminal TTR; a switch SW2 connected in series to the switch SW 1; a switch SW3 connected in series to the switch SW 2; a switch SW4 connected in series to the switch SW 3; a switch SW5 having one end connected to the switch SW4 and the other end connected to a connection point between the pixel signal input terminal TTV and the capacitor C0; a capacitor C2 connected between the pixel-side input terminal TIN and a connection point between the switch SW1 and the switch SW 2; a capacitor C3 connected between the pixel-side input terminal TIN and a connection point between the switch SW2 and the switch SW 3; a capacitor C4 connected between the pixel-side input terminal TIN and a connection point between the switch SW3 and the switch SW 4; and a capacitor C5 connected between the pixel-side input terminal TIN and a connection point between the switch SW4 and the switch SW 5.

In the above configuration, for example, the capacitors C1 to C5 have the same capacitance, and it is assumed that the capacitance of the capacitor C0 is a capacitance obtained by connecting in parallel a plurality of unit capacitances each corresponding to one of the capacitors C1 to C5. The number of capacitors C2 to C5 connected via switches and the number of parallel connections of unit capacitances in the capacitor C0 may vary depending on specifications.

The comparator body portion 42 includes: a current mirror circuit composed of a pair of transistors T11 and T12, which performs control so that the amount of current flowing through the pixel-side current line LG is equal to the amount of current flowing through the reference-side current line LR; a pair of transistors T21 and T22 constituting a differential pair; a first reset switch SW11 capable of short-circuiting between the drain terminal and the gate terminal of the transistor T21 to perform reset; a second reset switch SW12 capable of short-circuiting between the drain terminal and the gate terminal of the transistor T22 to perform reset; and a current source transistor T23, one terminal of which is connected to both the source terminal of transistor T21 and the source terminal of transistor T22, and the source terminal of which is grounded. The comparator body portion 42 may have a multi-stage structure as follows: which contains one or more sections of a back-end amplifier (not shown) in the back-end of the differential amplifier configuration shown in fig. 2.

In performing gain control, the gain control unit 15 outputs a gain control signal GC2 and a gain control signal GC3 so as to switch the slope of the RAMP signal RAMP output from the DA converter 13 and the input capacitance in the input capacitance variable unit 41 of the ULV comparator 14. Further, the gain control unit 15 also outputs a gain control signal GC1, and controls (switches) the gain of the PSRR correction circuit for absorbing the influence due to the switching of the input capacitance in conjunction with the switching of the input capacitance in the input capacitance variable unit 41 so as to reliably cancel the noise of the pixel power supply.

Next, details of the configuration of the PSRR correction circuit 12 will be explained.

Fig. 3 is a diagram showing a configuration example of the PSRR correction circuit.

In the present embodiment, the PSRR correction circuit can adopt the configuration shown in fig. 3, which enables low power consumption and accurate noise correction.

As shown in fig. 3, the PSRR correction circuit 12 includes a conductance-fixed bias unit 51, a bias unit 52, an input sensing unit 53, a delay phase adjustment unit 54, a lead phase adjustment unit 55, a transistor 56, a gain switching/inverting circuit 31, a gain adjustment unit 58, and a pixel power supply input terminal (noise monitor terminal) 59. The PSRR correction circuit having the same characteristics may take various forms (configurations), and thus specific circuits before/after the gain switching/inverting circuit 31 may have configurations different from those shown in fig. 3.

The conductance fixed bias unit 51 includes: a first current mirror circuit 63 including an N-channel MOS transistor 61 and an N-channel MOS transistor 62; a second current mirror circuit 66 including a P-channel MOS transistor 64 and a P-channel MOS transistor 65; and a pull-up resistor 67. The conductive fixed bias unit 51 is used to apply a fixed bias voltage (fixed bias voltage) to the bias unit 52, the input sensing unit 53, and the gain switching/inverting circuit 31.

In the above configuration, the current amount of the N-channel MOS transistor 62 is m times the current amount of the N-channel MOS transistor 61. A gate terminal of N-channel MOS transistor 61 and a gate terminal of N-channel MOS transistor 62 are connected to each other.

The source terminal of N-channel MOS transistor 61 is grounded, and the drain terminal of N-channel MOS transistor 61 is connected to the gate terminal of N-channel MOS transistor 61. On the other hand, the source terminal of N-channel MOS transistor 62 is grounded via pull-up resistor 67.

The size of P-channel MOS transistor 64 and the size of P-channel MOS transistor 65 are the same as each other. Further, a gate terminal of P-channel MOS transistor 65 is connected to a gate terminal of P-channel MOS transistor 64.

The source terminal of P-channel MOS transistor 64 is connected to power supply V_DDHAnd a drain terminal of P-channel MOS transistor 64 is connected to a drain terminal of N-channel MOS transistor 61. In this case, the power supply V_DDHMay be a pixel power supply or may be a power supply other than a pixel power supply.

The source terminal of P-channel MOS transistor 65 is connected to power supply V_DDHAnd a drain terminal of P-channel MOS transistor 65 is connected to a drain terminal of N-channel MOS transistor 62. The drain terminal of P-channel MOS transistor 65 is also connected to the gate terminal of P-channel MOS transistor 65.

In the conductance fixed bias unit 51 having the above-described configuration, the conductance of the N-channel MOS transistor 61 is constant, and the conductance is a constant value determined by the value of m, which is the ratio of the number of parallel connections between the N-channel MOS transistor 61 and the N-channel MOS transistor 62, and the resistance value of the pull-up resistor 67.

The bias unit 52 includes a P-channel MOS transistor 71, a switch SW21, and a capacitor (capacitive element) C11.

The drain terminal of the P-channel MOS transistor 71 is connected to a power supply V_DDHAnd the gate terminal of the P-channel MOS transistor 71 is connected to the power supply V via the capacitor C11_DDH。

Further, the gate terminal of the P-channel MOS transistor 71 is connected to the gate terminals of the P-channel MOS transistors 64 and 65 in the conductance fixed bias unit 51 via a switch SW 21.

In the above-described bias unit 52, the P-channel MOS transistor 71 functions as a current source, and a current that makes the conductance of the N-channel MOS transistor 72 in the input sensing unit 53 constant flows all the time from the drain terminal of the P-channel MOS transistor 71 to the common connection point of the drain terminal of the N-channel MOS transistor 72 and the P-channel MOS transistor 56.

The input sensing unit 53 includes an N-channel MOS transistor 72, a switch SW23, and a capacitor (capacitive element) C12.

The source terminal of the N-channel MOS transistor 72 is grounded, and the gate terminal of the N-channel MOS transistor 72 is connected to the pixel power supply input terminal via the capacitor C12.

Further, the gate terminal of the N-channel MOS transistor 72 is connected to the gate terminals of the N-channel MOS transistors 61 and 62 in the conductance fixed bias unit 51 via a switch SW23 used when holding is employed.

A drain terminal of the N-channel MOS transistor 72 is connected to the bias unit 52 and the delay phase adjusting unit 54. Also, the drain terminal of N-channel MOS transistor 72 is also connected to the gate terminal of P-channel MOS transistor 56.

In the input sensing unit 53 having the above-described configuration, for example, in a period in which noise elimination and thus power supply noise correction are not performed, the switch SW23 is changed to a closed state (on state), thereby determining the operating point of the gate terminal of the N-channel MOS transistor 72. In other words, in this state, in the N-channel MOS transistor 72, a current corresponding to the current flowing through the N-channel MOS transistor 61 in the conductance fixed bias unit 51 flows.

Further, in a period in which noise cancellation is performed, in other words, in a period in which the noise cancellation signal XNC1 is superimposed on the RAMP signal RAMP as the reference signal to perform power supply noise correction, the switch SW23 is put in an on state (off state).

As a result, the AC component of the power supply noise detected at the pixel power supply input terminal 59 is extracted by the capacitor C12 as a high-pass filter so as to be input to the gate terminal of the N-channel MOS transistor 72.

Further, in the N-channel MOS transistor 72, a current including an AC component corresponding to an AC (alternating current) component of pixel power supply noise included in the pixel power supply and including a DC component determined by the N-channel MOS transistor 61 flows as a noise cancel signal NC0, and power supply noise as a voltage signal is converted into a noise cancel signal NC0 as a current signal.

As described above, the conductance of N-channel MOS transistor 61 is always constant (fixed), and therefore the conductance of N-channel MOS transistor 72 is also constant.

Therefore, fluctuations in the gain Δ Id/Δ Vin of the voltage-current conversion can be suppressed, so it is not necessary to provide a pull-up resistor between the N-channel MOS transistor 72 and the ground, so the gain at the time of the voltage-current conversion (Δ Id/Δ Vin) can be increased, whereby low power consumption and low noise of the input sensing unit 53 can be realized.

As described above, a current for making the conductance of the N-channel MOS transistor 72 in the input sensing unit 53 constant flows all the time from the drain terminal of the P-channel MOS transistor 71 to the common connection point of the drain terminal of the N-channel MOS transistor 72 and the P-channel MOS transistor 56.

Therefore, the current flowing through P-channel MOS transistor 56 side is: a current flowing from the P-channel MOS transistor 71 of the bias unit 52 to the common connection point of the drain terminal of the N-channel MOS transistor 72 and the P-channel MOS transistor 56 is subtracted from the noise cancel signal NC0 flowing in the N-channel MOS transistor 72 of the input sensing unit 53, thereby obtaining a current.

In other words, the current flowing on the P-channel MOS transistor 56 side is a noise cancellation signal NC1 (equivalent to the first noise cancellation signal) obtained by removing a part of the DC component from the noise cancellation signal NC0 with the bias unit 52.

Further, in the bias unit 52, the switch SW21 is in a closed state (on state) in a period in which noise cancellation is not performed, and the switch SW21 is in an open state (off state) in a period in which noise cancellation is performed.

By this, when the switch SW21 is brought into an open state (off state) in the period of time in which noise cancellation is performed as described above, the output noise of the conductance-fixing bias unit 51 is output to the common connection point of the drain terminal of the N-channel MOS transistor 72 and the P-channel MOS transistor 56 via the P-channel MOS transistor 71, and thus it is possible to prevent the output noise from being superimposed on the noise cancellation signal NC 1. Further, in some cases, the switch SW21 need not be provided.

The delay phase adjusting unit 54 includes: a variable capacitance capacitor C13 located at the power supply V_DDHAnd the common connection point of the drain terminal of N-channel MOS transistor 72 and P-channel MOS transistor 56.

Delay phase adjusting section 54 adjusts the delay phase of the high frequency component in the current (i.e., noise cancel signal) flowing from P-channel MOS transistor 56 to the common connection point of the drain terminal of N-channel MOS transistor 72 and P-channel MOS transistor 56.

In other words, the variable capacitance capacitor C13 of the delay phase adjusting unit 54 functions as a low-pass filter, and attenuates (the gain of) the AC component of the noise cancel signal, so as to perform phase adjustment, that is, perform adjustment of the delay phase. In this case, the cutoff frequency of the low-pass filter is determined by the capacitance of the variable capacitance capacitor C13 and the resistance component of the P-channel MOS transistor 56.

The leading phase adjusting unit 55 includes: and a variable capacitance capacitor C14 connected between the pixel power supply input terminal 59 and the gain switching/inverting circuit 31.

The leading phase adjusting unit 55 adjusts the leading phase in the high frequency region in the current flowing from the common connection point of the drain terminal of the N-channel MOS transistor 72 and the P-channel MOS transistor 56 to the gain switching/inverting circuit 31 (i.e., the noise cancellation signal NC 1).

In the leading phase adjusting unit 55, the gain switching/inverting circuit 31 and the pixel power supply are connected via the variable capacitance capacitor C14, thereby causing the high-pass component to propagate into the gain switching/inverting circuit 31.

In other words, the variable capacitance capacitor C14 of the leading phase adjusting unit 55 functions as a high-pass filter, and the high-frequency component of the pixel power supply noise is superimposed on the gain switching/inverting circuit 31 so as to perform phase adjustment, that is, adjustment of the leading phase. In this case, the cutoff frequency as a high-pass filter is determined by the capacitance of the variable capacitance capacitor C14 and the apparent resistance value of the gain switching/inverting circuit 31.

Gain switching/invertingThe circuit 31 includes: a P-channel MOS transistor group 73G composed of a plurality of P-channel MOS transistors 73 connected in parallel to each other, in which their gate terminals are commonly connected to the gate terminal of the P-channel MOS transistor 56, and their source terminals are commonly connected to the power supply V_DDHAnd their drain terminals are commonly connected to the variable capacitance capacitor C14 of the leading phase adjusting unit 55.

Further, the gain switching/inverting circuit 31 further includes: a P-channel MOS transistor group 74G composed of a plurality of P-channel MOS transistors 74 connected in parallel with each other, wherein their source terminals are commonly connected to a power supply V_DDHAnd their drain terminals are commonly connected to the commonly connected drain terminals of the P-channel MOS transistor group 73G, and their gate terminals are commonly connected to their drain terminals via a connection number of changeover switches (not shown).

Further, the gain switching/inverting circuit 31 further includes: an N-channel MOS transistor group 75G; and a capacitor C15. Here, the N-channel MOS transistor group 75G functions as a current source and is constituted by a plurality of N-channel MOS transistors 75 connected in parallel to each other, their drain terminals are connected to a common connection point between the commonly connected drain terminal of the P-channel MOS transistor group 73G and the commonly connected drain terminal of the P-channel MOS transistor group 74G, while their source terminals are commonly grounded, and their commonly connected gate terminals are connected to the gate terminal of the N-channel MOS transistor 61 of the conductance fixed bias unit 51 via a switch SW 22. Capacitor C15 has one end connected to the commonly connected gate terminal of N-channel MOS transistor group 75G, and the other end grounded.

In the above configuration, the number of P-channel MOS transistors 73 to be actually operated (the number of parallel connections of the P-channel MOS transistors 73) among a plurality of P-channel MOS transistors 73 which constitute the P-channel MOS transistor group 73G and are connected in parallel to each other, the number of P-channel MOS transistors 74 to be actually operated (the number of parallel connections of the P-channel MOS transistors 74) among a plurality of P-channel MOS transistors 74 which constitute the P-channel MOS transistor group 74G and are connected in parallel to each other, and the number of N-channel MOS transistors 75 to be actually operated (the number of parallel connections of the N-channel MOS transistors 75) among the plurality of N-channel MOS transistors 75 which constitute the N-channel MOS transistor group 75G and are connected in parallel to each other may be switched in conjunction with switching of an input capacitance of the ULV comparator described later, so that gain switching of the PSRR correction circuit 12 can be effectively performed.

Details of the gain switching/inverting circuit 31 will be described later.

Note that the configuration of the gain switching/inverting circuit 31 is only one example, and other circuits having a polarity inverting function of a waveform and a gain switching function may be equally applied.

The gain adjustment unit 58 includes: a P-channel MOS transistor group 76G composed of P-channel MOS transistors 76 connected in parallel with each other, wherein gate terminals of a plurality of P-channel MOS transistors 76 connected in parallel with each other are commonly connected to commonly connected gate terminals of a plurality of P-channel MOS transistors 74 constituting the P-channel MOS transistor group 74G and connected in parallel with each other via a connection number of change-over switches (not shown). In the P-channel MOS transistor group 76G, their source terminals are commonly connected to a power supply V_DDHAnd their drain terminals are commonly connected to a connection point between the variable current source 35 and the output resistor 36 in the DA converter 13.

Here, the gain adjustment unit 58 adjusts the number of parallel connections of P-channel MOS transistors to be actually driven (changes the number of outputs of a multi-output current mirror formed in cooperation with the P-channel MOS transistor group 74G) in the ULV comparator 14 so that the noise signal and the noise cancellation signal are appropriately cancelled out by each other, thereby performing fine adjustment of the gain in accordance with the amplitude of the power supply noise signal.

Here, the operation of the gain switching/inverting circuit 31 will be explained.

Since the P-channel MOS transistor group 73G in the gain switching/inverting circuit 31 functions as a multi-output current mirror circuit in cooperation with the P-channel MOS transistor 56, currents (currents having the same polarity and having a size ratio corresponding to a transistor size ratio) proportional to currents flowing through the P-channel MOS transistor 56 by the noise cancel signal NC1 flow between the source terminal and the drain terminal of each P-channel MOS transistor 73 constituting the P-channel MOS transistor group 73G.

In this case, the sum of the current flowing between the source terminals and the drain terminals of the plurality of P-channel MOS transistors 73 that constitute the P-channel MOS transistor group 73G and that actually operate and the current flowing between the source terminals and the drain terminals of the plurality of P-channel MOS transistors 74 that constitute the P-channel MOS transistor group 74G and that actually operate is equal to the current flowing between the drain terminals and the source terminals of the plurality of N-channel MOS transistors 75 that constitute the N-channel MOS transistor group 75G and that actually operate as a current source.

Therefore, the current flowing through the P-channel MOS transistor group 74G is equal to a current obtained by subtracting the current flowing through the P-channel MOS transistor group 73G from the current flowing through the N-channel MOS transistor group 75G.

In other words, the current flowing through the P-channel MOS transistor group 74G has an opposite polarity with respect to the current flowing through the P-channel MOS transistor group 73G corresponding to the noise cancel signal NC 1.

The noise canceling signal whose gain is switched and whose polarity is inverted (hereinafter, may be referred to as a noise canceling signal XNC1 of opposite polarity, and is equivalent to a second noise canceling signal) is supplied to the DA converter 13 as a final noise canceling signal.

Next, the operation of the solid-state image pickup element as a whole will be described.

When performing gain control, the gain control unit 15 of the solid-state image pickup element 10 switches both the slope of the RAMP signal RAMP, which is the reference signal output from the DA converter, and the input capacitance of the input capacitance variable unit 41 of the ULV comparator 14.

Incidentally, in the ULV comparator 14, the input capacitance of the pixel signal VSL and the input capacitance of the RAMP signal RAMP are arranged on the same side in the differential pair, but because of the presence of the input capacitance on the RAMP signal RAMP side, the amount of attenuation reaching the differential pair from the pixel signal VSL becomes larger than that of the conventional comparator due to the capacitance voltage division. As a result, there is a problem that noise of the transistor becomes large with respect to the pixel signal VSL in practical use.

Therefore, by reducing the input capacitance on the RAMP signal RAMP side and increasing the amplitude of the RAMP signal RAMP, it is possible to reduce the amount of attenuation of the pixel signal VSL reaching the differential pair while maintaining the output result of the single-slope AD converter 17 (DA converter 13+ ULV comparator 14+ counter 18), and further suppress the deterioration of noise.

However, when the gain of the single-slope AD converter 17 is low, the amplitude of the RAMP signal RAMP is inherently large, and thus the input capacitance on the RAMP signal RAMP side cannot be reduced.

When the gain of the single-slope AD converter 17 is low (see the left side of fig. 5), the gain control unit 15 increases the input capacitance C _ RAMP on the RAMP signal RAMP side and decreases the input capacitance C _ VSL on the pixel signal VSL side as shown in fig. 5.

On the other hand, when the gain of the single slope AD converter 17 is high (see the right side of fig. 5), the gain control unit 15 decreases the input capacitance on the RAMP signal RAMP side and increases the input capacitance on the pixel signal VSL side.

As a result, as the gain is reduced from the high gain state, the input capacitance C _ RAMP on the RAMP signal RAMP side increases in stages, and the input capacitance C _ VSL on the pixel signal VSL side decreases in stages.

Fig. 4 is a graph showing the relationship between the gain of the single-slope AD converter and the amplitude of the ramp signal.

Fig. 5 is a diagram showing a relationship between the input capacitance on the ramp signal side and the input capacitance on the pixel signal side and the gain of the single-slope AD converter.

Note that when the gain of the single-slope AD converter 17 is in an extremely low situation, although the noise cancellation effect may be reduced, noise can be suppressed by performing band adjustment or the like.

As described above, the gain control unit 15 sets the control signal of each unit according to the gain setting of the single-slope AD converter 17, and switches the input capacitance in stages, and also thereby switches the amplitude of the RAMP signal RAMP to suppress the deterioration of noise to a minimum.

Also, the gain control unit 15 simultaneously controls the gain switching/inverting circuit 31 of the PSRR correction circuit 12 so as to switch the gain of the PSRR correction circuit in accordance with the switching of the capacitance (input capacitance) of the input capacitance variable unit 41 in the ULV comparator 14.

More specifically, the gain control unit 15 controls the gain switching/inverting circuit 31 so as to control the number of P-channel MOS transistors 73 that are connected in parallel with each other and actually driven, among the plurality of P-channel MOS transistors 73 of the P-channel MOS transistor group 73G for constituting the gain switching/inverting circuit 31.

Similarly, the number of P-channel MOS transistors 74 connected in parallel with each other and actually driven among a plurality of P-channel MOS transistors 74 constituting a P-channel MOS transistor group 74G is controlled, and the number of N-channel MOS transistors 75 connected in parallel with each other and actually driven among a plurality of N-channel MOS transistors 75 constituting an N-channel MOS transistor group 75G is controlled.

In this case, the sum of the current flowing between the source terminals and the drain terminals of the plurality of P-channel MOS transistors 73 that constitute the P-channel MOS transistor group 73G and that actually operate and the current flowing between the source terminals and the drain terminals of the plurality of P-channel MOS transistors 74 that constitute the P-channel MOS transistor group 74G and that actually operate is equal to the current flowing between the drain terminals and the source terminals of the plurality of N-channel MOS transistors 75 that constitute the N-channel MOS transistor group 75G and that actually operate.

Also, at the time of AD conversion of the pixel signal VSL, the PSRR correction circuit 12 monitors occurrence of power supply noise in the pixel power supply GPW, and generates a noise removal signal XNC1 for removing (correcting) the power supply noise based on the power supply noise generated by the pixel power supply GPW to output the generated noise removal signal XNC1 to the DA converter 13.

On the other hand, the DA converter 13 generates a RAMP signal RAMP having a waveform (voltage value) that changes in a RAMP-like manner with time as a reference signal, and the generated reference signal is output to the ULV comparator 14.

Therefore, the RAMP signal RAMP output from the DA converter 13 includes the noise removal signal XNC1 having an opposite polarity with respect to the noise signal of the pixel power supply.

In other words, the PSRR correction circuit 12 inputs the generated noise removal signal XNC1 to the ULV comparator 14 via the DA converter 13 to cause the ULV comparator 14 to remove the power supply noise. Therefore, when the reference signal (i.e., the RAMP signal RAMP) on which the noise cancellation signal XNC1 is superimposed is input to the ULV comparator 14, the power supply noise of the pixel power supply GPW superimposed on the pixel signal VSL is cancelled by the noise cancellation signal XNC1 when the RAMP signal RAMP is compared with the pixel signal VSL transmitted from the pixel 11.

As a result, the single-slope AD converter 17 effectively outputs the a/D conversion result of the pixel signal VSL (after canceling the noise of the pixel power supply) as a digital pixel signal.

Therefore, in the solid-state image pickup element 10, even in the case where power supply noise from the pixel power supply is propagated to the vertical signal line VSL via the parasitic capacitance between the nodes within the pixel, the amplifying transistor 24, and the selection transistor 25, and the power supply noise is superimposed on the pixel signal output from the pixel 11 and then input to the ULV comparator 14, the inversion timing of the output from the ULV comparator 14 does not shift, and thus a pixel signal having a correct pixel value can be obtained.

According to the solid-state image pickup element 10 as described above, power supply noise can be eliminated with high accuracy by a simpler configuration, whereby a higher quality image can be obtained. Further, according to the solid-state image pickup element 10, low power consumption can be achieved.

< construction example of image pickup element >

Fig. 6 is a diagram illustrating one example of a plan view of the image pickup element.

Although the plan view of the image pickup element may be considered in many ways, in the figure, the pixel array unit 81 provided with a plurality of pixels 11 is disposed on the upper chip uc (upper chip).

The lower chip lc (lower chip) includes, in addition to the PSRR correction circuit 12, the DA converter 13, the ULV comparator 14, the gain control unit 15, and the load MOS transistor 16 described above: a pixel control circuit 82 for performing readout control and the like for the pixel array unit 81; a logic block 83 including a gain control unit 15 and an MPU (micro processor unit), and configured to execute various controls and image processing for the entire solid-state image pickup element 10; and an interface unit 84 that performs various interface operations.

In the above configuration, it is necessary to cause a current corresponding to the noise cancel signal XNC1 to flow into the output resistor 36 configuring the DA converter 13, so in order to reduce the influence of noise mixing or frequency characteristic variation due to an increase in the wiring length, it is preferable to arrange the PSRR correction circuit 12 adjacent to the DA converter 13.

A plurality of ULV comparators 14 for constituting the single slope AD converter 17 are respectively arranged at the upper and lower portions of the lower chip LC as shown in fig. 6, and the pixel signals VSL are respectively input to the ULV comparators 14 from the respective pixels 11 for constituting the pixel array unit 81 in the upper chip UC, and therefore, it is preferable that the DA converter 13 which has to supply the RAMP signal RAMP to the plurality of ULV comparators 14 is arranged in the central portion of the lower chip.

< example of configuration of image pickup apparatus >

Further, the present technology can be generally applied to all electronic apparatuses using an image pickup element for a photoelectric conversion unit such as: an image pickup device such as a digital camera or a video camera; a portable terminal device having an image pickup function; an image pickup device is used in a copying machine or the like of an image reading unit.

Fig. 7 is a diagram showing a configuration example of an image pickup apparatus as one of other electronic apparatuses.

The image pickup device 90 includes: an optical system 91 having a lens group and the like; a solid-state image pickup element 10; a Digital Signal Processor (DSP) 92 as a Signal processing circuit for processing the captured data; a display 93, which is configured by a liquid crystal display, an organic Electroluminescence (EL) display, or the like, for displaying a photographed image and various information; an operation unit 94 through which a user performs various operations such as an image pickup instruction and data setting; a controller 95 that executes overall control of the imaging device 90; a frame memory 96 for storing image data; a recording unit 97 that performs recording of captured data on a recording medium (not shown) such as a hard disk, a memory card, or the like; and a power supply unit 98 that supplies power to the entire image pickup device 90.

In the above configuration, the DSP 92, the display 93, the operation unit 94, the controller 95, the frame memory 96, the recording unit 97, and the power supply unit 98 are connected to each other via a bus.

According to the above configuration, since the above solid-state image pickup element 10 is used as an image pickup element, a clear and high-quality image with little noise can be captured for a long time with low power consumption.

As a practical aspect of the imaging device 90, a video camera, a digital camera, a camera module used for a mobile terminal device such as a smartphone, and the like can be cited.

Fig. 8 is a diagram showing a configuration example of an image pickup device as still another electronic apparatus.

The image pickup apparatus 100 includes: an optical system 101 having a lens group and the like; a solid-state image pickup element 10; a DSP (digital signal processor) 102 as a signal processing circuit for processing captured data; an interface unit 103 that performs an interface operation with the external device 110; and a frame memory 104 for storing image data.

The image pickup apparatus 100 of such a kind is configured to perform photographing under the control of the external device 110 with the power supplied from the external device 110, and can be applied to, for example, a camera module or the like as follows: the camera module or the like receives power supply from the vehicle side and captures a monitoring image of the surroundings of the vehicle under control of an in-vehicle ECU (electronic control unit) or the like as the external device 110.

In this case, the external device 110 includes: an interface unit 111 that performs an interface operation with the image pickup apparatus 100; an image processing unit 112 that performs image processing on the captured data acquired via the interface unit 111 to perform image processing for obtaining desired image data (e.g., a peripheral obstacle image, a marker recognition image, etc.); a power supply unit 113 that supplies operating power to the image pickup apparatus 100 and the external device 110; an external controller 114 that controls the image pickup apparatus 100 via the interface unit 111; and a recording unit 115 that performs recording of captured data on a recording medium (not shown) such as a hard disk, a memory card, or the like.

Examples of applications of the imaging device 100 include: in order to ensure safe driving such as automatic parking, and to recognize the state of the driver, etc., an in-vehicle sensor that is disposed at the outer peripheral surface (front, side, rear) of an automobile or in the vehicle compartment so as to photograph the surroundings of the vehicle or the interior of the vehicle; a monitoring camera for remotely monitoring a vehicle or a road in motion; and a distance measuring device.

Note that it is applicable to an image pickup apparatus: it uses a body of a home appliance (an air conditioner, a refrigerator, a microwave oven, etc.) as an external device 110, detects a position, an action (gesture), etc. of a user, and performs control accordingly.

Further, the present invention can be applied to personal authentication, skin imaging, and the like.

The above description has been directed to the case where an image corresponding to visible light is captured; however, it can be applied to an imaging apparatus for infrared rays, ultraviolet rays, X-rays, and the like.

The effects described in this specification are merely illustrative or exemplary and not restrictive. In other words, the technique according to the present disclosure can exert other effects.

The following technical solutions also belong to the technical scope of the present disclosure.

(1) A solid-state image pickup element comprising:

a pixel that outputs a pixel signal;

a noise cancellation signal generation circuit connected to a pixel power supply that supplies power to the pixels, the noise cancellation signal generation circuit being configured to:

generating a first noise removal signal for removing power supply noise of the pixel power supply; and is

Performing gain switching and polarity inversion on the first noise cancellation signal based on a gain control signal, thereby outputting a second noise cancellation signal;

a DA (digital-to-analog) converter configured to:

generating a reference signal and outputting the generated reference signal, the reference signal being a ramp signal; and is

Converting the current of the second noise cancellation signal into a voltage to superimpose the converted voltage on the reference signal;

a comparator to which the reference signal and the pixel signal are input via an input capacitance connected to one terminal of a differential pair and which outputs an inverted signal having a timing corresponding to the pixel signal and a gain setting;

a counter that converts an inverted timing of the comparator into a digital value; and

a gain control unit that outputs the gain control signal based on an amount of change in the input capacitance when changing a slope of the reference signal and the input capacitance to perform gain control of the comparator.

(2) The solid-state image pickup element according to (1), wherein,

the comparator includes an input capacitance switching unit including:

a first capacitor connected between an input terminal and the one terminal of the differential pair;

a plurality of second capacitors each having one end connected to the one terminal of the differential pair; and

a plurality of switches for connecting the second capacitor and the first capacitor in parallel with each other.

(3) The solid-state image pickup element according to (1) or (2), wherein,

the noise cancellation signal generation circuit includes:

a pixel power supply input unit connected to the pixel power supply;

a first noise removal signal generation unit that converts a pixel power supply voltage input via the pixel power supply input unit into a current to generate the first noise removal signal; and

a gain switching/inverting circuit that performs gain switching and polarity inversion on the first noise cancellation signal based on the gain control signal.

(4) The solid-state image pickup element according to (3), wherein,

the gain switching/inverting circuit includes:

a first transistor group including a plurality of transistors connected in parallel to each other and capable of flowing a current amount proportional to a current amount of the first noise cancellation signal;

a second transistor group including a plurality of transistors connected in parallel with each other, connected in series with the first transistor group, and capable of flowing a predetermined constant current; and

a third transistor group connected in parallel with the first transistor group and capable of outputting the second noise cancellation signal.

(5) The solid-state image pickup element according to (4), further comprising:

a fourth transistor group that constitutes a current mirror circuit together with the third transistor group and that is capable of adjusting a gain of the second noise cancel signal to output the adjusted gain.

(6) The solid-state image pickup element according to any one of (3) to (5),

the gain switching/inverting circuit and the DA converter are disposed adjacent or near to each other.

(7) The solid-state image pickup element according to any one of (1) to (6),

the comparator is arranged in a peripheral portion of the chip, and

the DA converter is disposed in a central portion of the chip.

(8) An electronic device, comprising:

a pixel array unit in which a plurality of pixels each outputting a pixel signal are arranged in an array;

a noise cancellation signal generation circuit connected to a pixel power supply that supplies power to the pixels, the noise cancellation signal generation circuit being configured to:

generating a first noise removal signal for removing power supply noise of the pixel power supply; and is

Performing gain switching and polarity inversion on the first noise cancellation signal based on a gain control signal, thereby outputting a second noise cancellation signal;

a DA (digital-to-analog) converter configured to:

generating a reference signal and outputting the generated reference signal, the reference signal being a ramp signal; and is

Converting the current of the second noise cancellation signal into a voltage to superimpose the converted voltage on the reference signal;

a comparator to which the reference signal and the pixel signal are input via an input capacitance connected to one terminal of a differential pair and which outputs an inverted signal having a timing corresponding to the pixel signal and a gain setting;

a counter that converts an inverted timing of the comparator into a digital value;

a gain control unit that outputs the gain control signal based on an amount of change in an input capacitance when changing a slope of the reference signal and the input capacitance to perform gain control of the comparator; and

an image data processing unit that processes image data based on an output of the counter.

List of reference numerals

10 solid-state image pickup element

11 pixels

12 PSRR correction circuit

13 DA converter

14 ULV comparator

15 gain control unit

16 load MOS transistor

17 single slope AD converter

18 counter

21 photodiode

22 pass transistor

23 floating diffusion region

24 amplifying transistor

25 select transistor

31 gain switching/inverting circuit

35 variable current source

36 output resistor

41 input capacitance variable unit

42 comparator body part

43 reference voltage holding capacitor

51-conductance fixed bias unit

52 bias unit

53 input sensing unit

54 delay phase adjusting unit

55 leading phase adjusting unit

56P channel MOS transistor

58 gain adjustment unit

59 pixel power supply input terminal

73P-channel MOS transistor

73G P channel MOS transistor group

74P channel MOS transistor

74G P channel MOS transistor group

75N-channel MOS transistor

75G N channel MOS transistor group

76P channel MOS transistor

76G P channel MOS transistor group

C11, C12, C15 capacitor

C13, C14 variable capacitance capacitor

GC 1-GC 3 gain control signals

GPW pixel power supply

LC lower chip

LG pixel side current line

LR reference side current line

NC0 noise cancellation signal

NC1 noise cancellation signal (first noise cancellation signal)

PRC image data processing unit

PW power supply unit

RAMP signal

SW 1-SW 5 switches

TIN pixel side input terminal

TTR reference signal input terminal

TTV pixel signal input terminal

UC chip

VSL vertical signal line, pixel signal

XNC1 noise cancellation signal of opposite polarity (second noise cancellation signal)