Preparation method and structure of split gate SiC VDMOS device with source field plate
阅读说明：本技术 具有源场板的分裂栅SiC VDMOS器件的制备方法及结构 (Preparation method and structure of split gate SiC VDMOS device with source field plate ) 是由 赵伟 魏敬和 刘国柱 聂晓飞 魏应强 于宗光 于 2020-12-24 设计创作，主要内容包括：本发明公开一种具有源场板的分裂栅SiC VDMOS器件的制备方法及结构,属于半导体器件及制造领域。提供N+SiC衬底,在其表面形成N-SiC外延层；在N-SiC外延层中依次形成P阱区、N+区和P+区；通过高温氧化在表面形成栅氧化层,并在栅氧化层上沉积金属或多晶硅,刻蚀形成栅极；淀积SiO-2,刻蚀形成栅源隔离介质；刻蚀栅源隔离介质的顶部形成用于制作源场板的凹槽；沉积金属,形成源极和源场板；采用Ni金属溅射工艺在N+SiC衬底底部沉积金属,形成漏极。本发明既能降低栅漏电容,改善器件的性能,又能降低栅氧化层中的电场峰值,从而保证分裂栅氧化层具有和传统平面栅SiC VDMOS器件栅氧化层同样的可靠性。(The invention discloses a preparation method and a structure of a split gate SiC VDMOS device with a source field plate, and belongs to the field of semiconductor devices and manufacturing. Providing an N + SiC substrate, and forming an N-SiC epitaxial layer on the surface of the N + SiC substrate; sequentially forming a P well region, an N + region and a P + region in the N-SiC epitaxial layer; forming a gate oxide layer on the surface through high-temperature oxidation, depositing metal or polysilicon on the gate oxide layer, and etching to form a gate; deposition of SiO 2 Etching to form a gate-source isolation medium; etching the top of the gate-source isolation medium to form a groove for manufacturing a source field plate; depositing metal to form a source electrode and a source field plate; and depositing metal at the bottom of the N + SiC substrate by adopting a Ni metal sputtering process to form a drain electrode. The invention can reduce the gate leakage capacitance, improve the performance of the device, and reduce the electric field peak value in the gate oxide layer, thereby ensuring the split gate oxideThe layer has the same reliability as the gate oxide of the traditional planar gate SiC VDMOS device.)
1. A preparation method of a split gate SiC VDMOS device with a source field plate is characterized by comprising the following steps:
providing an N + SiC substrate, and forming an N-SiC epitaxial layer on the surface of the N + SiC substrate in an epitaxial growth mode;
sequentially forming a P well region, an N + region and a P + region in the N-SiC epitaxial layer through high-temperature ion implantation; the two P well regions are positioned at the top of the N-SiC epitaxial layer and are symmetrically arranged; the two P well regions are separated by an N-SiC epitaxial layer; the N + region and the P + region are arranged at the top of the P well region side by side, the N + region is arranged at the inner side of the P + region, and the N + region and the N-SiC epitaxial layer are separated by the P well region;
forming a gate oxide layer on the surface through high-temperature oxidation, depositing metal or polysilicon on the gate oxide layer, and etching to form a gate;
deposition of SiO2Etching to form a gate-source isolation medium; etching the top of the gate-source isolation medium to form a groove for manufacturing a source field plate;
depositing metal to form a source electrode and a source field plate;
and depositing metal at the bottom of the N + SiC substrate by adopting a Ni metal sputtering process to form a drain electrode.
2. The method of claim 1, wherein the doping concentration of the N-SiC epitaxial layer is in the range of 1e13/cm3～1e16/cm3。
3. The method of claim 1, wherein the P-well region has a doping concentration in the range of 1e16/cm3～5e19/cm3。
4. The method of fabricating the split-gate SiC VDMOS device having the source field plate of claim 1, wherein the doping concentration range of the N + region is 1e18/cm3～5e20/cm3。
5. The method of fabricating the split-gate SiC VDMOS device having the source field plate of claim 1, wherein the P + region has a doping concentration in a range of 1e18/cm3～5e20/cm3。
6. The method of claim 1, wherein the gate oxide layer has a thickness in the range of 30nm to 150 nm.
7. The method for preparing the split-gate SiC VDMOS device with the source field plate according to claim 1, wherein the vertical distance from the bottom edge of the source field plate to the gate oxide layer is 0.2 μm to 0.5 μm; the horizontal distance from the two sides of the source field plate to the grid electrode is 0.2-0.5 mu m.
8. A split gate SiC VDMOS device structure with a source field plate is characterized by comprising a drain electrode, an N + SiC substrate, an N-SiC epitaxial layer, a P well region, an N + region, a P + region, a gate oxide layer, a grid electrode, a grid source isolation medium, a source electrode and a source field plate;
the N + SiC substrate is positioned on the top surface of the drain electrode, and the N-SiC epitaxial layer is positioned on the top surface of the N + SiC substrate;
the two P well regions are positioned in the N-SiC epitaxial layer and are symmetrically arranged, and the two P well regions are separated by the N-SiC epitaxial layer;
the N + region and the P + region are arranged at the top of the P well region side by side, the N + region is arranged at the inner side of the P + region, and the N + region and the N-SiC epitaxial layer are separated by the P well region;
the gate oxide layer is positioned on the top of the P well region;
the two gates are positioned on the top of the gate oxide layer;
the grid source isolation medium is positioned on the top of the grid oxide layer and covers the two grids;
the source field plate is positioned on the top of the grid source isolation medium;
the source electrode is positioned at the tops of the N + region and the P + region and covers the gate oxide layer, the gate source isolation medium and the source field plate.
Technical Field
The invention relates to the technical field of semiconductor devices and manufacturing, in particular to a preparation method and a structure of a split-gate SiC VDMOS device with a source field plate.
Background
SiC has excellent physical properties, and is one of typical representatives of third-generation semiconductors, and is suitable for application fields such as high temperature, high frequency, high voltage, high power and the like. The SiC power device has wide application prospect in the fields of electric vehicles, charging piles, data centers, photovoltaic power generation, rail transit and the like.
The traditional plane gate SiC VDMOS device has very large gate-drain overlap capacitance, and due to the gate-drain charge Miller effect, when an element is in a high-frequency state, the frequency response of the device is greatly reduced, so that the performance of the device is lost. Compared with the traditional plane gate structure, the split gate structure divides the gate structure into two parts, reduces the gate leakage capacitance and improves the device performance of the groove gate VDMOS. However, when the split-gate SiC VDMOS device is subjected to high voltage, the electric field peak value in the gate oxide layer is significantly higher than that of the conventional planar gate, which makes the high voltage endurance reliability of the gate oxide layer lower than that of the conventional planar gate SiC VDMOS device.
Disclosure of Invention
The invention aims to provide a preparation method of a split-gate SiC VDMOS device with a source field plate, which aims to solve the problem that when the conventional split-gate SiC VDMOS device bears high voltage, the high-voltage-resistant reliability of a gate oxide layer is lower than that of the conventional planar-gate SiC VDMOS device.
In order to solve the technical problem, the invention provides a preparation method of a split gate SiC VDMOS device with a source field plate, which comprises the following steps:
providing an N + SiC substrate, and forming an N-SiC epitaxial layer on the surface of the N + SiC substrate in an epitaxial growth mode;
sequentially forming a P well region, an N + region and a P + region in the N-SiC epitaxial layer through high-temperature ion implantation; the two P well regions are positioned at the top of the N-SiC epitaxial layer and are symmetrically arranged; the two P well regions are separated by an N-SiC epitaxial layer; the N + region and the P + region are arranged at the top of the P well region side by side, the N + region is arranged at the inner side of the P + region, and the N + region and the N-SiC epitaxial layer are separated by the P well region;
forming a gate oxide layer on the surface through high-temperature oxidation, depositing metal or polysilicon on the gate oxide layer, and etching to form a gate;
deposition of SiO2Etching to form a gate-source isolation medium; etching the top of the gate-source isolation medium to form a groove for manufacturing a source field plate;
depositing metal to form a source electrode and a source field plate;
and depositing metal at the bottom of the N + SiC substrate by adopting a Ni metal sputtering process to form a drain electrode.
Optionally, the doping concentration range of the N-SiC epitaxial layer is 1e13/cm3～1e16/cm3。
Optionally, the doping concentration range of the P-well region is 1e16/cm3～5e19/cm3。
Optionally, the doping concentration range of the N + region is 1e18/cm3～5e20/cm3。
Optionally, the doping concentration range of the P + region is 1e18/cm3～5e20/cm3。
Optionally, the thickness range of the gate oxide layer is 30nm-150 nm.
Optionally, the vertical distance from the bottom edge of the source field plate to the gate oxide layer is 0.2-0.5 μm; the horizontal distance from the two sides of the source field plate to the grid electrode is 0.2-0.5 mu m.
The invention also provides a split gate SiC VDMOS device structure with the source field plate, which comprises a drain electrode, an N + SiC substrate, an N-SiC epitaxial layer, a P well region, an N + region, a P + region, a gate oxide layer, a gate source isolation medium, a source electrode and a source field plate;
the N + SiC substrate is positioned on the top surface of the drain electrode, and the N-SiC epitaxial layer is positioned on the top surface of the N + SiC substrate;
the two P well regions are positioned in the N-SiC epitaxial layer and are symmetrically arranged, and the two P well regions are separated by the N-SiC epitaxial layer;
the N + region and the P + region are arranged at the top of the P well region side by side, the N + region is arranged at the inner side of the P + region, and the N + region and the N-SiC epitaxial layer are separated by the P well region;
the gate oxide layer is positioned on the top of the P well region;
the two gates are positioned on the top of the gate oxide layer;
the grid source isolation medium is positioned on the top of the grid oxide layer and covers the two grids;
the source field plate is positioned on the top of the grid source isolation medium;
the source electrode is positioned at the tops of the N + region and the P + region and covers the gate oxide layer, the gate source isolation medium and the source field plate.
In the preparation method and the structure of the split gate SiC VDMOS device with the source field plate, provided is an N + SiC substrate, and an N-SiC epitaxial layer is formed on the surface of the N + SiC substrate in an epitaxial growth mode; sequentially forming a P well region, an N + region and a P + region in the N-SiC epitaxial layer through high-temperature ion implantation; the two P well regions are positioned at the top of the N-SiC epitaxial layer and are symmetrically arranged; the two P well regions are separated by an N-SiC epitaxial layer; the N + region and the P + region are arranged at the top of the P well region side by side, the N + region is arranged at the inner side of the P + region, and the N + region and the N-SiC epitaxial layer are separated by the P well region; forming a gate oxide layer on the surface through high-temperature oxidation, depositing metal or polysilicon on the gate oxide layer, and etching to form a gate; deposition of SiO2Etching to form a gate-source isolation medium; etching the top of the gate-source isolation medium to form a groove for manufacturing a source field plate; depositing metal to form a source electrode and a source field plate; and depositing metal at the bottom of the N + SiC substrate by adopting a Ni metal sputtering process to form a drain electrode. The split-gate SiC VDMOS device is improved, the peak value of an electric field in the gate oxide layer is reduced through the source field plate close to the gate oxide layer, so that the gate oxide layer in the split-gate SiC VDMOS device has the same reliability as the gate oxide layer of the traditional planar gate SiC VDMOS device, the characteristic of low gate leakage capacitance of the split-gate SiC VDMOS is kept, and the excellent high-frequency working performance of the SiC VDMOS is guaranteed.
Drawings
FIG. 1 is a schematic illustration of providing an N + SiC substrate and forming an N-SiC epitaxial layer;
FIG. 2 is a schematic diagram of the formation of a P-well region in an N-SiC epitaxial layer;
FIG. 3 is a schematic illustration of the formation of N + regions in an N-SiC epitaxial layer;
FIG. 4 is a schematic illustration of the formation of P + regions in an N-SiC epitaxial layer;
FIG. 5 is a schematic diagram of forming a gate oxide layer on a surface;
FIG. 6 is a schematic diagram of forming a gate on a gate oxide layer;
FIG. 7 is a deposition of SiO2Etching to form a schematic diagram of a gate-source isolation medium;
FIG. 8 is a schematic illustration of etching the top of the gate source isolation dielectric to form a recess;
fig. 9 is a schematic diagram of forming source and source field plates;
fig. 10 is a schematic diagram of the drain formed by depositing metal on the bottom of an N + SiC substrate.
Detailed Description
The following will explain in detail the manufacturing method and structure of a split-gate SiC VDMOS device with a source field plate according to the present invention with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a preparation method of a split gate SiC VDMOS device with a source field plate, which comprises the following steps:
as shown in FIG. 1, an N + SiC substrate 02 is provided, an N-SiC epitaxial layer 03 is formed on the surface of the N + SiC substrate by means of epitaxial growth, and the doping concentration range of the N-SiC epitaxial layer 03 is 1e13/cm3～1e16/cm3；
As shown in fig. 2 to 4, a P-well region 04, an N + region 05 and a P + region 06 are sequentially formed in an N-SiC epitaxial layer 03 by high temperature ion implantation, wherein the doping concentration range of the P-well region 04 is 1e16/cm3～5e19/cm3The doping concentration range of the N + region 05 is 1e18/cm3～5e20/cm3The doping concentration range of the P + region 06 is 1e18/cm3～5e20/cm3(ii) a Two P well regions 04 are located on top of the N-SiC epitaxial layer 03Are symmetrically arranged; the two P well regions 04 are separated by an N-SiC epitaxial layer 03; the N + region 05 and the P + region 06 are located at the top of the P well region 04 side by side, the N + region 05 is located on the inner side of the P + region 06, and the N + region 05 and the N-SiC epitaxial layer 03 are separated by the P well region 04;
as shown in fig. 5, forming a gate oxide layer 07 on the surface by high-temperature oxidation, wherein the thickness of the gate oxide layer 07 is in the range of 30nm-150 nm; as shown in fig. 6, metal or polysilicon is deposited on the gate oxide layer 07, and a gate electrode 08 is formed by etching;
as shown in FIG. 7, SiO is deposited2Etching to form a gate-source isolation medium 09; as shown in fig. 8, the top of the gate-source isolation medium 09 is etched to form a groove for manufacturing a source field plate;
as shown in fig. 9, metal is deposited to form a source electrode 10 and a source field plate 11; the vertical distance d1 from the bottom edge of the source field plate 10 to the gate oxide layer 07 is 0.2-0.5 μm; the horizontal distance d2 from the two sides of the source field plate 11 to the gate 08 is 0.2-0.5 μm. The peak value of an electric field in the gate oxide layer is reduced through the source field plate close to the gate oxide layer, so that the gate oxide layer in the split-gate SiC VDMOS device has the same reliability as the gate oxide layer of the traditional planar gate SiC VDMOS device, and meanwhile, the characteristic of low gate leakage capacitance of the split-gate SiC VDMOS device is kept, and the excellent high-frequency working performance of the SiC VDMOS device is ensured.
As shown in fig. 10, a Ni metal sputtering process is used to deposit metal on the bottom of the N + SiC substrate 02 to form the drain 01.
Example two
The invention also provides a split gate SiC VDMOS device structure with a source field plate, which is shown in figure 10 and comprises a drain electrode 01, an N + SiC substrate 02, an N-SiC epitaxial layer 03, a P well region 04, an N + region 05, a P + region 06, a gate oxide layer 07, a gate electrode 08, a gate source isolation medium 09, a source electrode 10 and a source field plate 11; the N + SiC substrate 02 is positioned on the top surface of the drain electrode 01, and the N-SiC epitaxial layer 03 is positioned on the top surface of the N + SiC substrate 02; the two P well regions 04 are positioned in the N-SiC epitaxial layer 03 and are symmetrically arranged, and the two P well regions 04 are separated by the N-SiC epitaxial layer 03; the N + region 05 and the P + region 06 are located at the top of the P well region 04 side by side, the N + region 05 is located on the inner side of the P + region 06, and the N + region 05 and the N-SiC epitaxial layer 03 are separated by the P well region 04; the gate oxide layer 07 is positioned on the top of the P well region 04; two gates 08 are positioned on top of the gate oxide layer 07; the gate-source isolation medium 09 is positioned on the top of the gate oxide layer 07 and covers the two gates 08; the source field plate 11 is positioned on the top of the gate-source isolation medium 09; the source electrode 10 is positioned on the top of the N + region 05 and the P + region 06 and covers the gate oxide layer 07, the gate electrode 08, the gate-source isolation medium 09 and the source field plate 11.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.