阅读说明：本技术 半导体封装方法、半导体封装结构及封装体 (Semiconductor packaging method, semiconductor packaging structure and packaging body ) 是由 刘杰 应战 于 2019-10-16 设计创作，主要内容包括：本发明提供一种半导体封装方法、半导体封装结构及封装体,所述方法包括如下步骤：提供衬底晶圆,衬底晶圆具有相对设置的第一表面及第二表面,在第一表面具有多个凹槽,在凹槽底部具有多个导电柱,导电柱贯穿衬底晶圆；提供多个半导体裸片堆叠体；将半导体裸片堆叠体置于凹槽中,半导体裸片堆叠体的上表面低于或者平齐于凹槽的上边缘,半导体裸片堆叠体的底部与导电柱电连接；将盖板晶圆覆盖在衬底晶圆的第一表面,以密封凹槽,形成半导体封装结构,衬底晶圆、半导体裸片堆叠体及盖板晶圆之间的间隙未被填充物填充。本发明优点在于,形成的半导体结构具有封装高度低、可靠性高及翘曲度低的特点。(The invention provides a semiconductor packaging method, a semiconductor packaging structure and a packaging body, wherein the method comprises the following steps: providing a substrate wafer, wherein the substrate wafer is provided with a first surface and a second surface which are oppositely arranged, the first surface is provided with a plurality of grooves, the bottoms of the grooves are provided with a plurality of conductive columns, and the conductive columns penetrate through the substrate wafer; providing a plurality of semiconductor die stacks; placing the semiconductor die stacked body in the groove, wherein the upper surface of the semiconductor die stacked body is lower than or flush with the upper edge of the groove, and the bottom of the semiconductor die stacked body is electrically connected with the conductive columns; and covering the cover plate wafer on the first surface of the substrate wafer to seal the groove to form the semiconductor packaging structure, wherein gaps among the substrate wafer, the semiconductor bare chip stacking body and the cover plate wafer are not filled with fillers. The invention has the advantages that the formed semiconductor structure has the characteristics of low packaging height, high reliability and low warping degree.)

1. A semiconductor packaging method, comprising the steps of:

providing a substrate wafer, wherein the substrate wafer is provided with a first surface and a second surface which are arranged oppositely, the first surface is provided with a plurality of grooves, the bottoms of the grooves are provided with a plurality of conductive columns, and the conductive columns penetrate through the bottoms of the grooves to reach the second surface;

providing a plurality of semiconductor die stacks;

placing the semiconductor die stack in the recess, an upper surface of the semiconductor die stack being below or flush with an upper edge of the recess, a bottom of the semiconductor die stack being electrically connected to the conductive pillars;

covering a cover wafer on the first surface of the substrate wafer to seal the recess, forming a semiconductor package structure, gaps between the substrate wafer, the semiconductor die stack, and the cover wafer not being filled with a filler.

2. The semiconductor packaging method according to claim 1, wherein a plurality of conductive bumps are formed on the second surface of the substrate wafer, and the conductive bumps are electrically connected to the conductive pillars.

3. The semiconductor packaging method of claim 1, wherein the method of forming the recess in the substrate wafer comprises the steps of:

carrying out planarization treatment on the first surface of the substrate wafer;

and removing part of the substrate wafer from the first surface until the conductive posts are exposed, and forming the grooves.

4. The semiconductor packaging method according to claim 3, wherein the substrate wafer has dicing streets as alignment marks for forming the grooves.

5. The semiconductor packaging method of claim 1, wherein the semiconductor die stack is formed from a plurality of semiconductor die stacks, the semiconductor dies being electrically connected therebetween and electrically connected with the conductive pillars through a bottom of the semiconductor die stack.

6. The semiconductor packaging method of claim 5, wherein the semiconductor dies are electrically connected to each other by conductive pillars penetrating through each semiconductor die and conductive bumps between adjacent semiconductor dies.

7. The semiconductor packaging method of claim 1, wherein the bottom of the stack of semiconductor dies and the conductive pillars that extend through the bottom of the recess are electrically connected by a conductive bump.

8. The semiconductor packaging method of claim 1, wherein a surface of the lid wafer facing the substrate wafer has a plurality of conductive pillars electrically connected with an upper surface of the semiconductor die stack.

9. The semiconductor packaging method according to claim 1, further comprising, after the step of sealing the groove, a step of dicing: and cutting the semiconductor packaging structure along the gaps among the grooves to form a plurality of mutually independent packaging bodies.

10. A semiconductor package structure, comprising:

the manufacturing method comprises the following steps that a substrate wafer is provided with a first surface and a second surface which are arranged oppositely, the first surface is provided with a plurality of grooves, the bottoms of the grooves are provided with a plurality of conductive columns, and the conductive columns penetrate through the bottoms of the grooves to reach the second surface;

a plurality of semiconductor die stacks disposed within the recesses and having upper surfaces that are lower than or flush with upper edges of the recesses, the bottoms of the semiconductor die stacks being electrically connected to the conductive pillars;

a cover wafer overlying the first surface of the substrate wafer to seal the recess, gaps between the substrate wafer, the stack of semiconductor dies, and the cover wafer being unfilled by a filler.

11. The semiconductor package structure of claim 10, wherein the substrate wafer has a plurality of conductive bumps on the second surface thereof, the conductive bumps being electrically connected to the conductive pillars.

12. The semiconductor package structure of claim 10, wherein the stack of semiconductor dies is formed from a plurality of stacks of semiconductor dies, the semiconductor dies being electrically connected between each other and electrically connected to the conductive pillars through a bottom of the stack of semiconductor dies.

13. The semiconductor package structure of claim 12, wherein the semiconductor dies are electrically connected to each other by conductive pillars penetrating through each semiconductor die and conductive bumps between adjacent semiconductor dies.

14. The semiconductor package structure of claim 10, wherein the bottom of the stack of semiconductor dies and the conductive pillars that extend through the bottom of the recess are electrically connected by a conductive bump.

15. The semiconductor package structure of claim 10, wherein a surface of the lid wafer facing the substrate wafer has a plurality of conductive pillars electrically connected with an upper surface of the semiconductor die stack.

16. A package, comprising:

the substrate is provided with a first surface and a second surface which are oppositely arranged, the first surface is provided with at least one groove, the bottom of the groove is provided with a plurality of conductive columns, and the conductive columns penetrate through the bottom of the groove to reach the second surface;

at least one semiconductor die stack disposed within the recess, an upper surface of the semiconductor die stack being below or flush with an upper edge of the recess, a bottom of the semiconductor die stack being electrically connected to the conductive pillars;

a cover plate covering the first surface of the substrate to seal the recess, gaps between the substrate, the stack of semiconductor dies, and the cover plate being unfilled by a filler.

Technical Field

The present invention relates to the field of semiconductor packaging, and in particular, to a semiconductor packaging method, a semiconductor packaging structure and a package.

Background

The stack package technology, also called 3D or three-dimensional package technology, is one of the mainstream multi-chip package technologies at present, and can stack at least two semiconductor chips (Die, also called bare Die, i.e. a full-function block cut from a wafer) in a vertical direction, and is commonly used to manufacture electronic components such as memory chips, logic chips, processor chips, and the like. As the electronic industry develops, high capacity, high functionality, high speed and small size of electronic components are increasingly required, and in order to meet the requirements, more chips need to be incorporated into a single package, which causes the package height of the electronic components to be higher and the reliability to be lower, affecting the performance of the package structure.

Therefore, how to reduce the package height of the package and improve the reliability of the package is a technical problem that needs to be solved at present.

Disclosure of Invention

The present invention provides a semiconductor packaging method, a semiconductor packaging structure and a package, which have the features of low package height, high reliability and low warpage.

In order to solve the above problems, the present invention provides a semiconductor packaging method, which includes the steps of: providing a substrate wafer, wherein the substrate wafer is provided with a first surface and a second surface which are arranged oppositely, the first surface is provided with a plurality of grooves, the bottoms of the grooves are provided with a plurality of conductive columns, and the conductive columns penetrate through the bottoms of the grooves to reach the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the recess, an upper surface of the semiconductor die stack being below or flush with an upper edge of the recess, a bottom of the semiconductor die stack being electrically connected to the conductive pillars; covering a cover wafer on the first surface of the substrate wafer to seal the recess, forming a semiconductor package structure, gaps between the substrate wafer, the semiconductor die stack, and the cover wafer not being filled with a filler.

Further, the second surface of the substrate wafer is provided with a plurality of conductive blocks, and the conductive blocks are electrically connected with the conductive columns.

Further, the method for forming the groove on the substrate wafer comprises the following steps: carrying out planarization treatment on the first surface of the substrate wafer; and removing part of the substrate wafer from the first surface until the conductive posts are exposed, and forming the grooves.

Further, the substrate wafer is provided with a cutting channel, and the cutting channel is used as an alignment mark for forming the groove.

Further, the semiconductor die stack is formed from a plurality of semiconductor die stacks, the semiconductor dies being electrically connected therebetween and electrically connected with the conductive pillars through a bottom of the semiconductor die stack.

Further, the semiconductor dies are electrically connected through the conductive columns penetrating through the semiconductor dies and the conductive blocks between the adjacent semiconductor dies.

Further, the bottom of the stack of semiconductor dies is electrically connected to the conductive posts that extend through the bottom of the recess by conductive bumps.

Further, a surface of the lid wafer facing the substrate wafer has a plurality of conductive pillars electrically connected with an upper surface of the semiconductor die stack.

Further, after the step of sealing the groove, a cutting step is also included: and cutting the semiconductor packaging structure along the gaps among the grooves to form a plurality of mutually independent packaging bodies.

The present invention also provides a semiconductor package structure, which includes: the manufacturing method comprises the following steps that a substrate wafer is provided with a first surface and a second surface which are arranged oppositely, the first surface is provided with a plurality of grooves, the bottoms of the grooves are provided with a plurality of conductive columns, and the conductive columns penetrate through the bottoms of the grooves to reach the second surface; a plurality of semiconductor die stacks disposed within the recesses and having upper surfaces that are lower than or flush with upper edges of the recesses, the bottoms of the semiconductor die stacks being electrically connected to the conductive pillars; a cover wafer overlying the first surface of the substrate wafer to seal the recess, gaps between the substrate wafer, the stack of semiconductor dies, and the cover wafer being unfilled by a filler.

Further, the second surface of the substrate wafer is provided with a plurality of conductive blocks, and the conductive blocks are electrically connected with the conductive columns.

Further, the semiconductor die stack is formed from a plurality of semiconductor die stacks, the semiconductor dies being electrically connected therebetween and electrically connected with the conductive pillars through a bottom of the semiconductor die stack.

Further, the semiconductor dies are electrically connected through the conductive columns penetrating through the semiconductor dies and the conductive blocks between the adjacent semiconductor dies.

Further, the bottom of the stack of semiconductor dies is electrically connected to the conductive posts that extend through the bottom of the recess by conductive bumps.

Further, a surface of the lid wafer facing the substrate wafer has a plurality of conductive pillars electrically connected with an upper surface of the semiconductor die stack.

The present invention also provides a package, comprising: the substrate is provided with a first surface and a second surface which are oppositely arranged, the first surface is provided with at least one groove, the bottom of the groove is provided with a plurality of conductive columns, and the conductive columns penetrate through the bottom of the groove to reach the second surface; at least one semiconductor die stack disposed within the recess, an upper surface of the semiconductor die stack being below or flush with an upper edge of the recess, a bottom of the semiconductor die stack being electrically connected to the conductive pillars; a cover plate covering the first surface of the substrate to seal the recess, gaps between the substrate, the stack of semiconductor dies, and the cover plate being unfilled by a filler.

The invention has the advantages that the grooves are formed on the substrate wafer to accommodate the stacked semiconductor bare chips, and the cover plate wafer is used for sealing, so that the height of a semiconductor packaging structure can be greatly reduced while the same number of semiconductor bare chips are packaged, and ultra-thin packaging is realized. In addition, gaps among the substrate wafer, the semiconductor bare chip stacking body and the cover plate wafer are not filled with fillers, only the cover plate wafer is used for sealing the grooves, and then the semiconductor bare chip stacking body is sealed, so that the problems of reliability and warping degree caused by deformation of a semiconductor packaging structure due to the fact that the fillers are not matched with expansion coefficients of the substrate wafer, the semiconductor bare chip stacking body and the cover plate wafer can be avoided.

Drawings

FIG. 1 is a schematic step diagram of one embodiment of a semiconductor packaging method of the present invention;

FIGS. 2A-2G are schematic flow diagrams illustrating a semiconductor packaging method according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the invention.

Fig. 4 is a schematic structural diagram of an embodiment of the package of the present invention.

Detailed Description

The following describes the semiconductor packaging method, semiconductor packaging structure and package in detail with reference to the accompanying drawings.

Fig. 1 is a schematic step diagram of a semiconductor packaging method according to an embodiment of the invention. Referring to fig. 1, the semiconductor packaging method includes the following steps: step S10, providing a substrate wafer, where the substrate wafer has a first surface and a second surface opposite to each other, the first surface has a plurality of grooves, the bottom of each groove has a plurality of conductive pillars, and the conductive pillars penetrate through the bottom of each groove to reach the second surface; a step S11 of providing a plurality of semiconductor die stacks; a step S12 of placing the semiconductor die stack in the groove, wherein the upper surface of the semiconductor die stack is lower than or flush with the upper edge of the groove, and the bottom of the semiconductor die stack is electrically connected to the conductive pillars; step S13, covering a cover wafer on the first surface of the substrate wafer to seal the grooves, so as to form a semiconductor package structure, wherein gaps among the substrate wafer, the semiconductor die stacked body and the cover wafer are not filled with fillers; step S14, cutting the semiconductor package structure along the gaps between the grooves to form a plurality of independent packages.

Fig. 2A to 2G are schematic flow charts of a semiconductor packaging method according to an embodiment of the present invention.

Referring to step S10 and fig. 2C, a substrate wafer 200 is provided, wherein the substrate wafer 200 has a first surface 200A and a second surface 200B disposed opposite to each other. The first surface 200A has a plurality of grooves 201, the bottom of the grooves 201 has a plurality of conductive posts 202, and the conductive posts 202 penetrate through the bottoms of the grooves 201 to the second surface 200B.

One embodiment of forming the recess 201 is illustrated below.

Referring to fig. 2A, the substrate wafer 200 has a first surface 200A and a second surface 200B disposed opposite to each other. The first surface 200A is a back surface of the substrate wafer 200, the second surface 200B is a front surface of the substrate wafer 200, that is, at the second surface 200B, the substrate wafer 200 has a functional layer 200C. The conductive pillars 202 extend from the second surface 200B toward the interior of the substrate wafer 200, and the surfaces of the conductive pillars 202 are exposed at the second surface 200B. The conductive posts 202 can not only conduct electricity, but also conduct heat.

Referring to fig. 2B, the first surface 200A of the substrate wafer 200 is planarized to facilitate subsequent processes. Further, the first surface 200A of the substrate wafer 200 may be planarized by chemical mechanical polishing. In this step, the substrate wafer 200 is thinned. It should be noted that, after the step is completed, the distance H from the first surface 200A of the substrate wafer 200 to the functional layer 200C of the second surface 200B is greater than or equal to the height of the semiconductor die stack 210, so as to provide sufficient operating space for the subsequent processes.

Referring to fig. 2C, a portion of the substrate wafer 200 is removed from the first surface 200A to expose the conductive pillars 202, so as to form the grooves 201. In this step, a photolithography and etching process may be used to remove a portion of the substrate wafer 200, and the etching is stopped when the conductive pillars 202 are exposed at the bottom of the grooves 201. Further, when the etching is stopped, the etching conditions can be adjusted, so that the etching rate of the edge of the groove 201 is smaller than the etching rate of the middle of the groove 201, the corner of the bottom of the groove 201 is arc-shaped, and the stability of the side wall of the groove 201 can be enhanced.

Further, in this step, the substrate wafer 200 has the scribe lines 203, as shown in fig. 2C, the scribe lines 203 pass through the gap between two adjacent grooves 201, and when the grooves 201 are formed, the scribe lines 203 can be used as alignment marks for forming the grooves 201, so that the accuracy of forming the grooves 201 is improved, and no additional alignment mark is required, thereby saving the process steps and improving the production efficiency.

In the above-mentioned embodiment of forming the groove 201 on the first surface 200A of the substrate wafer 200, in other embodiments of the present invention, other methods may be adopted to form the groove 201 on the first surface 200A of the substrate wafer 200.

In this embodiment, the width of the scribe line 203 is the same as the distance between two grooves 201, and in other embodiments of the present invention, the grooves 201 may occupy part of the space of the scribe line 203, so that the distance between two adjacent grooves 201 is smaller than the width of the scribe line 203, thereby facilitating the subsequent semiconductor die stack 210 to be placed in the groove 201; it is furthermore possible to avoid that the sides of the stack of semiconductor dies 210 are in contact with the sidewalls of the recess 201, which would affect the performance of the stack of semiconductor dies 210.

Further, with reference to fig. 2A, a plurality of conductive bumps 204 are disposed on the second surface 200B of the substrate wafer 200, and the conductive bumps 204 are electrically connected to the conductive pillars 202 to electrically connect the conductive pillars 202 to an external device, such as a printed circuit board. Wherein the conductive bumps 204 may be formed on the second surface 200B of the substrate wafer 200 before the grooves 201 are formed.

Referring to step S11 and fig. 2D, a plurality of semiconductor die stacks 210 are provided. The number of semiconductor die stacks 210 may be the same as the number of recesses 201, or the number of semiconductor die stacks 210 is greater than the number of recesses 201. Specifically, if the number of the semiconductor die stacks 210 is the same as the number of the grooves 201, one semiconductor die stack 210 is placed in one groove 201 in a subsequent process; if the number of semiconductor die stacks 210 is greater than the number of recesses 201, two or more semiconductor die stacks 210 may be placed in parallel within one recess 201.

The semiconductor die stack 210 is formed by stacking a plurality of semiconductor dies 210A, in this embodiment, three semiconductor dies 210A are schematically illustrated. Three semiconductor dies 210A are stacked in sequence to form the semiconductor die stack 210. In the semiconductor die stack 210, the semiconductor dies 210A are electrically connected to each other so that electrical signals of the semiconductor dies 210A can be transmitted to an external structure. In the present embodiment, the semiconductor dies 210A are electrically connected to each other through the conductive pillar 211 penetrating through each semiconductor die and the conductive bump 212 between adjacent semiconductor dies. The method of forming the conductive pillars on the semiconductor die 210A includes, but is not limited to, a Through Silicon Via (TSV) process, which is well known in the art.

After this step is performed, the bottom of the semiconductor die stack 210 is exposed with the surface of the conductive pillars, and the top of the semiconductor die stack 210 is also exposed with the surface of the conductive pillars.

Referring to step S12 and fig. 2E, the semiconductor die stack 210 is placed in the recess 201. In this step, one semiconductor die stack 210 may be placed in one of the recesses 201, and a plurality of semiconductor die stacks 210 may also be placed. In this embodiment, one semiconductor die stack 210 is placed within one recess 201.

The bottom of the semiconductor die stack 210 is electrically connected to the conductive pillars 202 that extend through the bottom of the recess 201. That is, the conductive pillars 211 exposed at the bottom of the semiconductor die stack 210 are electrically connected with the conductive pillars 202 exposed at the bottom of the recess 201. Specifically, the two may be electrically connected through the conductive block 213.

The upper surface of the semiconductor die stack 210 is below or flush with the upper edge of the recess 201 to facilitate subsequent processing. In this embodiment, the upper surface of the semiconductor die stack 210 is lower than the upper edge of the recess 201.

Referring to step S13 and fig. 2F, a cover wafer 220 is covered on the first surface 200A of the substrate wafer 200 to seal the recess 201, so as to form a semiconductor package structure. After the step is completed, the inner space of the groove 201 is a closed space. Wherein the cover wafer 220 and the substrate wafer 200 may be bonded through a bonding process such that the groove 201 is sealed.

The semiconductor packaging method of the invention forms the groove on the substrate wafer to contain the semiconductor bare chip stacking body, and seals through the cover plate wafer, thereby greatly reducing the height of the semiconductor packaging structure and realizing ultra-thin packaging while packaging the same number of semiconductor bare chips. In addition, gaps among the substrate wafer 200, the semiconductor die stack 210 and the cover plate wafer 220 are not filled with fillers, and only the cover plate wafer 220 is used for sealing the groove 201, so that the semiconductor die stack 210 is sealed, and the problem of reliability caused by deformation of a semiconductor packaging structure due to the fact that expansion coefficients of the fillers are not matched with those of the substrate wafer, the semiconductor die stack and the cover plate wafer can be solved.

Further, the surface of the lid wafer 220 facing the substrate wafer 200 has a plurality of conductive pillars 221, and the conductive pillars 221 are electrically connected to the upper surface of the semiconductor die stack 210, i.e., the conductive pillars 221 of the lid wafer 220 surface are electrically connected to the conductive pillars 211 exposed at the upper surface of the semiconductor die stack 210. The lid wafer 220 can provide thermal conduction to the stack of semiconductor dies 210 through the conductive pillars 221 and further fix the position of the stack of semiconductor dies 210. In addition, in a semiconductor package, other wafers may be stacked on the cover wafer 220, and the conductive pillars 221 may function as electrical connections.

Optionally, in this embodiment, after step S13, a cutting step is further included. Referring to step S14 and fig. 2G, the semiconductor package structure is cut along the gaps between the grooves 201 to form a plurality of independent packages. Specifically, the cutting is performed along the cutting lines 203 between the grooves 201 to form a plurality of packages independent of each other. The cutting methods include, but are not limited to, mechanical cutting, laser cutting, and the like.

The invention also provides a semiconductor packaging structure formed by adopting the semiconductor packaging method. Fig. 3 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the invention. Referring to fig. 3, the semiconductor package structure includes a substrate wafer 300, a plurality of semiconductor die stacks 310, and a lid wafer 320.

The substrate wafer 300 has a first surface 300A and a second surface 300B opposite to each other, the first surface 300A has a plurality of grooves 301, the bottoms of the grooves 301 have a plurality of conductive pillars 302, and the conductive pillars 302 penetrate the bottoms of the grooves 301 to reach the second surface 300B. The substrate wafer 300 has a plurality of conductive bumps 304 on the second surface 300B, and the conductive bumps 304 are electrically connected to the conductive pillars 302.

The semiconductor die stack 310 is placed in the recess 301 with the upper surface of the semiconductor die stack 310 being below or flush with the upper edge of the recess 301, in this embodiment the upper surface of the semiconductor die stack 310 is below the upper edge of the recess 301. The bottom of the semiconductor die stack 310 is electrically connected with the conductive pillars 302. The stack of semiconductor dies is formed by a plurality of semiconductor dies 310A stacked 310, the semiconductor dies 310A being electrically connectable to each other by conductive pillars 311 extending through each of the semiconductor dies 310A and conductive bumps 312 between adjacent ones of the semiconductor dies 310A, and electrically connectable to the conductive pillars 302 by a bottom of the stack of semiconductor dies 310. Wherein the conductive pillars 302 and the bottom of the semiconductor die stack 310 can be electrically connected by conductive bumps 313.

The cover wafer 320 covers the first surface 300A of the substrate wafer 300 to seal the recess 301. The gaps between the substrate wafer 300, the stack of semiconductor dies 310, and the lid wafer 320 are not filled with filler. Further, the cover wafer 320 has a plurality of conductive pillars 321 on its surface facing the substrate wafer 300, and the conductive pillars 321 are electrically connected to the upper surface of the semiconductor die stack 310. Specifically, the conductive pillars 321 are electrically connected with the conductive pillars 311 exposed at the upper surface of the semiconductor die stack 310. The lid wafer 300 can provide thermal conduction to the stack of semiconductor dies 310 through the conductive pillars 321 and further fix the position of the stack of semiconductor dies 310. In addition, in a semiconductor package, other wafers may be stacked on the cover wafer 300, and the conductive pillars 321 may function as electrical connections.

The semiconductor packaging structure of the invention forms the groove on the substrate wafer to contain the semiconductor bare chip stacking body, and seals through the cover plate wafer, thereby greatly reducing the height of the semiconductor packaging structure and realizing ultra-thin packaging. In addition, gaps among the substrate wafer, the semiconductor bare chip stacking body and the cover plate wafer are not filled with fillers, only the cover plate wafer is used for sealing the grooves, and then the semiconductor bare chip stacking body is sealed, so that the problem of reliability of a semiconductor packaging structure caused by the fact that the fillers are not matched with expansion coefficients of the substrate wafer, the semiconductor bare chip stacking body and the cover plate wafer can be solved, and the semiconductor packaging structure has good reliability.

The invention also provides a packaging body. Fig. 4 is a schematic structural diagram of an embodiment of the package of the present invention. Referring to fig. 4, the package is formed by cutting the semiconductor package structure along the scribe lines between the grooves. The package includes a substrate 400, at least one semiconductor die stack 410, and a lid plate 420.

The substrate 400 has a first surface 400A and a second surface 400B opposite to each other, the first surface 400A has at least one groove 401, the bottom of the groove 401 has a plurality of conductive pillars 402, and the conductive pillars 402 penetrate through the bottom of the groove 401 to the second surface 400B.

The semiconductor die stack 410 is placed in the recess 401, the upper surface of the semiconductor die stack 410 is lower than or flush with the upper edge of the recess 401, and the bottom of the semiconductor die stack 410 is electrically connected to the conductive pillars 402.

The cover plate 420 covers the first surface 400A of the substrate 400 to seal the recess 401, and gaps between the substrate 400, the semiconductor die stack 410, and the cover plate 420 are not filled with a filler. The packaging body has small packaging thickness, meets the requirement of ultra-thin packaging body, does not hesitate to cause substrate deformation due to different thermal expansion coefficients, and has high reliability.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.