阅读说明：本技术 一种单粒子加固7相时钟产生电路 (Single-particle reinforced 7-phase clock generation circuit ) 是由 时飞 李建成 边强 李全利 赵伟 孙洪江 于 2020-12-24 设计创作，主要内容包括：本发明公开了一种单粒子加固7相时钟产生电路,包括：环形移位寄存器、复位检测器和门控缓冲器；环形移位寄存器,用于产生7相时钟信号；门控缓冲器,用于对7相时钟信号进行去毛刺处理后输出,以实现对多相时钟长布线的驱动；复位检测器,用于在出现单粒子效应时,抑制单粒子效应下环形移位寄存器产生的时钟信号异常。本发明通过带有置位、复位功能的触发器级联组成环形移位寄存器架构实现7相时钟输出,同时通过错误检测复位逻辑实现单粒子加固,避免环路受单粒子影响进入非正常循环状态；结构实现简单,附加抖动小,且扩展性强,可通过增加环路中级联触发器数量获得N相时钟输出。(The invention discloses a single-particle reinforced 7-phase clock generation circuit, which comprises: a ring shift register, a reset detector and a gate control buffer; a ring shift register for generating a 7-phase clock signal; the gating buffer is used for carrying out deburring processing on the 7-phase clock signal and then outputting the processed signal so as to drive long wiring of the multiphase clock; and the reset detector is used for inhibiting the clock signal abnormality generated by the annular shift register under the single event effect when the single event effect occurs. According to the invention, 7-phase clock output is realized by forming an annular shift register architecture by cascading triggers with setting and resetting functions, and single event reinforcement is realized by error detection resetting logic, so that a loop is prevented from entering an abnormal cycle state under the influence of single events; the structure is simple to realize, the additional jitter is small, the expansibility is strong, and N-phase clock output can be obtained by increasing the number of cascaded triggers in a loop.)

1. A single-event hardened 7-phase clock generation circuit, comprising: a ring shift register, a reset detector and a gate control buffer;

a ring shift register for generating a 7-phase clock signal;

the gating buffer is used for carrying out deburring processing on the 7-phase clock signal and then outputting the processed signal so as to drive long wiring of the multiphase clock;

and the reset detector is used for inhibiting the clock signal abnormality generated by the annular shift register under the single event effect when the single event effect occurs.

2. The single event hardened 7-phase clock generation circuit of claim 1, wherein the ring is a circular ringA shift register, comprising: 7 triggers connected end to end in turn: flip-flop DFF₀Trigger DFF₁Trigger DFF₂Trigger DFF₃Trigger DFF₄Trigger DFF₅And flip-flop DFF₆；

Two inputs D of each flip-flop_nAnd D'_nRespectively receiving two output signals Q of the previous stage trigger_n-1And Q'_n-1And outputs two pairs of output signals (Q)_n，Q'_n) And (dQ)_n,dQ'_n) (ii) a Wherein the output signal dQ_nAnd dQ'_nAre respectively output signals Q_nAnd Q'_nA delayed signal;

output signal dQ_nAnd dQ_n' is connected to a reset detect detector to reduce the effect of node parasitic capacitance in the ring shift register on the operating frequency range.

3. The single-event hardened 7-phase clock generation circuit according to claim 2,

global signal RST_CHECKThe output port of any flip-flop is connected with the set end of any flip-flop in the annular shift register, and the initial state of the output port of any flip-flop is '1';

global signal RST_CHECKAnd the output ports of the other 6 flip-flops except any one flip-flop in the annular shift register are all in an initial state of '0'.

4. The single event hardened 7-phase clock generation circuit according to claim 3, wherein the reference clock signal CLKREF is connected to the clock input signal port CK of the 7 flip-flops; when a reference clock signal CLKREF is input, the initial values of the output ports of all the triggers are sequentially shifted through a ring shift register, the output ports of all the triggers are clock signals with the duty ratio of 1:6, the period T of the input reference clock signal CLKRREF is taken as a phase-shifting reference interval, and the output time delays of two adjacent triggers are sequentially differed by T to generate a 7-phase clock signal.

5. The single-event hardened 7-phase clock generation circuit according to claim 2, wherein the flip-flops are: a dual-mode D flip-flop with reset and set functions.

6. The single event hardened 7-phase clock generation circuit of claim 1, wherein the gated buffer comprises: 7 buffers: buffer BUF₆Buffer BUF₅Buffer BUF₄Buffer BUF₃Buffer BUF₂Buffer BUF₁And a buffer BUF₀；

Each buffer receives a phase clock signal, and the received phase clock signal is output after being subjected to deburring processing.

7. The single-event hardened 7-phase clock generation circuit according to claim 6, wherein the buffer comprises: a two-way gate control unit and an inverting gate; the two-way gate control unit and the inverting gate are composed of PMOS tubes and NMOS tubes; the PMOS tube includes: PM (particulate matter)₁And PM₂The NMOS tube comprises: NM₁And NM₂；

PM₁、PM₂、NM₁And NM₂Sequentially connected in series, one input signal A is connected with PM₁And NM₁Grid, the other input signal B is connected with PM₂And NM₂The grid electrode forms a double-channel gate control unit;

PM₃and NM₃Are connected in series to form an inverting gate;

the output signal C of the two-way gate control unit is connected with the input of the inverting gate, and the inverting gate outputs a signal D.

8. The single event hardened 7-phase clock generation circuit of claim 2, wherein the reset detector comprises: all-0 detection logic unit, multi-1 detection logic unit and first NAND gate N₁And a third inverting gate INV₃And a fourth inverting gate INV₄And a second NAND gate N₂；

An all 0 detection logic unit comprising: a left half adder and a right half adder; the left half adder includes: four first-stage left half-adders HA₁₁、HA₁₂、HA₁₃And HA₁₄Two second-stage left half-adders HA₁₅And HA₁₆A third-stage left half adder HA₁₇And a first inverter gate INV₁(ii) a The right half adder includes: four first-stage right half adders HA₂₁、HA₂₂、HA₂₃And HA₂₄Two second-stage right half adders HA₂₅And HA₂₆A third-stage right half adder HA₂₇And a second inverter INV₂；

First-stage left half adder HA₁₁For use according to VSS ═ 0 and dQ₀Output signal { C₀,S₁}＝0+dQ₀；

Second-stage left half adder HA₁₂According to dQ₁And dQ₂Output signal { C₁,S₁}＝dQ₁+dQ₂；

Third-stage left half adder HA₁₃According to dQ₃And dQ₄Output signal { C₂,S₂}＝dQ₃+dQ₄；

Fourth-stage left half adder HA₁₄According to dQ₅And dQ₆Output signal { C₃,S₃}＝dQ₅+dQ₆；

Second-stage left half adder HA₁₅For according to S₁And S₂Output signal { C₄,S₄}＝S₁+S₂；

Second-stage left half adder HA₁₆For according to S₃And S₄Output signal { C₅,S₅}＝S₃+S₄；

Third-stage left half adder HA₁₇For according to S₅And S₆Output signal { C₆,S₆}＝S₅+S₆；

First-stage right half adder HA₂₁Is used in accordance withVSS ═ 0 and dQ'₀Output signal { C'₀,S'₀}＝0+dQ'₀；

Second stage right half adder HA₂₂From dQ'₁And dQ'₂Output signal { C'₁,S'₁}＝dQ'₁+dQ'₂；

Third stage right half adder HA₂₃From dQ'₃And dQ'₄Output signal { C'₂,S'₂}＝dQ'₃+dQ'₄；

Fourth-stage right half adder HA₂₄From dQ'₅And dQ'₆Output signal { C'₃,S'₃}＝dQ'₅+dQ'₆；

Second stage right half adder HA₂₅From S'₁And S'₂Output signal { C'₄,S'₄}＝S'₁+S'₂；

Second stage right half adder HA₂₆From S'₃And S'₄Output signal { C'₅,S'₅}＝S'₃+S'₄；

Third stage right half adder HA₂₇From S'₅And S'₆Output signal { C'₆,S'₆}＝S'₅+S'₆；

First inverter gate INV₁For converting the signal S₆Output to the first NAND gate N₁Second inverting gate INV₂For signal S'₆Output to the first NAND gate N₁；

First NAND gate N₁For the signal S₆And signal S'₆Performing NAND logic processing to output signal Y₁To the second NAND gate N₂；

A multi-1 detection logic unit for receiving the carry signal C output by the all-0 detection logic unit₁、C₂、···、C₇、C'₁、C'₂、···、C'₇(ii) a For carry signal C₁、C₂、···、C₇、C'₁、C'₂、···、C'₇Performing AND logic processing to output R_OA signal;

third inverter INV₃R for receiving the output of the multi 1 detection logic unit₀A signal;

fourth inverter INV₄For receiving the third inverting gate INV₃Output signal, output Y₂A signal;

second NAND gate N₂For the first NAND gate N₁Y of the output₁Signal, Y output from fourth inverting gate₂The signals are subjected to NAND logic processing, and a global signal RST is output_CHECK。

9. The single-event reinforced 7-phase clock generation circuit according to claim 8, wherein the half adder is composed of an exclusive or gate and an and gate; wherein S is_nAnd S'_nRepresenting the sum output signal of a half-adder, C_nAnd C'_nRepresenting a half-adder carry signal.

10. The single-event hardened 7-phase clock generation circuit according to claim 8, wherein the 1-more detection logic unit comprises: 14 NMOS transistors and one PMOS transistor PM₁₀(ii) a Wherein, 12 NMOS pipes are: NM₁₀、NM₁₁···、NM₁₆、NM'₁₀、NM'₁₁···、NM'₁₆；

NM₁₀And NM'₁₀Connected in series, the gates being connected to carry signals C₀And C'₀；

NM₁₁And NM'₁₁Connected in series, the gates being connected to carry signals C₁And C'₁；

And so on;

NM₁₆and NM'₁₆The tubes are connected in series, and the gates are connected with carry signals C₆And C'₆；

NM₁₀、NM₁₁、···、NM₁₆All the drains of (1) and the signal line R₀Connected to PM₁₀Gate and drain electrodes and signal lineR₀Are connected.

Technical Field

The invention belongs to the technical field of integrated circuit design, and particularly relates to a single-particle reinforced 7-phase clock generation circuit.

Background

The multiphase clock generation circuit is a key module for realizing high-speed serial communication. The multi-phase sampling or gating circuit can provide multi-phase sampling or gating signals for the parallel-serial and serial-parallel conversion modules, and can provide high-quality multi-phase clock signals for a high-speed serial system through reasonable clock tree layout.

The traditional DLL architecture multiphase clock generation circuit has the defects of complex design, difficulty in reinforcement, limited frequency locking range, introduction of additional jitter into a delay unit and the like, and can be disordered and incapable of self-recovery under the influence of a single particle, so that functional interruption is caused, and when the DLL architecture multiphase clock generation circuit is integrated in a PLL loop as a feedback frequency divider, the PLL loop cannot be self-regulated to realize recovery.

Disclosure of Invention

The technical problem of the invention is solved: the single-event reinforced 7-phase clock generation circuit overcomes the defects of the prior art, realizes 7-phase clock output by forming an annular shift register framework through cascading triggers with setting and resetting functions, and simultaneously realizes single-event reinforcement through error detection resetting logic so as to prevent a loop from entering an abnormal cycle state under the influence of single events; the structure is simple to realize, the additional jitter is small, the expansibility is strong, and N-phase clock output can be obtained by increasing the number of cascaded triggers in a loop.

In order to solve the technical problem, the invention discloses a single-event reinforced 7-phase clock generation circuit, which comprises: a ring shift register, a reset detector and a gate control buffer;

a ring shift register for generating a 7-phase clock signal;

the gating buffer is used for carrying out deburring processing on the 7-phase clock signal and then outputting the processed signal so as to drive long wiring of the multiphase clock;

and the reset detector is used for inhibiting the clock signal abnormality generated by the annular shift register under the single event effect when the single event effect occurs.

In the above-described single-particle reinforced 7-phase clock generation circuit, the ring shift register includes: 7 triggers connected end to end in turn: flip-flop DFF₀Trigger DFF₁Trigger DFF₂Trigger DFF₃Trigger DFF₄Trigger DFF₅And flip-flop DFF₆；

Two inputs D of each flip-flop_nAnd D'_nRespectively receiving two output signals Q of the previous stage trigger_n-1And Q'_n-1And outputs two pairs of output signals (Q)_n，Q'_n) And (dQ)_n,dQ'_n) (ii) a Wherein the output signal dQ_nAnd dQ'_nAre respectively output signals Q_nAnd Q'_nA delayed signal;

output signal dQ_nAnd dQ_n' is connected to a reset detect detector to reduce the effect of node parasitic capacitance in the ring shift register on the operating frequency range.

In the above-described single-event hardened 7-phase clock generation circuit,

global signal RST_CHECKThe output port of any flip-flop is connected with the set end of any flip-flop in the annular shift register, and the initial state of the output port of any flip-flop is '1';

global signal RST_CHECKAnd the output ports of the other 6 flip-flops except any one flip-flop in the annular shift register are all in an initial state of '0'.

In the single-particle reinforced 7-phase clock generation circuit, a reference clock signal CLKREF is connected with clock input signal ports CK of 7 triggers; when a reference clock signal CLKREF is input, the initial values of the output ports of all the triggers are sequentially shifted through a ring shift register, the output ports of all the triggers are clock signals with the duty ratio of 1:6, the period T of the input reference clock signal CLKRREF is taken as a phase-shifting reference interval, and the output time delays of two adjacent triggers are sequentially differed by T to generate a 7-phase clock signal.

In the above-mentioned single-event reinforced 7-phase clock generation circuit, the flip-flop is: a dual-mode D flip-flop with reset and set functions.

In the above-described single-event hardened 7-phase clock generation circuit, the gated buffer includes: 7 buffers: buffer BUF₆Buffer BUF₅Buffer BUF₄Buffer BUF₃Buffer BUF₂Buffer BUF₁And a buffer BUF₀；

Each buffer receives a phase clock signal, and the received phase clock signal is output after being subjected to deburring processing.

In the above-described single-event hardened 7-phase clock generation circuit, the buffer includes: a two-way gate control unit and an inverting gate; the two-way gate control unit and the inverting gate are composed of PMOS tubes and NMOS tubes; the PMOS tube includes: PM (particulate matter)₁And PM₂The NMOS tube comprises: NM₁And NM₂；

PM₁、PM₂、NM₁And NM₂Sequentially connected in series, one input signal A is connected with PM₁And NM₁Grid, the other input signal B is connected with PM₂And NM₂The grid electrode forms a double-channel gate control unit;

PM₃and NM₃Are connected in series to form an inverting gate;

the output signal C of the two-way gate control unit is connected with the input of the inverting gate, and the inverting gate outputs a signal D.

In the above-described single-event hardened 7-phase clock generation circuit, the reset detector includes: all-0 detection logic unit, multi-1 detection logic unit and first NAND gate N₁And a third inverting gate INV₃And a fourth inverting gate INV₄And a second NAND gate N₂；

An all 0 detection logic unit comprising: a left half adder and a right half adder; the left half adder includes: four first-stage left half-adders HA₁₁、HA₁₂、HA₁₃And HA₁₄Two second-stage left half-adders HA₁₅And HA₁₆A third-stage left half adder HA₁₇And a first inverter gate INV₁(ii) a The right half adder includes: four first-stage right half adders HA₂₁、HA₂₂、HA₂₃And HA₂₄Two second-stage right half adders HA₂₅And HA₂₆A third-stage right half adder HA₂₇And a second inverter INV₂；

First-stage left half adder HA₁₁For use according to VSS ═ 0 and dQ₀Output signal { C₀,S₁}＝0+dQ₀；

Second-stage left half adder HA₁₂According to dQ₁And dQ₂Output signal { C₁,S₁}＝dQ₁+dQ₂；

Third-stage left half adder HA₁₃According to dQ₃And dQ₄Output signal { C₂,S₂}＝dQ₃+dQ₄；

Fourth-stage left half adder HA₁₄According to dQ₅And dQ₆Output signal { C₃,S₃}＝dQ₅+dQ₆；

Second-stage left half adder HA₁₅For according to S₁And S₂Output signal { C₄,S₄}＝S₁+S₂；

Second-stage left half adder HA₁₆For according to S₃And S₄Output signal { C₅,S₅}＝S₃+S₄；

Third-stage left half adder HA₁₇For according to S₅And S₆Output signal { C₆,S₆}＝S₅+S₆；

First-stage right half adder HA₂₁For according to VSS ═ 0 and dQ'₀Output signal { C'₀,S'₀}＝0+dQ'₀；

Second stage right half adder HA₂₂From dQ'₁And dQ'₂Output signal { C'₁,S'₁}＝dQ'₁+dQ'₂；

Third stage right half adder HA₂₃From dQ'₃And dQ'₄Output signal { C'₂,S'₂}＝dQ'₃+dQ'₄；

Fourth-stage right half adder HA₂₄From dQ'₅And dQ'₆Output signal { C'₃,S'₃}＝dQ'₅+dQ'₆；

Second stage right half adder HA₂₅From S'₁And S'₂Output signal { C'₄,S'₄}＝S'₁+S'₂；

Second stage right half adder HA₂₆From S'₃And S'₄Output signal { C'₅,S'₅}＝S'₃+S'₄；

Third stage right half adder HA₂₇From S'₅And S'₆Output signal { C'₆,S'₆}＝S'₅+S'₆；

First inverter gate INV₁For converting the signal S₆Output to the first NAND gate N₁Second inverting gate INV₂For signal S'₆Output to the first NAND gate N₁；

First NAND gate N₁For the signal S₆And signal S'₆Performing NAND logic processing to output signal Y₁To the second NAND gate N₂；

A multi-1 detection logic unit for receiving the carry signal C output by the all-0 detection logic unit₁、C₂、···、C₇、C'₁、C'₂、···、C'₇(ii) a For carry signal C₁、C₂、···、C₇、C'₁、C'₂、···、C'₇Performing AND logic processing to output R_OA signal;

third inverter INV₃R for receiving the output of the multi 1 detection logic unit₀A signal;

fourth inverter INV₄For receiving the third inverting gate INV₃Output signal, output Y₂A signal;

second NAND gate N₂For the first NAND gate N₁Y of the output₁Signal, Y output from fourth inverting gate₂The signals are subjected to NAND logic processing, and a global signal RST is output_CHECK。

In the single-particle reinforced 7-phase clock generating circuit, the half adder consists of an exclusive-or gate and an and gate; wherein S is_nAnd S'_nRepresenting the sum output signal of a half-adder, C_nAnd C'_nRepresenting a half-adder carry signal.

In the above-mentioned single-event reinforced 7-phase clock generation circuit, the 1-more detection logic unit includes: 14 NMOS transistors and one PMOS transistor PM₁₀(ii) a Wherein, 12 NMOS pipes are: NM₁₀、NM₁₁···、NM₁₆、NM'₁₀、NM'₁₁···、NM'₁₆；

NM₁₀And NM'₁₀Connected in series, the gates being connected to carry signals C₀And C'₀；

NM₁₁And NM'₁₁Connected in series, the gates being connected to carry signals C₁And C'₁；

And so on;

NM₁₆and NM'₁₆The tubes are connected in series, and the gates are connected with carry signals C₆And C'₆；

NM₁₀、NM₁₁、···、NM₁₆All the drains of (1) and the signal line R₀Connected to PM₁₀Gate and drain poles and signal line R₀Are connected.

The invention has the following advantages:

(1) the circuit structure is simple and easy to expand.

(2) The working frequency range is wide, and the additional jitter is small.

(3) Loop stability is not required to be considered, and an additional resistance-capacitance device is not required.

(4) The N-phase clock signal is generated, the N-frequency division function can be realized, and the method is very suitable for high-speed SerDes design.

Drawings

FIG. 1 is a schematic structural diagram of a single-event reinforced 7-phase clock generation circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a 7-phase clock signal generated by a single-event-reinforced 7-phase clock generation circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a buffer according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a reset detector according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a half adder according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a multi-1 detection logic unit according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in fig. 1, in this embodiment, the single-event reinforced 7-phase clock generation circuit includes: a ring shift register, a reset detector, and a gated buffer. The annular shift register is used for generating a 7-phase clock signal; the gating buffer is used for carrying out deburring processing on the 7-phase clock signal and then outputting the processed signal so as to drive long wiring of the multiphase clock; and the reset detector is used for inhibiting the clock signal abnormality generated by the annular shift register under the single event effect when the single event effect occurs.

In this embodiment, the ring shift register may specifically include: 7 triggers connected end to end in turn: flip-flop DFF₀Trigger DFF₁Trigger DFF₂Trigger DFF₃Trigger DFF₄Trigger DFF₅And flip-flop DFF₆. Wherein two input terminals D of each flip-flop_nAnd D'_nRespectively receiving two output signals Q of the previous stage trigger_n-1And Q'_n-1And output twoTo the output signal (Q)_n，Q'_n) And (dQ)_n,dQ'_n) (ii) a Wherein the output signal dQ_nAnd dQ'_nAre respectively output signals Q_nAnd Q'_nA delayed signal; output signal dQ_nAnd dQ_n' is connected to a reset detect detector to reduce the effect of node parasitic capacitance in the ring shift register on the operating frequency range.

Preferably, the global signal RST_CHECKThe output port of any flip-flop is connected with the set end of any flip-flop in the annular shift register, and the initial state of the output port of any flip-flop is '1'; global signal RST_CHECKAnd the output ports of the other 6 flip-flops except any one flip-flop in the annular shift register are all in an initial state of '0'.

Preferably, the reference clock signal CLKREF is connected to the clock input signal port CK of the 7 flip-flops; when a reference clock signal CLKREF is input, the initial values of the output ports of all the triggers are sequentially shifted through a ring shift register, the output ports of all the triggers are clock signals with the duty ratio of 1:6, the period T of the input reference clock signal CLKRREF is taken as a phase-shifting reference interval, and the output time delays of two adjacent triggers are sequentially differed by T to generate a 7-phase clock signal.

Preferably, the flip-flop can be a dual-mode D flip-flop with reset and set functionality.

Wherein, when the circuit is powered on, the global RST_CHECKWhen not enabled, each flip-flop outputs node Q_n、Q'_nThe signal being in a set or reset state, RST, respectively_CHECKAfter the enable signal is turned on, the clock signal with the frequency of F will be Q_n、Q'_nThe initial state in the node is shifted in turn, each flip-flop outputs a node Q_n、Q'_nI.e. a clock signal with a 1:6 duty cycle and a frequency of F/7, the signal phase interval T/7 between the output nodes of adjacent flip-flops, and the 7-phase clock waveform is shown in fig. 2.

In this embodiment, the gating buffer may specifically include: 7 buffers: buffer BUF₆Buffer BUF₅Buffer BUF₄Buffer BUF₃Buffer BUF₂Buffer BUF₁And a buffer BUF₀. Each buffer receives a phase clock signal, and the received phase clock signal is output after being deburred. 7 buffers are respectively cascaded at the output of each trigger and used for suppressing the glitch and providing the driving capability.

In this embodiment, the buffer may specifically include: a two-way gate unit and an inverting gate. In fig. 3, the two-way gate control unit and the inverting gate are composed of PMOS transistors and NMOS transistors. The PMOS tube includes: PM (particulate matter)₁And PM₂The NMOS tube comprises: NM₁And NM₂. Specifically, the method comprises the following steps: PM (particulate matter)₁、PM₂、NM₁And NM₂Sequentially connected in series, one input signal A is connected with PM₁And NM₁Grid, the other input signal B is connected with PM₂And NM₂The grid electrode forms a double-channel gate control unit; PM (particulate matter)₃And NM₃Are connected in series to form an inverting gate; the output signal C of the two-way gate control unit is connected with the input of the inverting gate, and the inverting gate outputs a signal D.

Preferably, when the states of the A, B two input signals of the buffer are the same, the level D of the output end is consistent with that of the A, B two input signals; when the A, B input signal level states are opposite, the output end level D maintains the previous state. Transient burrs may appear on one path of the dual-mode trigger affected by the single event, and the transient burrs are filtered after passing through the buffer.

In this embodiment, as shown in fig. 4, the reset detector may specifically include: all-0 detection logic unit, multi-1 detection logic unit and first NAND gate N₁And a third inverting gate INV₃And a fourth inverting gate INV₄And a second NAND gate N₂。

Preferably, the all 0 detection logic unit may specifically include: a left half adder and a right half adder.

The left half adder includes: four first-stage left half-adders HA₁₁、HA₁₂、HA₁₃And HA₁₄Two second-stage left half-adders HA₁₅And HA₁₆1 toA third-stage left half adder HA₁₇And a first inverter gate INV₁。

The right half adder includes: four first-stage right half adders HA₂₁、HA₂₂、HA₂₃And HA₂₄Two second-stage right half adders HA₂₅And HA₂₆A third-stage right half adder HA₂₇And a second inverter INV₂。

Specifically, the method comprises the following steps:

first-stage left half adder HA₁₁For use according to VSS ═ 0 and dQ₀Output signal { C₀,S₁}＝0+dQ₀。

Second-stage left half adder HA₁₂According to dQ₁And dQ₂Output signal { C₁,S₁}＝dQ₁+dQ₂。

Third-stage left half adder HA₁₃According to dQ₃And dQ₄Output signal { C₂,S₂}＝dQ₃+dQ₄。

Fourth-stage left half adder HA₁₄According to dQ₅And dQ₆Output signal { C₃,S₃}＝dQ₅+dQ₆。

Second-stage left half adder HA₁₅For according to S₁And S₂Output signal { C₄,S₄}＝S₁+S₂。

Second-stage left half adder HA₁₆For according to S₃And S₄Output signal { C₅,S₅}＝S₃+S₄。

Third-stage left half adder HA₁₇For according to S₅And S₆Output signal { C₆,S₆}＝S₅+S₆。

First-stage right half adder HA₂₁For according to VSS ═ 0 and dQ'₀Output signal { C'₀,S'₀}＝0+dQ'₀。

Second stage right half adder HA₂₂For according to dQ'₁And dQ'₂Output signal { C'₁,S'₁}＝dQ'₁+dQ'₂。

Third stage right half adder HA₂₃From dQ'₃And dQ'₄Output signal { C'₂,S'₂}＝dQ'₃+dQ'₄。

Fourth-stage right half adder HA₂₄From dQ'₅And dQ'₆Output signal { C'₃,S'₃}＝dQ'₅+dQ'₆。

Second stage right half adder HA₂₅From S'₁And S'₂Output signal { C'₄,S'₄}＝S'₁+S'₂。

Second stage right half adder HA₂₆From S'₃And S'₄Output signal { C'₅,S'₅}＝S'₃+S'₄。

Third stage right half adder HA₂₇From S'₅And S'₆Output signal { C'₆,S'₆}＝S'₅+S'₆。

First inverter gate INV₁For converting the signal S₆Output to the first NAND gate N₁Second inverting gate INV₂For signal S'₆Output to the first NAND gate N₁。

First NAND gate N₁For the signal S₆And signal S'₆Performing NAND logic processing to output signal Y₁To the second NAND gate N₂。

A multi-1 detection logic unit for receiving the carry signal C output by the all-0 detection logic unit₁、C₂、···、C₇、C'₁、C'₂、···、C'₇(ii) a For carry signal C₁、C₂、···、C₇、C'₁、C'₂、···、C'₇Performing AND logic processing to output R_OA signal.

Third inverter INV₃For receivingR output by multi-1 detection logic unit₀A signal.

Fourth inverter INV₄For receiving the third inverting gate INV₃Output signal, output Y₂A signal.

Second NAND gate N₂For the first NAND gate N₁Y of the output₁Signal, Y output from fourth inverting gate₂The signals are subjected to NAND logic processing, and a global signal RST is output_CHECK。

Preferably, the output signals of the flip-flops are added through a half adder chain, and the connection modes of the left half adder chain and the right half adder chain are consistent. As in fig. 5, each half-adder consists of an exclusive or gate XOR AND an AND gate AND. Wherein, S (S)_nAnd S'_n) Representing the sum output signal of the half-adder, C (C)_nAnd C'_n) Representing a half-adder carry signal.

Further, the left and right groups of half adder chains output S₆And S'₆While each half adder outputs a carry signal C_nWhen the circuit works normally, 7 flip-flops output clock signals and pass through a half adder chain to obtain S₆And S₆' signal sum is constant ' 1 ', each half adder carry signal C_nIs constantly "0", at this time RST_CHECKThe signal output is a constant 0. Under the space radiation environment, under the influence of single particles, more than one '1' or all '0' condition may appear in the original stable 1:6 duty ratio signal, which causes the clock signal to be disordered, and at the moment, the reset detector can detect the abnormal state of the clock signal and generate a reset signal. E.g. more than one "1" state per cycle in a 7-phase clock signal, e.g. "1010000", the corresponding half-adder outputs a carry signal C₂And C'₂Output "1", multiple "1" detection logic is C₂And C'₂The controlled NMOS switch is conducted to pull the potential of the drain terminal of the PMOS connected with the diode low, and RST is carried out after the potential of the drain terminal of the PMOS passes through the buffer and the NAND gate_CHECKPulling high to carry out global reset, and restoring 7 triggers to an initial reset or set state, so that the loop begins to be reestablished; if the clock of 7 phases is "0" every cycle, i.e., "0000000", the half adder chain outputs S₆、S'₆Are all '0', RST is sent through an inverter and a NAND gate_CHECKThe signal is pulled "high" to perform a global reset and the loop begins to re-establish. The factors such as delay difference of 7-phase clock reaching the half adder after layout wiring, competition generated by a combinational logic unit, hazard and the like can cause the reset detector to output narrow pulse width burrs, and in order to ensure that the reset signal is not interfered during normal work, the reset detector outputs a signal RST_CHECKThe end is added with a 0.5pF filter capacitor CAP₀The glitch is suppressed and the reset is prevented from being triggered by mistake.

Preferably, as shown in fig. 6, the multi-1 detection logic unit may specifically include: 14 NMOS transistors and one PMOS transistor PM₁₀(ii) a Wherein, 12 NMOS pipes are: NM₁₀、NM₁₁···、NM₁₆、NM'₁₀、NM'₁₁···、NM'₁₆. Specifically, the method comprises the following steps: NM₁₀And NM'₁₀Connected in series, the gates being connected to carry signals C₀And C'₀；NM₁₁And NM'₁₁Connected in series, the gates being connected to carry signals C₁And C'₁(ii) a And so on; NM₁₆And NM'₁₆The tubes are connected in series, and the gates are connected with carry signals C₆And C'₆。NM₁₀、NM₁₁、···、NM₁₆All the drains of (1) and the signal line R₀Connected to PM₁₀Gate and drain poles and signal line R₀Are connected.

In summary, in the present embodiment, the ring shift register consists of 7D flip-flops (DFFs) with set and reset functions₆、DFF₅、DFF₄、DFF₃、DFF₂、DFF₁、DFF₀) The method comprises the steps that through setting the setting or resetting state of each D trigger at the initial stage, one D trigger is set to be in the setting '1' state, the other 6D triggers are set to be in the resetting '0' state, when a high-speed reference clock is input from the outside, the initial value of each D trigger is shifted through a shift register link, each D trigger outputs a clock signal with the frequency of F/7 and the duty ratio format of 1:6, and the phase interval of T/7 is formed between the output signals of the adjacent D triggers. Shift register chainThe middle D flip-flops adopt a mature dual-mode reinforced structure, and the output of each D flip-flop is cascaded with a gating buffer, namely 7-phase clock signals CK0, CK1, CK2, CK3, CK4, CK5 and CK 6. The reset detector employs a dual mode half-adder architecture including all '0' detection logic and multiple '1' detection logic. The error states possibly existing in the 7-phase clock signals comprise full '0' and more '1', the outputs of the 7-phase clock signals are added through a dual-mode half adder chain, the addition output of the dual-mode half adder chain generates a reset signal, and full '0' detection is realized; and the carry signal of each half adder is matched with the NMOS series switch to generate a reset signal, so that the multi-1 detection is realized.

Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.

Those skilled in the art will appreciate that the invention may be practiced without these specific details.