阅读说明：本技术 一种无频率损耗的集成电路抗单粒子翻转加固方法 (Frequency-loss-free integrated circuit single event upset resistance reinforcing method ) 是由 宋睿强 邵津津 刘必慰 吴振宇 梁斌 池雅庆 陈建军 于 2020-12-24 设计创作，主要内容包括：本发明公开一种无频率损耗的集成电路抗单粒子翻转加固方法,步骤包括：S1.获取目标集成电路中所有的触发器；S2.遍历获取的所有触发器进行判断,每次判断时对当前触发器所在的数据通路进行静态时序分析,计算出数据通路的时序余量,并计算将当前触发器替换为所需的加固触发器后建立时间参数的增量值以及CLK-Q延时的增量值,根据当前触发器对应的时序余量与增量值之间的差值判断当前触发器是否为所需筛选出的目的触发器；S3.将步骤S2筛选出的所有目的触发器替换为加固触发器,得到加固后的集成电路。本发明能够抗单粒子翻转,同时能够保持集成电路工作频率不变,实现无频率损耗。(The invention discloses a frequency-loss-free integrated circuit single event upset resistance reinforcing method, which comprises the following steps: s1, acquiring all triggers in a target integrated circuit; s2, all the triggers obtained through traversal are judged, static time sequence analysis is carried out on a data path where the current trigger is located during each judgment, time sequence allowance of the data path is calculated, an increment value of a time parameter and an increment value of CLK-Q time delay are established after the current trigger is replaced by a needed reinforced trigger, and whether the current trigger is a target trigger needing to be screened is judged according to a difference value between the time sequence allowance and the increment value corresponding to the current trigger; and S3, replacing all the target triggers screened in the step S2 with reinforced triggers to obtain the reinforced integrated circuit. The invention can resist single event upset, can keep the working frequency of the integrated circuit unchanged and realize no frequency loss.)

1. A frequency-loss-free integrated circuit single event upset resistance reinforcing method is characterized by comprising the following steps:

s1, trigger acquisition: acquiring all triggers in a target integrated circuit;

s2, screening triggers: traversing all acquired triggers to judge, performing static time sequence analysis on a data path where a current trigger is located during each judgment, calculating time sequence allowance of the data path, calculating an increment value of a set-up time parameter and a CLK-Q delay parameter after the current trigger is replaced by a needed reinforced trigger, wherein the CLK-Q delay parameter is the delay from a clock end CLK of the trigger to an output end Q, and judging whether the current trigger is a target trigger needing to be screened according to a difference value between the time sequence allowance corresponding to the current trigger and the increment value;

s3, reinforcing the trigger: and replacing all the target triggers screened in the step S2 with the reinforced triggers to obtain the reinforced integrated circuit.

2. The method for strengthening the immunity to single event upsets of the integrated circuit without frequency loss of claim 1, wherein in step S2, the maximum arrival time required for the data to arrive at the input and output of the flip-flop and the arrival time that must be satisfied at the input and output of the flip-flop are used to respectively calculate a first timing margin for the data to arrive at the input of the current flip-flop and a second timing margin for the data to arrive at the output of the current flip-flop.

3. The method according to claim 2, wherein the step of calculating the first timing margin for the data to reach the input end of the current flip-flop comprises: calculating a first maximum arrival time T required by data to arrive at an input end D of a current trigger through static time sequence analysis_D，arriveAnd calculating a first arrival time T that the input D of the current flip-flop has to satisfy_D，requireAccording to said first maximum arrival time T_D，arriveFirst arrival time T_D，requireObtaining the first time sequence remainder of the data arriving at the input end D of the current triggerQuantity T_D，slack。

4. The method according to claim 2, wherein the step of calculating the second timing margin for the data to reach the output terminal of the current flip-flop comprises: through static time sequence analysis, calculating a second maximum arrival time T required by data from an output end Q of the current trigger to an input end D of the next-stage trigger_Q，arriveAnd calculating a second arrival time T which must be satisfied for the data to arrive at the input end D of the next stage trigger from the output end Q of the current trigger_Q，requireAccording to said second maximum arrival time T_Q，arriveSecond arrival time T_Q，_requireObtaining a second time sequence margin T of the data reaching the output end Q of the trigger_Q，slack。

5. The method for reinforcing the integrated circuit without the frequency loss against the single event upset according to any one of claims 1 to 4, wherein in the step S2, the specific calculation steps of the increment value are as follows: respectively obtaining the establishing time parameters and the CLK-Q time delay parameters of the current trigger and the reinforcement trigger, subtracting the establishing time parameters between the current trigger and the reinforcement trigger to obtain an increment value delta T of the establishing time parameters after the reinforcement trigger is replaced by the needed reinforcement trigger_setupAnd subtracting the CLK-Q delay parameters between the current trigger and the hardened trigger to obtain an increment value of the CLK-Q delay parameters after the current trigger is replaced by the needed hardened trigger.

6. The method for reinforcing single event upset resistance of the integrated circuit without frequency loss according to any one of claims 1 to 4, wherein in the step S2, the step of judging whether the current trigger is a target trigger to be screened specifically comprises: if the increment value corresponding to the established delay parameter is smaller than the first timing allowance T of the current trigger_D，slackAnd the increment value of the CLK-Q delay parameter is less than the secondTiming margin T_Q，slackIf yes, the current trigger is judged to be the target trigger needing to be screened, and the first time sequence margin T is added_D，slackThe second timing margin T is the timing margin when the data reaches the input end D of the current trigger_Q，slackIs the timing margin for data to arrive at the flip-flop output Q.

7. The method for strengthening the resistance to the single event upset of the integrated circuit without the frequency loss according to any one of claims 1 to 4, wherein the strengthened trigger is a trigger having the same driving capability as a trigger in a target integrated circuit and having the resistance to the single event upset.

Technical Field

The invention relates to the technical field of large-scale integrated circuit design, in particular to a single event upset resistance reinforcing method for an integrated circuit without frequency loss.

Background

In the universe space, a large number of high-energy particles exist, and the integrated circuit can generate single-particle transient pulses after being bombarded by the high-energy particles. For example, when a single-event transient pulse is generated at a node of a cross-interlock inverter circuit of a flip-flop unit, a data value of one node is changed to cause a data value of another node to be changed, and finally, a data value stored in a time sequence unit is changed, so that the stored data is erroneous to cause a single-event upset effect. The single event upset effect changes the data values stored in the integrated circuit timing unit, which can cause the integrated circuit to execute erroneous instructions or read erroneous data, thereby affecting the normal operation of the integrated circuit.

In order to alleviate the influence of the single event upset effect on the normal operation of the integrated circuit, a reinforcement method is required to be adopted in the design process of the integrated circuit to prevent the single event upset. For the reinforcement of integrated circuits, the following two methods are mainly adopted in the prior art:

one type of reinforcement method is to use redundant reinforcement structures, such as cross-interlock flip-flop cell structures, dual-modular redundant flip-flop structures, triple-modular redundant flip-flop structures, and the like. However, the reinforcing method introduces part of redundant logic, which reduces the working frequency of the trigger unit and increases the unit area of the trigger unit;

the other is directed to a static memory sequential circuit, which is most sensitive to the single event upset effect due to the large sensitive area and the small node capacitance. The reinforcing method adopts the bit crossing and error correction and detection coding technology, and improves the single event upset resistance of the static memory circuit. Similarly, due to the addition of circuits such as error correction and detection, the reinforcing method can reduce the operating frequency of the static memory sequential circuit and increase the circuit area of the circuit.

For large scale integrated circuits, the maximum operating frequency is determined by the critical data path in the circuit. In the stage of integrated circuit design, the critical data path usually just meets the timing requirement of the circuit, and no more timing margin remains. At this time, if the conventional single event upset immunity method is still adopted, due to the reduction of the working frequency of the flip-flop, the critical data path timing violation is caused, so that the working frequency of the whole integrated circuit is reduced, which is not acceptable for the frequency sensitive integrated circuit. Therefore, it is desirable to provide a method for reinforcing an integrated circuit against single event upset, so as to prevent single event upset, and simultaneously maintain the operating frequency of the integrated circuit unchanged, thereby achieving no frequency loss.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the reinforcement method for resisting the single event upset of the integrated circuit, which is simple in implementation method, can resist the single event upset, can keep the working frequency of the integrated circuit unchanged, and realizes no frequency loss.

In order to solve the technical problems, the technical scheme provided by the invention is as follows:

a frequency-loss-free integrated circuit single event upset resistance reinforcing method comprises the following steps:

s1, trigger acquisition: acquiring all triggers in a target integrated circuit;

s2, screening triggers: traversing all acquired triggers to judge, performing static time sequence analysis on a data path where a current trigger is located during each judgment, calculating time sequence allowance of the data path, calculating an increment value of a set-up time parameter and a CLK-Q delay parameter after the current trigger is replaced by a needed reinforced trigger, wherein the CLK-Q delay parameter is the delay from a clock end CLK of the trigger to an output end Q, and judging whether the current trigger is a target trigger needing to be screened according to a difference value between the time sequence allowance corresponding to the current trigger and the increment value;

s3, reinforcing the trigger: and replacing all the target triggers screened in the step S2 with the reinforced triggers to obtain the reinforced integrated circuit.

Further, in step S2, a first timing margin for the data to arrive at the input terminal of the current flip-flop and a second timing margin for the data to arrive at the output terminal of the current flip-flop are calculated respectively by using the maximum arrival time required for the data to arrive at the input terminal and the output terminal of the flip-flop and the arrival times that must be satisfied at the input terminal and the output terminal of the flip-flop.

Further, the step of calculating the first timing margin for the data to arrive at the input terminal of the current flip-flop comprises: calculating a first maximum arrival time T required by data to arrive at an input end D of a current trigger through static time sequence analysis_D，arriveAnd calculating a first arrival time T that the input D of the current flip-flop has to satisfy_D，requireAccording to said first maximum arrival time T_D，arriveFirst arrival time T_D，requireObtaining a first timing margin T of data arriving at an input end D of a current trigger_D，slack。

Further, the step of calculating a second timing margin for the data to reach the current flip-flop output includes: through static time sequence analysis, calculating a second maximum arrival time T required by data from an output end Q of the current trigger to an input end D of the next-stage trigger_Q，arriveAnd calculating a second arrival time T which must be satisfied for the data to arrive at the input end D of the next stage trigger from the output end Q of the current trigger_Q，requireAccording to said second maximum arrival time T_Q，arriveSecond arrival time T_Q，requireObtaining a second time sequence margin T of the data reaching the output end Q of the trigger_Q，slack。

Further, in step S2, the specific calculation step of the increment value is: obtaining the establishment of a current trigger and the reinforcement trigger, respectivelyTime parameter and the CLK-Q time delay parameter, subtracting the establishing time parameter between the current trigger and the reinforcement trigger to obtain an increment value delta T of the establishing time parameter after the reinforcement trigger is replaced by the needed reinforcement trigger_setupAnd subtracting the CLK-Q delay parameters between the current trigger and the hardened trigger to obtain an increment value of the CLK-Q delay parameters after the current trigger is replaced by the needed hardened trigger.

Further, in step S2, the step of determining whether the current trigger is a target trigger to be screened specifically includes: if the increment value corresponding to the set-up time parameter is less than the first timing margin T of the current trigger_D，slackAnd the increment value of the CLK-Q delay parameter is less than a second timing margin T_Q，slackIf yes, the current trigger is judged to be the target trigger needing to be screened, and the first time sequence margin T is added_D，slackThe second timing margin T is the timing margin when the data reaches the input end D of the current trigger_Q，slackIs the timing margin for data to arrive at the flip-flop output Q.

Furthermore, the reinforced trigger is specifically selected from triggers with the same driving capability as the trigger in the target integrated circuit and the single event upset effect resistance function.

Compared with the prior art, the invention has the advantages that:

1. according to the invention, the time sequence allowance on each data path of the integrated circuit is obtained by performing static time sequence analysis on the data path of the integrated circuit, the trigger needing to be reinforced is screened out based on the time sequence allowance on the data path and the increment value of the parameter after the trigger is replaced by the reinforced trigger, and then the screened trigger is replaced by the reinforced trigger, so that the proper position of the integrated circuit needing to use the reinforced trigger can be selected according to the time sequence allowances of different data paths, the single event upset resistance of the integrated circuit can be improved, and no frequency loss can be realized.

2. According to the invention, the trigger unit is selectively replaced by the reinforced trigger unit according to the time sequence allowance of different data paths, so that each level of data path of the integrated circuit still meets the static time sequence requirement after the reinforced trigger unit is used, the integrated circuit can still normally work under the original frequency, meanwhile, the single event upset resistance of the integrated circuit is improved, and the method is particularly suitable for large-scale integrated circuits with less time sequence allowance.

Drawings

Fig. 1 is a schematic flow chart illustrating an implementation process of the single event upset resistance strengthening method for the integrated circuit without frequency loss in this embodiment.

Fig. 2 is a schematic diagram of circuit structures of an nth stage flip-flop to an N +2 th stage flip-flop in an embodiment of specific application.

Fig. 3 is a schematic circuit diagram of the circuit structure from the N-th stage flip-flop to the N + 2-th stage flip-flop after the reinforcement in the embodiment of the present invention.

Detailed Description

The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.

As shown in fig. 1, the steps of the method for reinforcing the integrated circuit without frequency loss against single event upset in this embodiment include:

s1, trigger acquisition: acquiring all triggers in a target integrated circuit;

s2, screening triggers: traversing all acquired triggers to judge, performing static time sequence analysis on a data path where a current trigger is located during each judgment, calculating the time sequence allowance of the data path, calculating an increment value of a set-up time parameter and a CLK-Q delay parameter after the current trigger is replaced by a needed reinforced trigger, wherein the CLK-Q delay parameter is the time delay from a clock end CLK of the trigger to an output end Q, and judging whether the current trigger is a target trigger needing to be screened according to the difference value between the time sequence allowance and the increment value corresponding to the current trigger;

s3, reinforcing the trigger: and replacing all the target triggers screened out in the step S2 with reinforced triggers to obtain the reinforced integrated circuit.

In the embodiment, the static time sequence analysis is performed on the integrated circuit data path to obtain the time sequence allowance on each data path of the integrated circuit, the trigger needing to be reinforced is screened out based on the time sequence allowance on the data path and the increment value of the parameter after the trigger is replaced by the reinforced trigger, the screened trigger is replaced by the reinforced trigger, the trigger unit can be replaced by the reinforced trigger unit according to the time sequence allowance selection of different data paths, and it is ensured that each level of the integrated circuit data path still meets the static time sequence requirement after the trigger unit is replaced, so that the working frequency of the integrated circuit is ensured to be unchanged, namely, the integrated circuit still can normally work under the original frequency, meanwhile, the single event upset resistance of the integrated circuit can be improved, and no frequency loss is realized.

In step S1, the cell names of all level flip-flops may be obtained by the physical design tool of the integrated circuit. And traversing each trigger after all the triggers are obtained, performing static time sequence analysis on the data paths of each trigger by using a static time sequence analysis tool, and calculating the time sequence allowance of each data path.

In step S2, the maximum arrival time required for the data to reach the input and output of the flip-flop and the arrival times that the input and output of the flip-flop have to meet are used to calculate the timing margin for the data to reach the input of the current flip-flop and the timing margin for the data to reach the output of the current flip-flop, respectively.

The specific step of calculating the timing margin when the data reaches the input end of the current trigger comprises the following steps: calculating a first maximum arrival time T required by data to arrive at an input end D of a current trigger through static time sequence analysis_D，arriveAnd calculating a first arrival time T that the input D of the present flip-flop has to meet, according to the operating frequency of the circuit_D，requireAccording to a first maximum arrival time T_D，arriveFirst arrival time T_D，requireObtaining a first timing margin T of data arriving at an input end D of a current trigger_D，slack. In particular the first arrival time T that the current flip-flop input D has to meet_D，requireMinus the first maximum arrival time T_D，arriveThat is, the data arrives at the input end D of the current triggerFirst timing margin T_D，slack。

The specific step of calculating the timing margin when the data reaches the output end of the current trigger comprises the following steps: through static time sequence analysis, calculating a second maximum arrival time T required by data from an output end Q of the current trigger to an input end D of the next-stage trigger_Q，arriveAnd calculating a second arrival time T which is required to be satisfied when data arrives at the input end D of the next stage trigger from the output end Q of the current trigger according to the working frequency of the circuit_Q，requireAccording to the second maximum arrival time T_Q，_arriveSecond arrival time T_Q，requireObtaining a second time sequence margin T of the data reaching the output end Q of the trigger_Q，slack. In particular to a second arrival time T which must be satisfied for the next stage of flip-flop input D_Q，requireMinus a second maximum arrival time T_Q，arriveObtaining a second time sequence margin T of the data reaching the output end Q of the trigger_Q，slack。

In step S2 of this embodiment, the specific calculation steps of the increment value are: respectively obtaining the establishing time parameters of the current trigger and the reinforcement trigger and the CLK-Q time delay parameters, subtracting the establishing time parameters between the current trigger and the reinforcement trigger to obtain the increment value delta T of the establishing time parameters after the reinforcement trigger is replaced by the needed reinforcement trigger_setupAnd subtracting the CLK-Q delay parameters between the current trigger and the hardened trigger to obtain an increment value of the CLK-Q delay parameters after the current trigger is replaced by the needed hardened trigger. And subsequently screening all triggers needing reinforcement by combining the time sequence allowance and the size relationship between the increment values.

In step S2 of this embodiment, the specific steps of determining whether the current trigger is the target trigger to be screened are: if the increment value of the corresponding establishment time parameter is less than the first timing allowance T of the current trigger_D，slackAnd the increment value of the CLK-Q delay parameter is less than a second timing margin T_Q，slackIf the current trigger is the target trigger needing to be screened, namely the trigger needing to be replaced by the reinforced trigger, the first timing margin T_D，slackThe timing margin for data arriving at input D of the current flip-flop, the second timing margin T_Q，slackIs the timing margin for data to arrive at the flip-flop output Q.

In this embodiment, the reinforcing trigger may specifically select a trigger having the same driving capability as the trigger in the target integrated circuit and having a function of resisting a single event upset, so that the reinforcing function of resisting the single event upset can be performed at a position where the reinforcing trigger is used, and the performance of resisting the single event upset of the integrated circuit is improved.

Referring to fig. 1, the detailed process for implementing the single event upset resistance reinforcement of the integrated circuit in this embodiment is as follows:

step S1, in the physical design stage of the integrated circuit, all the trigger unit names used in the target integrated circuit are extracted;

step S2, traversing all acquired triggers for judgment;

s21, selecting one trigger, and calculating first maximum arrival time T required by data to arrive at an input end D of the trigger through a static time sequence analysis tool_D，arriveAnd calculating a first arrival time T which must be satisfied for the data to arrive at the input end D of the current trigger by a static time sequence analysis tool according to the working frequency of the circuit_D，requireObtaining the first time sequence allowance T of the data arriving at the input end D of the current trigger_D，slack；

S22, calculating a second maximum arrival time T required by the data of the currently selected trigger to arrive at the input end D of the next-stage trigger from the output end Q of the trigger through a static time sequence analysis tool_Q，arriveAnd according to the working frequency of the circuit, calculating the arrival time T which is required to be satisfied when the data starts from the output end Q of the current trigger and arrives at the input end D of the next trigger by using a static time sequence analysis tool_Q，requireObtaining a second timing margin T of data arriving at the output end Q of the trigger_Q，slack；

S23, selecting a reinforced trigger with the same driving capability as the current trigger, and respectively obtaining the setup time parameters and the CLK-Q delay of the two triggersTime parameter, and subtracting the two establishing time parameters to obtain the increment value delta T of the establishing time parameter after replacing the strengthening trigger_setupSubtracting the two CLK-Q delay parameters to obtain an increment value of the CLK-Q delay parameters which are replaced by the reinforced trigger;

s24, judging the relation between the increment value and the time sequence allowance, and if the increment value delta T of the parameter is established_setupLess than a first timing margin T_D，slackAnd the increment value of the CLK-Q delay parameter is less than a second timing margin T_Q，slackJudging that the current trigger can be replaced by a reinforced trigger;

and S25, repeating the steps S22-S24 until all triggers in the integrated circuit are traversed, and determining the number and the names of the triggers which can be replaced by the reinforced triggers.

And step 3: in the physical design tool, a unit capable of being replaced by a reinforcement trigger is replaced by a corresponding reinforcement trigger, physical placement and physical connection of the replacement unit are completed, a reinforced circuit layout is obtained, and reinforcement of the circuit for resisting single event upset is completed.

The present embodiment further describes the present invention by taking the method for reinforcing the integrated circuit against single event upset as an example in the specific application embodiment. As shown in fig. 2, for the circuit from the nth stage flip-flop to the N +2 th stage flip-flop, the detailed implementation flow is as follows:

step 1) obtaining unit names FF4 and FF5 of an N +1 level trigger through an integrated circuit physical design tool;

step 2) in the static timing analysis tool, the data arrival time and the data must arrival time to the flip-flops FF4 and FF5 are calculated respectively.

The embodiment specifically adopts a simplified calculation method to illustrate the implementation process of the invention:

the data paths reaching the input end of the FF4 are four in total and are FF1/U2/U5, FF2/U1/U2/U5, FF2/U1/U3/U5 and FF3/U3/U5 respectively. As seen from the number of cells, the number of cells on the second data path FF2/U1/U2/U5 and the third data path FF2/U1/U3/U5 are the most paired, and the delay of the XOR gate unit of U3 is larger than that of the XOR gate unit of U2, so that the maximum delay data path reaching the input end of FF4 is FF 2/U1/U3/U5.

For the sake of calculation, assuming that the cell delay of the flip-flop FF2 is 100 picoseconds, the cell delay of the U1 is 50 picoseconds, the cell delay of the U3 is 150 picoseconds, and the cell delay of the U5 is 100 picoseconds, the arrival time of data at the input of the FF4 is the sum of the cell delays, i.e., 400 picoseconds. By the same method, the maximum delay data path of data reaching the input end of FF5 is FF 3/U4/U6. Assuming 100 picosecond delay for the cell of flip-flop FF3, 100 picoseconds delay for the cell of U4, and 100 picoseconds delay for the cell of U6, the arrival time of data at the input of FF5 is the sum of the cell delays, i.e., 300 picoseconds.

Assume that the operating frequency of the circuit of fig. 2 is 2GHz, i.e., one clock cycle is 500 picoseconds, while assuming that the setup times of flip-flops FF4 and FF5 are both 50 picoseconds. Then the arrival time that must be satisfied for data to reach FF4 and FF5 cells is 450 picoseconds. By subtracting the times calculated in the above two steps, the timing margin to the input terminal of the FF4 cell is 50 picoseconds, and the timing margin to the input terminal of the FF5 cell is 100 picoseconds.

Further, in the static timing analysis tool, the data arrival time and the data necessary arrival time of the data arriving at the next stage flip-flops FF6 and FF7 from the output terminals of the flip-flops FF4 and FF5 are calculated, respectively. Since there is only one data path from the output of FF4 to the output of FF6, namely FF4/U7/U9/U11, the most delayed data path from the output of FF4 to the input of FF6 is this path. For the sake of calculation, assuming that the cell delay of the flip-flop FF4 is 100 picoseconds and the cell delays of the U7/U9/U11 are 50 picoseconds, the arrival time of data from the output of FF4 to the input of FF6 is the sum of the cell delays, i.e. 250 picoseconds. In the same way, it can be obtained that the arrival time of data from the output terminal of FF5 to the input terminal of FF7 is 200 picoseconds.

Further, assume that the setup times for flip-flops FF6 and FF7 are both 50 picoseconds. Then the arrival time that data must meet from the FF4 output to the FF6 input is 450 picoseconds. Similarly, the arrival time that data must meet from the output of FF5 to the input of FF7 is also 450 picoseconds. The time calculated by the two steps is subtracted, so that the timing allowance of the output end of the FF4 unit is 200 picoseconds, and the timing allowance of the output end of the FF5 unit is 250 picoseconds.

And 3) assuming that the establishment time of the hardened flip-flop is 150 picoseconds and the delay of the CLK-Q is 250 picoseconds, the establishment time is increased by 100 picoseconds and the delay of the CLK-Q is increased by 150 picoseconds after the FF4 flip-flop is replaced by the hardened flip-flop according to the establishment time of the FF4 and the FF5 and the delay data. Since the timing margin to the input of FF4 is only 50 picoseconds, less the incremental amount of setup time, flip-flop FF4 cannot be replaced with a hardened flip-flop. However, the margin values of FF5 flip-flops are each greater than (or equal to) a corresponding increase, so flip-flop FF5 may be replaced with a hardened flip-flop.

And step 4) replacing the trigger FF5 with a reinforced trigger through an integrated circuit physical design tool, wherein a circuit diagram obtained after the replacement is completed is shown in FIG. 3. And then, the physical placement and physical connection of the replacement units are completed by adopting an integrated circuit physical design tool, and finally the reinforcement of the whole circuit for resisting single event upset is completed.

According to the invention, the trigger unit is replaced by the reinforced trigger unit according to the time sequence allowance of different data paths, so that each level of data path of the integrated circuit still meets the static time sequence requirement after the reinforced trigger unit is used, the integrated circuit is ensured to still work normally under the original frequency, and meanwhile, the single event upset resistance of the integrated circuit is improved.

The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.