阅读说明：本技术 用于航天导航的低相位噪声四倍频时钟生成方法及电路 (Low-phase noise quadruple frequency clock generation method and circuit for aerospace navigation ) 是由 郭瑞 梁晟溟 赵诣 李昌彤 王粟 于 2021-05-21 设计创作，主要内容包括：本发明涉及一种用于航天导航的低相位噪声四倍频时钟生成方法及电路,通过设置放大器工作电压利用放大器非线性区谐波特性,实现对基准时钟源四倍频的功能。本发明实现对高稳时钟源进行四倍频,并通过多级放大器放大与多级滤波网络达到输出低相位噪声时钟信号,时钟相位均方根抖动小于18ps。本发明方法可用于航天导航系统上对发射机上的时钟源进行倍频,产生用于发射频段的整数倍频率伪码和载波信号,解决数字锁相环相位噪声大的问题,保证发射机良好的相位不平衡度。(The invention relates to a low phase noise quadruple frequency clock generation method and a circuit for aerospace navigation, which realize the function of quadruple frequency of a reference clock source by setting the working voltage of an amplifier and utilizing the harmonic characteristic of the nonlinear region of the amplifier. The invention realizes the quadruple frequency of the high-stability clock source, and outputs the clock signal with low phase noise through the amplification of the multistage amplifier and the multistage filter network, and the root mean square jitter of the clock phase is less than 18 ps. The method can be used for frequency multiplication of a clock source on a transmitter on a space navigation system to generate integral multiple frequency pseudo codes and carrier signals for transmitting frequency bands, solves the problem of high phase noise of a digital phase-locked loop, and ensures good phase imbalance of the transmitter.)

1. A low phase noise quadruple frequency clock generation method for aerospace navigation is characterized by comprising the following steps:

(1) a resistor is connected in series with the power supply end of the first-stage amplifier, so that the power supply voltage of the first-stage amplifier is reduced, the first-stage amplifier works in a nonlinear region, and higher harmonics are generated;

(2) the generated higher harmonic is filtered by a band-pass filter to remove the frequency except the fourth harmonic, and the secondary filtering is the first-stage filtering;

(3) and performing second-stage amplification and second-stage filtering on the fourth harmonic to meet the clock power requirement.

2. The method of claim 1, wherein the low phase noise quadruple clock generation method comprises: and the front end of each stage of filter is provided with a matching network to avoid the self-excitation of the amplifier.

3. The method of claim 1, wherein the low phase noise quadruple clock generation method comprises: the single event locking of the first-stage amplifier is prevented through the resistor connected in series with the power supply end of the first-stage amplifier.

4. The method of claim 1, wherein the low phase noise quadruple clock generation method comprises: the power supply end of the second-stage amplifier is connected in series with a resistor to prevent the second-stage amplifier from generating single event locking.

5. A low-phase-noise quadruple-frequency clock generating circuit implemented based on the low-phase-noise quadruple-frequency clock generating method for aerospace navigation according to claim 1, comprising: the input matching circuit, the power supply circuit, the first-stage amplification circuit, the matching network circuit, the first-stage band-pass filter, the second-stage amplification circuit and the second-stage band-pass filter;

the power supply circuit is used for supplying power to the first-stage amplifying circuit and the second-stage amplifying circuit, the input matching circuit is used for adjusting the input impedance of the first-stage amplifying circuit, and a power supply end of the first-stage amplifying circuit is connected with a resistor R3 in series, so that the first-stage amplifying circuit works in a nonlinear area, and output signals comprise high harmonics; after LC impedance matching is carried out on each output harmonic signal through a matching network circuit, the frequency except the fourth harmonic is filtered out through a first-stage band-pass filter BPF 1; the fourth harmonic output by the first-stage band-pass filter is further amplified by the second-stage amplifying circuit to meet the signal amplitude requirement, and the signal amplified by the second-stage amplifying circuit is subjected to LC impedance matching by the matching network circuit and is filtered by the second-stage band-pass filter to obtain a final output clock.

6. The low phase noise quadruple clock generating circuit of claim 5, wherein: the input signal of the first-stage amplifier U1 is a 10.23MHz reference clock with power of 2dBm, the reference clock signal firstly passes through the first-stage amplifier U1, the gain of the first-stage amplifier is 15dBm, the 1dB compression point is 15dBm, the resistor R3 connected in series with the power supply end of the first-stage amplifier U1 is 51 ohm, the working current is 30mA, the power supply voltage is 5V, so that the voltage at the power supply pin of the first-stage amplifier is about 3.5V, and the first-stage amplifier works in a nonlinear area at the moment.

7. The low phase noise quadruple clock generating circuit of claim 5, wherein: the 1dB bandwidth of the first band pass filter is 2MHz, suppressing 60dB at 10.23 MHz.

8. The low phase noise quadruple clock generating circuit of claim 5, wherein: the gain of the second stage amplifier U3 is 28dB, and the resistor R5 connected in series at the power supply end of the second stage amplifier U3 is 22 ohms.

9. The low phase noise quadruple clock generating circuit of claim 5, wherein: the final output clock frequency was 40.92Mhz with a power of 5 dBm.

Technical Field

The invention relates to the field of communication, in particular to a design method of a low-phase noise quadruple frequency clock for aerospace navigation application.

Background

In the aerospace navigation application, a high-stability clock source generates a reference clock, and then the reference clock generates clocks with other frequencies through frequency multiplication and provides the clocks to other equipment, such as a navigation enhancement system for broadcasting navigation ranging signals with enhanced power, so as to improve the anti-interference capability of a ground terminal. The navigation enhancement system is provided with a navigation enhancement transmitter, a reference clock source of the navigation enhancement transmitter is a high-stability clock of 10.23MHz, and pseudo codes, carriers and the like are required to be generated when the navigation enhancement signal is transmitted, so that signals such as navigation messages and the like are subjected to up-conversion processing and transmitted. At this time, clocks such as pseudo codes and carriers need to be adjusted to be in fundamental frequency integer frequency multiplication relation, and the enhanced signals transmitted by the navigation enhanced transmitter need to ensure good phase imbalance degree so that no truncation exists at the 0 phase point.

At present, a digital frequency synthesis chip is adopted in the aspect of clock frequency multiplication, the digital frequency synthesis chip carries out register configuration through an external configuration signal, and a digital clock is output through an internal phase-locked loop. The frequency synthesis chip adopts a digital level standard to identify and multiply the frequency of an input analog clock, the problem of large phase root mean square jitter is inevitable, and the frequency synthesis chip with low phase noise in the market is generally expensive. In addition, the digital frequency synthesis chip needs register configuration, so that the sensitivity to a space environment is high, and the problems of single event upset, locking and the like are easy to occur.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the existing aerospace application environment and meeting the development requirements of low cost and high reliability, a novel low-phase-noise quadruple frequency clock generation method and circuit for aerospace navigation are provided, a quadruple frequency clock is generated based on the characteristic of amplifier nonlinear region resonance, and then the clock is filtered and amplified.

The purpose of the invention is realized by the following technical scheme:

a low phase noise quadruple frequency clock generation method for aerospace navigation comprises the following steps

(1) A resistor is connected in series with the power supply end of the first-stage amplifier, so that the power supply voltage of the first-stage amplifier is reduced, the first-stage amplifier works in a nonlinear region, and higher harmonics are generated;

(2) the generated higher harmonic is filtered by a band-pass filter to remove the frequency except the fourth harmonic, and the secondary filtering is the first-stage filtering;

(3) and performing second-stage amplification and second-stage filtering on the fourth harmonic to meet the clock power requirement.

Furthermore, a matching network is arranged at the front end of each stage of filter to avoid self-excitation of the amplifier.

Furthermore, the single event locking of the first-stage amplifier is prevented through the resistor connected in series with the power supply end of the first-stage amplifier.

Furthermore, the power supply end of the second-stage amplifier is connected in series with a resistor to prevent the second-stage amplifier from single event locking.

Further, the present invention further provides a low phase noise quadruple clock generating circuit, including: the input matching circuit, the power supply circuit, the first-stage amplification circuit, the matching network circuit, the first-stage band-pass filter, the second-stage amplification circuit and the second-stage band-pass filter;

the power supply circuit is used for supplying power to the first-stage amplifying circuit and the second-stage amplifying circuit, the input matching circuit is used for adjusting the input impedance of the first-stage amplifying circuit, and a power supply end of the first-stage amplifying circuit is connected with a resistor R3 in series, so that the first-stage amplifying circuit works in a nonlinear area, and output signals comprise high harmonics; after LC impedance matching is carried out on each output harmonic signal through a matching network circuit, the frequency except the fourth harmonic is filtered out through a first-stage band-pass filter BPF 1; the fourth harmonic output by the first-stage band-pass filter is further amplified by the second-stage amplifying circuit to meet the signal amplitude requirement, and the signal amplified by the second-stage amplifying circuit is subjected to LC impedance matching by the matching network circuit and is filtered by the second-stage band-pass filter to obtain a final output clock.

Further, an input signal of the first-stage amplifier U1 is a 10.23MHz reference clock with a power of 2dBm, the reference clock signal passes through the first-stage amplifier U1, a gain of the first-stage amplifier is 15dBm, a 1dB compression point is 15dBm, a resistor R3 connected in series with a power supply end of the first-stage amplifier U1 is 51 ohms, a working current is 30mA, and a power supply voltage is 5V, so that a voltage at a power supply pin of the first-stage amplifier is about 3.5V, and the first-stage amplifier operates in a nonlinear region.

Further, the 1dB bandwidth of the first band pass filter is 2MHz, and 60dB rejection occurs at 10.23 MHz.

Furthermore, the gain of the second stage amplifier U3 is 28dB, and the resistor R5 connected in series at the power supply end of the second stage amplifier U3 is 22 ohms.

Further, the final output clock frequency was 40.92Mhz and the power was 5 dBm.

Compared with the prior art, the invention has the following beneficial effects:

(1) the invention makes the working voltage of the amplifier enter a nonlinear region by setting the working voltage of the amplifier, so that the harmonic wave is output with the maximum power.

(2) The clock generated by the design of the invention is fourth harmonic of a high-stability clock source, the phase noise is consistent with the clock source, and compared with a digital phase-locked loop, the phase root-mean-square jitter is reduced from 120ps to 18 ps.

(3) The design of the invention does not need program configuration, thereby avoiding the problems that the register configuration is required by software in the traditional digital phase-locked loop and the single event upset is easy to occur in the internal register.

(4) The invention uses the self-characteristic of the amplifier, does not need software configuration, simplifies the system design and improves the reliability.

(5) The method can obviously improve the phase noise, the phase noise is equal to a high-stability clock source, the traditional digital frequency comprehensive frequency multiplication is replaced, and the cost is reduced; meanwhile, the method has a measure for resisting the single event effect, and improves the reliability in the space environment.

Drawings

Fig. 1 is a schematic diagram of the quadruple frequency circuit of the present invention.

Detailed Description

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

Because the frequency multiplication of the clock mostly adopts a digital phase-locked loop mode, the phase of the clock after frequency multiplication is deviated, and the phase consistency of pseudo codes and carriers of a navigation system transmitter is influenced to a great extent.

The theoretical basis of the present invention is to utilize the non-linear region of the amplifier to generate each harmonic of the input signal and then to select the required clock by the filter. In order to enable the amplifier to work in a nonlinear region and generate higher harmonics with higher power, the power supply voltage of the amplifier is reduced by serially connecting a resistor at the power supply end of the amplifier, the generated higher harmonics are filtered by a band-pass filter to remove frequencies except for fourth harmonics, then the fourth harmonics are amplified and filtered to meet the clock power requirement, and a matching network is arranged at the front end of each stage of filter to avoid self-excitation of the amplifier.

Specifically, the invention provides a low-phase-noise quadruple clock generation method for aerospace navigation, which comprises the following steps:

(1) a resistor is connected in series with the power supply end of the first-stage amplifier, so that the power supply voltage of the first-stage amplifier is reduced, the first-stage amplifier works in a nonlinear region, and higher harmonics are generated;

(2) the generated higher harmonic is filtered by a band-pass filter to remove the frequency except the fourth harmonic, and the secondary filtering is the first-stage filtering;

(3) and performing second-stage amplification and second-stage filtering on the fourth harmonic to meet the clock power requirement.

Preferably, a matching network is arranged at the front end of each stage of the filter to avoid self-excitation of the amplifier.

Preferably, the single event locking of the first-stage amplifier is prevented by a resistor connected in series with the power supply terminal of the first-stage amplifier.

Preferably, the power supply terminal of the second stage amplifier is connected in series with a resistor to prevent the second stage amplifier from single event locking.

The method can obviously improve the phase noise, the phase noise is equal to a high-stability clock source, the traditional digital frequency comprehensive frequency multiplication is replaced, and the cost is reduced; meanwhile, the method has a measure for resisting the single event effect, and improves the reliability in the space environment.

Based on the above thought, referring to fig. 1, the invention specifically designs a low-phase-noise quadruple-frequency clock generation circuit for aerospace navigation application, which comprises an input matching circuit, a power supply circuit, a first-stage amplification circuit, a matching network circuit, a first-stage band-pass filter, a second-stage amplification circuit and a second-stage band-pass filter.

The power supply circuit is used for supplying power to the first-stage amplifying circuit and the second-stage amplifying circuit, the input matching circuit is used for adjusting the input impedance of the first-stage amplifying circuit, and a power supply end of the first-stage amplifying circuit is connected with a resistor R3 in series, so that the first-stage amplifying circuit works in a nonlinear area, and output signals comprise high harmonics; after LC impedance matching is carried out on each output harmonic signal through a matching network circuit, the frequency except the fourth harmonic is filtered out through a first-stage band-pass filter BPF 1; the fourth harmonic output by the first-stage band-pass filter is further amplified by the second-stage amplifying circuit to meet the signal amplitude requirement, and the signal amplified by the second-stage amplifying circuit is subjected to LC impedance matching by the matching network circuit and is filtered by the second-stage band-pass filter to obtain a final output clock.

(1) The input signal is a 10.23MHz reference clock with power of 2dBm, the input signal passes through a first-stage amplifier U1, the gain of the first-stage amplifier is 15dBm, the 1dB compression point is 15dBm, a resistor R3 is set to 51 ohm, the working current is 30mA, the power supply voltage is 5V, the voltage at the power supply pin of the first-stage amplifier is about 3.5V, at the moment, the first-stage amplifier works in a nonlinear area, and the output signal comprises various higher harmonics. The series resistor R3 also prevents single event locking of the first stage amplifier.

The working principle is as follows:

according to the operational characteristics of the amplifier:

when the input signal power of the signal amplifier is small, the amplifier works in a linear state, the output signal and the input signal satisfy a linear relation,

such as formula

Vo＝a₀*Vi

Vi＝V₀*coswt

At this time, the frequency of the output signal is the same as that of the input signal, no new frequency component is generated, and the amplifier does not generate nonlinear distortion. Wherein Vo is the amplitude of the output signal of the amplifier,a₀for coefficients, Vi is the amplifier input signal, w is the angular frequency of the signal, V₀Is the input signal amplitude.

When the input signal power of the small-signal amplifier is increased, the amplifier starts to work in a nonlinear state, and the relation between the input and the output is approximate at the moment:

Vo＝a₀*Vi+a₁*Vi²,

changing Vi to V₀Substituting coswt to obtain

Vo＝1/2*a₁*V₀ ²+a₀*V₀coswt+1/2*a₁*a₀ ²cos2wt,

Wherein, a₀a₁The output signal now comprises the second harmonic 2w of the input signal for each coefficient.

The input signal power of the small-signal amplifier is further amplified, and the nonlinear state of the amplifier can be expressed by the following formula:

Vo＝a₀*Vi+a₁*Vi²+a₂Vi³+a₃*Vi⁴is substituted into the formula to obtain

Vo＝1+1/2*a₁*V₀ ²+1/4*a₃*V₀ ⁴+(a₀*V₀+a₂V₀ ³)coswt+(1/2*a₁*V₀ ²+1/2)cos2wt

+1/2*a₂V₀ ³cos3wt+1/8*a₃V₀ ⁴cos4wt

Wherein, a₀a₁a₂a₃The output signal now comprises the fourth harmonic 4w of the input signal for each coefficient.

(2) And after LC impedance matching is carried out on each output harmonic signal, the harmonic signal passes through a first band-pass filter BPF1, the 1dB bandwidth of the first band-pass filter is 2MHz, and 60dB is restrained at 10.23 MHz.

(3) The power of 40.92MHz is reduced to-16 dBm after passing through the first band-pass filter, the signal is further amplified to meet the signal amplitude requirement, and then passes through a second-stage amplifier U3, the second-stage amplifier works in a linear region, the gain of the second-stage amplifier U3 is 28dB, the series resistor R5 at the power supply end is 22 ohms, and the second-stage amplifier is prevented from generating a single particle bolt lock

(4) The clock signal output by the second-stage amplifier passes through LC impedance matching and a second band-pass filter U4, and finally the output clock is 40.92Mhz, and the power is 5 dBm.

The clock generated by the design of the invention is fourth harmonic of a high-stability clock source, the phase noise is consistent with the clock source, and compared with a digital phase-locked loop, the phase root-mean-square jitter is reduced from 120ps to 18 ps.

Meanwhile, the scheme of the invention does not need program configuration, thereby avoiding the problems that the register configuration is required by software in the traditional digital phase-locked loop and the single event upset is easy to occur in the internal register. The design utilizes the self characteristics of the amplifier, does not need software configuration, simplifies the system design and improves the reliability.