阅读说明：本技术 功率放大元件 (Power amplifying element ) 是由 马少骏 梅本康成 佐佐木健次 于 2021-03-24 设计创作，主要内容包括：本发明提供能够抑制电流向晶体管的一部分区域集中并扩大SOA的功率放大元件。在基板上,沿第一方向排列配置多个双极晶体管。与多个双极晶体管的各基极电极对应地设置多个第一电容元件。通过第一电容元件向双极晶体管供给高频信号。与多个双极晶体管的各基极电极对应地设置电阻元件。经由电阻元件,向双极晶体管供给基极偏压。关于与第一方向正交的第二方向,从多个双极晶体管观察时,多个第一电容元件配置在同一侧。从多个双极晶体管观察第二方向时,多个第一电容元件中的至少一个第一电容元件配置于与其它的一个第一电容元件部分地重叠的位置。(The invention provides a power amplification element capable of suppressing current concentration in a partial region of a transistor and enlarging an SOA. A plurality of bipolar transistors are arranged in a first direction on a substrate. A plurality of first capacitance elements are provided corresponding to the base electrodes of the plurality of bipolar transistors. A high-frequency signal is supplied to the bipolar transistor through the first capacitor element. A resistance element is provided corresponding to each base electrode of the plurality of bipolar transistors. A base bias voltage is supplied to the bipolar transistor via the resistance element. The plurality of first capacitive elements are arranged on the same side when viewed from the plurality of bipolar transistors in a second direction orthogonal to the first direction. When the second direction is viewed from the plurality of bipolar transistors, at least one of the plurality of first capacitance elements is disposed at a position partially overlapping with another one of the plurality of first capacitance elements.)

1. A power amplifying element, comprising:

a plurality of bipolar transistors arranged on a substrate in a first direction, each of the bipolar transistors including a collector layer, a base layer, an emitter layer, and at least one base electrode electrically connected to the base layer;

a plurality of first capacitance elements provided corresponding to the base electrodes of the plurality of bipolar transistors, one of the first capacitance elements being connected to the corresponding base electrode, and the other of the first capacitance elements being supplied with a high-frequency signal; and

a plurality of resistance elements provided corresponding to the base electrodes of the plurality of bipolar transistors, one end of each resistance element being connected to the corresponding base electrode and being supplied with a bias voltage from the other end thereof,

a second direction orthogonal to the first direction, the plurality of first capacitance elements being arranged on the same side as the plurality of bipolar transistors,

when the second direction is viewed from the plurality of bipolar transistors, at least one of the plurality of first capacitance elements is disposed at a position partially overlapping with another one of the plurality of first capacitance elements.

2. The power amplifying element according to claim 1,

the plurality of bipolar transistors each include a base electrode, a first capacitance element is arranged corresponding to one of the bipolar transistors,

the first capacitance element connected to one of the plurality of bipolar transistors and the first capacitance element connected to the next one of the plurality of bipolar transistors are arranged at different positions when viewed in the first direction, and are arranged so as to partially overlap when viewed in the second direction from the plurality of bipolar transistors.

3. The power amplifying element according to claim 1 or 2,

the plurality of bipolar transistors each include an emitter mesa layer that is long in the second direction and is disposed in a partial region of an upper surface of the emitter layer,

the at least one base electrode includes a base electrode main portion that is long in the second direction, and the base electrode main portion is arranged at a distance from the emitter mesa layer in the first direction in a plan view.

4. The power amplifying element according to claim 3,

the plurality of first capacitance elements are respectively arranged for each of the base electrode main portions of the base electrodes of the plurality of bipolar transistors.

5. The power amplifying element according to claim 4,

each of the plurality of bipolar transistors includes one emitter mesa layer and two base electrode main portions arranged on both sides of the emitter mesa layer in a plan view.

6. The power amplifying element according to claim 4,

the base electrode of each of said plurality of bipolar transistors comprises three base electrode main portions separated from each other and arranged in said first direction,

in each of the plurality of bipolar transistors, the emitter mesa layer is arranged between a central base electrode main portion and each of two base electrode main portions at both ends,

the first capacitance element connected to the central base electrode main portion is arranged at a position offset in the second direction with respect to the two first capacitance elements connected to the base electrode main portions at both ends, respectively, and is arranged at a position partially overlapping the two first capacitance elements with respect to the first direction.

7. The power amplifying device according to any one of claims 1 to 6,

each of the plurality of first capacitor elements includes three conductor layers, a central conductor layer is connected to a corresponding base electrode, and an upper conductor layer and a lower conductor layer are connected to each other.

8. The power amplifying element according to any one of claims 1 to 7,

further, a plurality of second capacitance elements connected to the base electrodes of the plurality of bipolar transistors,

with respect to the second direction, the plurality of second capacitance elements are arranged on the same side as viewed from the plurality of bipolar transistors,

when the second direction is viewed from the plurality of bipolar transistors, at least one of the plurality of second capacitance elements is disposed at a position partially overlapping with one of the other second capacitance elements.

Technical Field

The present invention relates to a power amplifying element.

Background

A power amplifier circuit for high-frequency signals of a mobile terminal, or the like uses a Heterojunction Bipolar Transistor (HBT) (patent document 1). The power amplifier circuit disclosed in patent document 1 includes a plurality of transistor pairs connected in parallel with each other. Each of the plurality of transistor pairs is formed of two transistors connected in parallel with each other. A capacitor and a ballast resistor are provided corresponding to the plurality of transistor pairs, respectively. The high frequency signal is input to the bases of both transistors of the transistor pair via the capacitor. The bases of both transistors of the transistor pair are supplied with a bias current via a ballast resistor. Since the capacitor and the ballast resistor are arranged for each transistor, the occupied area of the power amplifier circuit can be reduced as compared with the case where the capacitors and the ballast resistor are arranged for each transistor.

The HBTs have respective emitter terminals that are rectangular in plan view, and the base terminals have two base electrode main portions arranged so as to sandwich the emitter terminals in the width direction.

Patent document 1: japanese patent laid-open publication No. 2005-167605

In order to meet the requirements of the fifth generation mobile communication system (5G), high-voltage operation of a bipolar transistor such as an HBT is required. At a high operating voltage exceeding a certain breakdown limit, the HBT may be damaged in a load fluctuation test of the power amplifier circuit. For example, in the power amplifier circuit described in patent document 1, a variation in current occurs between transistors due to a variation in manufacturing of two transistors constituting a transistor pair. The current becomes more concentrated in the transistor through which a relatively large current flows, and the operation becomes unstable.

In addition, in one HBT, a relatively large current may flow on one base electrode main portion side due to asymmetry in the relative positional relationship between the emitter terminal and the base electrode main portions of the two base electrodes on both sides thereof. As the current is concentrated more and more in a region where a relatively large current flows within the HBT, the operation becomes unstable. Due to such instability of the operation, the Safe Operation Area (SOA) becomes narrow. This causes a drawback of a reduction in load fluctuation withstand voltage.

Further, miniaturization of elements of the power amplification circuit is desired.

Disclosure of Invention

The invention aims to provide a power amplification element capable of restraining current from concentrating to a part of the area of a transistor and enlarging an SOA.

According to an aspect of the present invention, there is provided a power amplifying element including:

a plurality of bipolar transistors arranged on the substrate in a first direction, each bipolar transistor including a collector layer, a base layer, an emitter layer, and at least one base electrode electrically connected to the base layer;

a plurality of first capacitance elements provided corresponding to the base electrodes of the plurality of bipolar transistors, one of the first capacitance elements being connected to the corresponding base electrode, and the other of the first capacitance elements being supplied with a high-frequency signal; and

a plurality of resistance elements provided corresponding to the base electrodes of the plurality of bipolar transistors, one end of each resistance element being connected to the corresponding base electrode and a base bias voltage being supplied from the other end,

a second direction orthogonal to the first direction, the plurality of first capacitance elements being arranged on the same side as the plurality of bipolar transistors,

when the second direction is viewed from the plurality of bipolar transistors, at least one of the plurality of first capacitance elements is disposed at a position partially overlapping with another one of the plurality of first capacitance elements.

Since the first capacitive element and the resistive element are disposed in correspondence with the respective base electrodes, it is possible to suppress the bias current and the high-frequency current from concentrating on a specific base electrode. This stabilizes the operation and enlarges the SOA. Further, when the second direction is viewed from the plurality of bipolar transistors, at least one of the first capacitance elements is disposed at a position partially overlapping with one of the other first capacitance elements, and therefore, the size can be reduced as compared with a configuration in which the first capacitance elements are disposed in a line along the first direction.

Drawings

Fig. 1 is a diagram showing a positional relationship in a plan view of two bipolar transistors among a plurality of bipolar transistors constituting a power amplification element according to a first embodiment, and a capacitor element and a resistor element connected to the two bipolar transistors.

Fig. 2 is a sectional view on the chain line 2-2 of fig. 1.

Fig. 3 is a cross-sectional view on the chain line 3-3 of fig. 1.

Fig. 4 is a diagram showing a positional relationship of the respective components of the power amplifying element of the first embodiment when viewed from above.

Fig. 5 is an equivalent circuit diagram of a part of the power amplifying element of the first embodiment.

Fig. 6A and 6B are plan views of two first capacitance elements of the power amplification elements of the first embodiment and the comparative example, respectively.

Fig. 7 is a sectional view of a first capacitor element of the power amplifying element according to the present modification of the first embodiment.

Fig. 8 is a diagram showing a positional relationship in a plan view of two bipolar transistors among a plurality of bipolar transistors constituting a power amplification element according to a second embodiment, and a capacitive element and a resistive element connected to the two bipolar transistors.

Fig. 9 is a diagram showing a positional relationship in a plan view of one bipolar transistor among a plurality of bipolar transistors constituting the power amplification element of the third embodiment, a capacitor element and a resistor element connected to the bipolar transistor.

Fig. 10 is a diagram showing a positional relationship in a plan view of one bipolar transistor among a plurality of bipolar transistors constituting a power amplification element according to a fourth embodiment, a capacitor element and a resistor element connected to the bipolar transistor.

Fig. 11 is a diagram showing a positional relationship in a plan view of two bipolar transistors among a plurality of bipolar transistors constituting a power amplification element according to a fifth embodiment, and a capacitor element and a resistor element connected to the two bipolar transistors.

Fig. 12 is an equivalent circuit diagram of a part of the power amplifying element of the fifth embodiment.

Description of the reference numerals

20 … substrate, 21 … subcollector layer, 22 … element isolation region, 30 … bipolar transistor, 31 … collector layer, 32 … base layer, 33 … emitter layer, 33E … emitter region, 34 … emitter mesa layer, 35 … alloying region, 36 … base mesa layer, 40B … base electrode, 40BF … base electrode main portion, 40BP … base electrode pad portion, 40C … collector electrode, 40E … emitter electrode, 40R … lower electrode, 41B … first layer base wiring, 41Ba, 41Bb … widening portion, 41C … first layer collector wiring, 41E … first layer emitter wiring, 42 … base bias input wiring, 43 … collector common wiring, 51 … first capacitance element, 52 … second capacitance element, 55 … resistance element, 61 … high frequency signal input wiring, 62 … ground wiring, 63 ground wiring 63 … output wiring, 64 … ground wiring, 68 … ground bump, 69 … output bump, 80, 81, 82 … insulating film, 82a … opening.

Detailed Description

[ first embodiment ]

A power amplifying element according to a first embodiment will be described with reference to the drawings of fig. 1 to 6B.

Fig. 1 is a diagram showing a positional relationship in a plan view of two bipolar transistors among a plurality of bipolar transistors constituting a power amplification element according to a first embodiment, and a capacitor element and a resistor element connected to the two bipolar transistors. Fig. 2 is a sectional view on the chain line 2-2 of fig. 1, and fig. 3 is a sectional view on the chain line 3-3 of fig. 1.

In fig. 1, collector electrode 40C, emitter electrode 40E, and base electrode 40B are hatched with a relatively thick right-side upward inclination, first-layer collector wiring 41C, emitter wiring 41E, base wiring 41B, and base bias input wiring 42 are hatched with a relatively thin right-side downward inclination, and resistive element 55 is hatched with a relatively thin right-side upward inclination.

A plurality of subcollector layers 21 (fig. 1 and 2) having n-type conductivity are disposed in a part of the surface of the substrate 20 (fig. 2 and 3). The shape of sub-collector layer 21 in plan view is, for example, a rectangle. The sub-collector layer 21 is formed of, for example, a semiconductor layer epitaxially grown on the substrate 20. The region other than the subcollector layer 21 in the epitaxial growth layer is insulated to become an element isolation region 22 (fig. 2 and 3).

Bipolar transistors 30 are disposed inside the subcollector layers 21 in a plan view. The bipolar transistor 30 is, for example, a Heterojunction Bipolar Transistor (HBT). The bipolar transistor 30 (fig. 2) includes a collector layer 31, a base layer 32, an emitter layer 33, and an emitter mesa layer 34, which are sequentially stacked on the subcollector layer 21. In a plan view, the outer peripheries of the base layer 32 and the emitter layer 33 coincide with the outer periphery of the collector layer 31. The three-layer structure composed of the collector layer 31, the base layer 32, and the emitter layer 33 is referred to as a base mesa layer 36. The base mesa layer 36 has a shape that is long in one direction (the left-right direction in fig. 1) in a plan view.

The emitter mesa layer 34 is disposed inside the emitter layer 33 in plan view. The emitter mesa layer 34 has a shape elongated in the same direction as the longitudinal direction of the base mesa layer 36. The region of the emitter layer 33 that overlaps the emitter mesa layer 34 actually operates as an emitter region 33e (fig. 2) of the bipolar transistor 30. That is, the emitter current flows through the emitter region 33e in the thickness direction. The emitter region 33e has a case called an intrinsic emitter layer. In the emitter layer 33, a region other than the emitter region 33e is substantially depleted, and may be referred to as a barrier layer.

The plurality of bipolar transistors 30 are arranged in a direction orthogonal to the longitudinal direction of the emitter mesa layer 34. In this specification, the direction in which the plurality of bipolar transistors 30 are arranged is referred to as a first direction D1, and the longitudinal direction of the emitter mesa layer 34 is referred to as a second direction D2.

Collector electrode 40C is disposed on subcollector layer 21 at a distance from collector layer 31 in first direction D1. Collector electrode 40C is electrically connected to collector layer 31 via subcollector layer 21.

Emitter electrode 40E is disposed on emitter mesa layer 34 so as to include emitter mesa layer 34 in a plan view. The emitter electrode 40E slightly protrudes to the outside compared to the edge of the emitter mesa layer 34. In the step of patterning emitter mesa layer 34, a self-matching step using emitter electrode 40E as an etching mask is applied. The emitter electrode 40E is electrically connected to the emitter layer 33 via the emitter mesa layer 34.

The base electrode 40B is disposed on the emitter layer 33. The base electrode 40B is electrically connected to the base layer 32 via an alloying region 35 that penetrates the emitter layer 33 and reaches the base layer 32. The base electrode 40B includes one base electrode main portion 40BF and one base electrode pad portion 40 BP. The base electrode main portion 40BF has a shape elongated in the second direction D2 in plan view, and is disposed at a distance from the emitter mesa layer 34 in the first direction D1. Further, the collector electrode 40C, the base electrode main portion 40BF, and the emitter electrode 40E are arranged in this order in the first direction D1. The base electrode pad portion 40BP is continuous with the base electrode main portion 40BF at one end portion of the base electrode main portion 40 BF.

An insulating film 80 (fig. 2) is formed over the entire region of the substrate to cover the bipolar transistor 30, the emitter electrode 40E, the base electrode 40B, and the collector electrode 40C. On this insulating film 80, a first emitter wiring 41E, a collector wiring 41C, a base wiring 41B, and a base bias input wiring 42 are arranged.

The first-layer emitter wiring 41E is arranged to partially overlap the emitter electrode 40E in a plan view. Emitter wiring 41E is connected to emitter electrode 40E through a contact hole provided in insulating film 80 (fig. 2).

The first-layer collector wiring 41C is arranged to partially overlap with the collector electrode 40C in a plan view. The collector wiring 41C is connected to the collector electrode 40C through a contact hole provided in the insulating film 80 (fig. 2). Further, the collector wiring 41C extends from a region overlapping the collector electrode 40C in a plan view to the outside of the sub-collector layer 21 toward one side (the right side in fig. 1) in the second direction D2.

The first-layer base wiring 41B is arranged to partially overlap with the base electrode pad portion 40BP of the base electrode 40B in plan view. The base wiring 41B is connected to the base electrode 40B through a contact hole provided in the insulating film 80 (fig. 2). The base wiring 41B extends from a region overlapping the base electrode pad portion 40BP toward one side (left side in fig. 1) in the second direction D2 to the outside of the sub-collector layer 21 in a plan view. The collector wiring 41C and the base wiring 41B extend toward opposite sides from each other when viewed from the bipolar transistor 30.

The high-frequency signal input wiring 61 extending in the first direction D1 intersects the plurality of base wirings 41B. The high-frequency signal input wiring 61 is arranged in a second-layer wiring layer above the first-layer base wiring 41B, and double-layer insulating films 81 and 82 are arranged therebetween (fig. 3). The insulating film 81 and the insulating film 82 are formed of mutually different insulating materials.

A part of the base wiring 41B is larger in size in the first direction D1 than the other parts. A portion where the size of the first direction D1 is relatively large is referred to as a widened portion 41 Ba. The opening 82A provided in the insulating film 82 is arranged in a region where the widened portion 41Ba overlaps the high-frequency signal input wiring 61 in plan view. The opening 82A is included in the widened portion 41Ba in plan view. Inside the opening 82A, only the insulating film 81 is interposed between the high-frequency signal input wiring 61 and the base wiring 41B. The first capacitive element 51 having the base wiring 41B and the high-frequency signal input wiring 61 as a lower electrode and an upper electrode, respectively, is formed inside the opening 82A in a plan view.

The first capacitive element 51 is connected to the base electrode 40B via the base wiring 41B. A high-frequency signal is supplied from the amplifier circuit or the input terminal of the previous stage to the high-frequency signal input wiring 61. The high-frequency signal supplied to the high-frequency signal input wiring 61 is input to the base electrode 40B via the first capacitive element 51 and the base wiring 41B. The first capacitor element 51 shown in fig. 1 is disposed at a position different from the other first capacitor element 51 when viewed in the first direction D1, and is disposed at a position partially overlapping the other first capacitor element 51 when viewed in the second direction D2 from the plurality of bipolar transistors. Here, "two objects are disposed at different positions when viewed in the X direction" means "two line images obtained by vertically projecting two objects onto a virtual straight line orthogonal to the X direction do not overlap". Further, "two objects are disposed at overlapping positions when viewed in the X direction" means "two line images obtained by vertically projecting two objects onto a virtual straight line orthogonal to the X direction overlap".

Each tip of the base wiring 41B reaches a position farther than the high-frequency signal input wiring 61 as viewed from the bipolar transistor 30. The base wirings 41B are connected to the base bias input wiring 42 via the resistive element 55, respectively. A base bias current is supplied from the base bias input wiring 42 to the base electrode 40B via the base wiring 41B.

Next, an example of the material of each component of the bipolar transistor 30 will be described. For example, a semi-insulating GaAs substrate is used as the substrate 20. The sub-collector layer 21 is formed of, for example, an n-type GaAs layer having a thickness of 400nm or more and 1000nm or less epitaxially grown on the substrate 20. The n-type GaAs layer was doped with silicon (Si) as an n-type dopant at a concentration of 2X 10¹⁸cm^―3Above and 4 × 10¹⁸cm^―3The following. In addition, tellurium (Te) may be used as the n-type dopant instead of Si. The element isolation region 22 is insulated by, for example, implanting boron (B), oxygen (O), helium (He), or the like.

The collector layer 31 is formed of, for example, n-type GaAs doped with Si, and has a thickness of 500nm or more and 2000nm or less. The doping concentration of Si varies in the thickness direction.

The base layer 32 is formed of, for example, p-type GaAs, InGaAs, or GaAsSb doped with carbon (C), and has a thickness of 50nm or more and 150nm or less. The doping concentration of C is 1X 10¹⁹cm^－3Above and at 5X 10¹⁹cm^－3The following. The sheet resistance of the base layer 32 is 130 Ω/□ or more and 300 Ω/□ or less.

The emitter layer 33 is formed of, for example, n-type InGaP doped with Si, and has a thickness of 20nm or more and 50nm or less. The doping concentration of Si is 2X 10¹⁷cm^－3Above and 5 × 10¹⁷cm^－3The following.

Emitter mesa layer 34 includes two layers, a cap layer and a contact layer thereon. The cap layer is formed of n-type GaAs doped with Si, and has a thickness of 50nm to 200 nm. The doping concentration of Si is 2X 10¹⁸cm^－3Above and 4 × 10¹⁸cm^－3The following. The contact layer is formed of Si-doped n-type InGaAs and has a thickness of 100nm to 200 nm. The doping concentration of Si is 1X 10¹⁹cm^－3Above and 3 × 10¹⁹cm^－3The following.

Fig. 4 is a diagram showing a positional relationship of the respective components of the power amplifying element of the first embodiment when viewed from above. The plurality of bipolar transistors 30 are arranged along the first direction D1. In the second direction D2, the common collector wiring 43 is disposed on one side (right side in fig. 4) of the plurality of bipolar transistors 30, and the plurality of first capacitance elements 51 are disposed on the opposite side. The high-frequency signal input wiring 61 is disposed at a position overlapping the plurality of first capacitance elements 51. The collector wirings 41C drawn out from the bipolar transistors 30 to the second direction D2 are continuous with the collector common wiring 43.

When viewed from the plurality of bipolar transistors 30, the plurality of resistance elements 55 are disposed at positions farther than the plurality of first capacitance elements 51. Further, the base bias input wiring 42 common to the plurality of bipolar transistors 30 is disposed at a position farther from the plurality of resistance elements 55 when viewed from the plurality of bipolar transistors 30. The high-frequency signal input wiring 61 and the base bias input wiring 42 extend in the first direction D1.

The output wiring 63 is arranged to overlap the collector common wiring 43 in a plan view. The ground line 62 is arranged to include a plurality of first-layer emitter wirings 41E in a plan view. The output wiring 63 and the ground wiring 62 are disposed in the same second-layer wiring layer as the high-frequency signal input wiring 61. A double layer of insulating films 81 and 82 (fig. 3) is disposed below the output wiring 63 and the ground line 62.

Ground line 62 is connected to emitter wirings 41E through openings provided in insulating films 81 and 82. That is, the plurality of emitter wirings 41E are connected to a common ground line 62. The output wiring 63 is connected to the common collector wiring 43 through openings provided in the insulating films 81 and 82.

The ground bump 68 is configured to be included in the ground line 62 in a plan view. The output bump 69 is disposed to be included in the output wiring 63. As the ground bumps 68 and the output bumps 69, for example, Cu pillar bumps are used. The ground bumps 68 and the output bumps 69 are connected to terminals of a module board or the like. Thereby, the emitter of the bipolar transistor 30 is grounded. The high-frequency signal amplified by the bipolar transistor 30 is output to a module substrate or the like via an output bump 69.

When attention is paid to one bipolar transistor 30 among the plurality of bipolar transistors 30, the first capacitance element 51 connected to the concerned bipolar transistor 30 and the first capacitance element 51 connected to the next bipolar transistor 30 are arranged at different positions when viewed in the first direction D1. When the second direction D2 is viewed from the plurality of bipolar transistors, the two first capacitance elements 51 are arranged to partially overlap.

Fig. 5 is an equivalent circuit diagram of a part of the power amplifying element of the first embodiment. The emitters of the bipolar transistors 30 are connected to the ground 62 (grounded), and the collectors are connected to the output wiring 63. The bases of the plurality of bipolar transistors 30 are connected to the high-frequency signal input wiring 61 via the first capacitive element 51, and are connected to the base bias input wiring 42 via the resistive element 55.

Next, the excellent effects of the first embodiment will be explained.

An operation in the case where a situation (breakdown in uniformity of current) occurs in which the base current (both base bias current and high-frequency current) of one bipolar transistor 30 (fig. 4) is slightly larger than the base current of the other bipolar transistor 30 will be described. In the bipolar transistor 30, when the distance between the emitter mesa layer 34 (fig. 1) and the base electrode main portion 40BF (fig. 1) of the base electrode 40B varies, for example, a collapse in the uniformity of the current may occur.

If the breakdown of the base current uniformity occurs and the base current of a specific one of the bipolar transistors 30 is relatively increased, the voltage drop due to the resistance element 55 (fig. 1) connected to the base electrode 40B of the bipolar transistor 30 is relatively increased. As a result, the potential of the base electrode 40B is relatively lowered. The base current decreases due to the decrease in the potential of the base electrode 40B. This suppresses the expansion of the breakdown in the uniformity of the base current. As a result, collapse of the uniformity of the emitter current is less likely to occur.

In addition, when the base electrode main portions 40BF of the base electrode 40B are disposed on both sides of one emitter mesa layer 34, uniformity of the base current supplied from each of the two base electrode main portions 40BF may be deteriorated in one bipolar transistor 30. Such a situation may arise, for example, in a case where the respective spacings of the two base electrode main portions 40BF from the emitter mesa layer 34 are not the same due to positional shifts within an allowable range in the manufacturing process. If the uniformity of the base current collapses in one bipolar transistor 30, the uniformity of the emitter current also collapses, and the base current is concentrated more and more on one base electrode main portion 40BF due to thermal effects. As a result, the operation becomes unstable.

In contrast, in the first embodiment, only one base electrode main portion 40BF is arranged for one emitter mesa layer 34 (fig. 1). Therefore, the collapse of the uniformity of the base current between the base electrode main portions is not generated.

As described above, in the first embodiment, the power amplification element including the plurality of bipolar transistors 30 operates stably, and the excellent effect of extending the SOA can be obtained. The SOA is enlarged, and thus the bipolar transistor 30 can operate at a high voltage.

Next, the excellent effects of the first embodiment will be described with reference to fig. 6A and 6B.

Fig. 6A and 6B are plan views of two first capacitance elements 51 of the power amplification elements of the first embodiment and the comparative example, respectively. In fig. 6A and 6B, the first capacitance element 51 is hatched. In the first embodiment, a part of the base wiring 41B is widened, and the first capacitance element 51 is arranged in the widened portion 41 Ba. The two first capacitive elements 51 are disposed at different positions when viewed in the first direction D1. In contrast, in the comparative example shown in fig. 6B, the two first capacitance elements 51 are arranged at the same position when viewed in the first direction D1 and are aligned in the first direction D1. The edge of the first capacitive element 51 coincides with the edge of the opening 82A (fig. 3) provided in the insulating film 82.

The lower limit of the wiring interval G1 of the base wiring 41B, the lower limit of the width W1 of the base wiring 41B, the lower limit of the dimension W2 of the opening 82A (i.e., the first capacitive element 51) in the first direction D1, and the lower limit of the alignment margin G2 between the edge of the opening 82A (i.e., the first capacitive element 51) and the edge of the base wiring 41B are determined according to process rules. For example, the lower limit of the gap G1 is 2 μm, the lower limit of the width W1 is 2 μm, the lower limit of the dimension W2 is 2 μm, and the lower limit of the alignment margin G2 is 3 μm.

In the case of the first embodiment (fig. 6A), the lower limit value of the dimension Wt1 in the first direction D1 of the region occupied by the two first capacitive elements 51 is 12 μm. In contrast, in the case of the comparative example (fig. 6B), the lower limit value of the dimension Wt1 in the first direction D1 of the region occupied by the two first capacitance elements 51 is 18 μm. Therefore, in the comparative example, the pitch of the plurality of bipolar transistors 30 in the first direction D1 cannot be made 18 μm or less. In the case of the first embodiment, the pitch in the first direction D1 direction of the plurality of bipolar transistors 30 can be narrowed to 12 μm. This can reduce the size of the power amplification element in the first direction D1.

In the first embodiment, the capacitance of the first capacitive element 51 can be set to a desired value by setting the dimension W2 of the first direction D1 of the first capacitive element 51 to 2 μm as the lower limit value and adjusting the dimension in the second direction D2.

In the first embodiment (fig. 6A), if the dimension Wt1 is set to 18 μm, which is the lower limit of the dimension Wt1 in the comparative example (fig. 6B), the dimension W2 of the first capacitive element 51 in the first direction D1 can be increased to 8 μm. As an example, the area of the first capacitor element 51 is set to 8 × 8 to 64 μm²The conditions of (a) were examined. In the case of the first embodiment, the size of the second direction D2 of the first capacitive element 51 is 8 μm. Therefore, the dimension Wt2 of the second direction D2 of the region occupied by the two first capacitance elements 51 is 30 μm.

In contrast, in the comparative example, since the dimension W2 of the first direction D1 of the first capacitor element 51 is 2 μm, the dimension 64/2 of the second direction D2 needs to be 32 μm. In this way, in the comparative example, in order to secure a desired capacitance under the condition that the dimension Wt1 is as small as possible, the first capacitive element 51 needs to be made thin and long. At this time, the dimension Wt2 of the second direction D2 of the region occupied by the two first capacitance elements 51 is 38 μm.

In this way, with the configuration of the first embodiment, by making the shape of the first capacitance element 51 close to a square, the area of the region occupied by the two first capacitance elements 51 can be reduced as compared with the comparative example. This can reduce the area of the region occupied by the power amplification element.

Next, a modified example of the first embodiment will be described with reference to fig. 7.

Fig. 7 is a sectional view of the first capacitive element 51 of the power amplifying element of the present modification of the first embodiment. In the first embodiment, the base wiring 41B (fig. 3) disposed in the first wiring layer is used as the lower electrode of the first capacitance element 51, and the high-frequency signal input wiring 61 disposed in the second wiring layer is used as the upper electrode of the first capacitance element 51. In the present modification, the first capacitor element 51 has three layers of electrodes.

The high-frequency signal input wiring 61 is used as an upper electrode, and the base wiring 41B is used as a central electrode. The lower electrode 40R is disposed in the same layer as the collector electrode 40C (fig. 2). The lower electrode 40R is disposed between the element isolation region 22 (fig. 3) and the insulating film 80 (fig. 3). The lower electrode 40R is connected to the high-frequency signal input wiring 61 through contact holes provided in the insulating films 80, 81, and 82.

In the present modification, the capacitance per unit area of the first capacitance element 51 can be increased as compared with the first embodiment. Therefore, the area of the region occupied by the first capacitor element 51 can be further reduced.

Next, another modification of the first embodiment will be described.

In order to distinguish the plurality of bipolar transistors 30 arranged in the first direction D1, the numbers are sequentially given from 1. In the first embodiment, the first capacitance elements 51 corresponding to the odd-numbered bipolar transistors 30 are disposed at positions close to the bipolar transistors 30, and the first capacitance elements 51 corresponding to the even-numbered bipolar transistors 30 are disposed at positions distant from the bipolar transistors 30. That is, when attention is paid to one bipolar transistor 30, the first capacitance element 51 connected to the concerned one bipolar transistor 30 is arranged at a position shifted in the second direction D2 with respect to the two first capacitance elements 51 connected to the two adjacent bipolar transistors 30, respectively.

In the present modification, the first capacitive element 51 connected to the concerned one of the bipolar transistors 30 is arranged at a position shifted in the second direction D2 with respect to the first capacitive element 51 connected to the one of the adjacent bipolar transistors 30. The first capacitive element 51 connected to the one bipolar transistor 30 of interest is disposed at the same position as the first capacitive element 51 connected to the opposite-side adjacent bipolar transistor 30 when viewed in the first direction D1. For example, when the second direction D2 is viewed from the plurality of bipolar transistors, the arrangement of two first capacitance elements 51 arranged so as to partially overlap with each other and the arrangement of two first capacitance elements 51 located beside each other are mirror-symmetric with respect to a symmetry axis parallel to the second direction D2.

More generally, at least one first capacitor element 51 of the plurality of first capacitor elements 51 may be disposed at a position where it partially overlaps with another first capacitor element 51 when viewed from the second direction D2 of the plurality of bipolar transistors. By adopting this arrangement, the area of the region occupied by the two first capacitance elements 51 arranged to overlap when viewed in the second direction D2 can be reduced.

[ second embodiment ]

Next, a power amplifying element according to a second embodiment will be described with reference to fig. 8. Hereinafter, the same configuration as that of the power amplifying element of the first embodiment will be omitted.

Fig. 8 is a diagram showing a positional relationship in a plan view of two bipolar transistors among a plurality of bipolar transistors constituting the power amplification element of the second embodiment, and a capacitive element and a resistive element connected to the two bipolar transistors. In the first embodiment, one bipolar transistor 30 (fig. 1, 2) is arranged inside one subcollector layer 21 in a plan view. In contrast, in the second embodiment, two bipolar transistors 30 are arranged inside one subcollector layer 21.

The respective configurations of the bipolar transistors 30 are the same as those of the bipolar transistor 30 of the first embodiment (fig. 1 and 2). That is, the bipolar transistor 30 includes a base mesa layer 36 and an emitter mesa layer 34, respectively. A collector electrode 40C is disposed between the two base mesa layers 36. The first layer collector wiring 41C is connected to the collector electrode 40C. When attention is paid to one bipolar transistor 30, the emitter mesa layer 34 is disposed closer to the collector electrode 40C than the base electrode main portion 40 BF. For example, the two bipolar transistors 30 arranged inside one subcollector layer 21 have a mirror-symmetric relationship in their configurations.

In the first embodiment, the collector electrodes 40C are respectively arranged for the respective bipolar transistors 30, but in the second embodiment, one collector electrode 40C is shared by two bipolar transistors 30. In the second embodiment, as in the first embodiment, the first capacitor element 51 and the resistor element 55 are connected to the two base electrodes 40B, respectively.

Next, the excellent effects of the second embodiment will be explained.

In the second embodiment, since one collector electrode 40C is shared by two bipolar transistors 30, a plurality of bipolar transistors 30 can be arranged in a higher density in the first direction than in the first embodiment. Therefore, the dimension Wt1 (fig. 6A) of the first direction D1 of the area occupied by the two first capacitance elements 51 is smaller than that of the first embodiment.

If the configuration of the comparative example of fig. 6B is adopted under the condition that the dimension Wt1 (fig. 6A and 6B) is small, the first capacitor element 51 needs to be further lengthened in the second direction D2 in order to secure a necessary capacitance. Therefore, the area of the region for securing the alignment margin G2 increases, and the area of the unnecessary region that does not contribute to the capacitance increases. In the second embodiment, the shape of the first capacitive element 51 is close to a square, so the increase of the unnecessary area when the dimension Wt1 is reduced is small as compared with the comparative example. In this way, in the second embodiment, the effect of configuring the two first capacitive elements 51 to be offset in the second direction D2 is more significant.

[ third embodiment ]

Next, a power amplifying element according to a third embodiment will be described with reference to fig. 9. Hereinafter, the same configuration as that of the power amplifying element (fig. 1 to 5) of the first embodiment will be omitted from description.

Fig. 9 is a diagram showing a positional relationship in a plan view of one bipolar transistor among a plurality of bipolar transistors constituting the power amplification element of the third embodiment, a capacitor element and a resistor element connected to the bipolar transistor. In the first embodiment, one base electrode 40B is provided for one emitter mesa layer 34 of one bipolar transistor 30 (fig. 1). In contrast, in the third embodiment, two base electrodes 40B are arranged for one emitter mesa layer 34. That is, two base electrodes 40B are disposed inside one base mesa layer 36 in a plan view so as to be separated from each other.

The base electrode main portions 40BF of the two base electrodes 40B are arranged so as to sandwich the emitter mesa layer 34 in the first direction D1. The two collector electrodes 40C are arranged so as to sandwich the base mesa layer 36 in the first direction D1. Collector wiring 41C is connected to each of the two collector electrodes 40C. The area of the emitter mesa layer 34 in plan view is about twice the area of the emitter mesa layer 34 (fig. 1) of the power amplifying element of the first embodiment. More specifically, the dimension (width) of the first direction D1 of the emitter mesa layer 34 is about twice.

The base wirings 41B are connected to the two base electrodes 40B, respectively. The first capacitive element 51 and the resistive element 55 are also arranged one for each base electrode 40B.

Next, the excellent effects of the third embodiment will be explained.

If the two base electrode main portions 40BF corresponding to one bipolar transistor 30 in the third embodiment are connected to each other and one first capacitor element 51 and one resistor element 55 are disposed, collapse of the uniformity of the base current between the two base electrode main portions 40BF cannot be suppressed. In contrast, in the third embodiment, the first capacitor element 51 and the resistor element 55 are connected to the two base electrode main portions 40BF, respectively. Therefore, in one bipolar transistor 30, collapse of the uniformity of the base current between the two base electrode main portions 40BF can be suppressed. This makes it difficult to break the emitter current uniformly, and as a result, the SOA can be enlarged.

In the third embodiment as well, the area of the region occupied by the plurality of first capacitance elements 51 can be reduced as in the first embodiment.

[ fourth embodiment ]

Next, a power amplifying element according to a fourth embodiment will be described with reference to fig. 10. Hereinafter, the same configuration as that of the power amplifying element (fig. 9) of the third embodiment will not be described.

Fig. 10 is a diagram showing a positional relationship in a plan view of one bipolar transistor among a plurality of bipolar transistors constituting a power amplification element according to a fourth embodiment, a capacitor element and a resistor element connected to the bipolar transistor. In a third embodiment, a bipolar transistor 30 (fig. 9) includes an emitter mesa layer 34. In contrast, in the fourth embodiment, one bipolar transistor 30 includes two emitter mesa layers 34. That is, two emitter mesa layers 34 are disposed inside one base mesa layer 36 in a plan view.

The two emitter mesa layers 34 are disposed at an interval in the first direction D1. Emitter electrodes 40E are disposed corresponding to the two emitter mesa layers 34, respectively. One emitter wiring 41E is arranged to partially overlap with the two emitter electrodes 40E in a plan view. One emitter wiring 41E is connected to two emitter electrodes 40E.

Three base electrodes 40B are arranged corresponding to one bipolar transistor 30. The base electrode main portion 40BF of one base electrode 40B is disposed between the two emitter mesa layers 34. The base electrode main portions 40BF of the other two base electrodes 40B are disposed outside the two emitter mesa layers 34. Therefore, in any of the two emitter mesa layers 34, the base electrode main portion 40BF is disposed on both sides thereof, respectively.

The two emitter mesa layers 34 and the three base electrodes 40B are arranged inside the one base mesa layer 36 in a plan view. Collector electrodes 40C are disposed on both sides of the base mesa layer 36. Collector wirings 41C are connected to the two collector electrodes 40C, respectively.

The three base electrodes 40B are connected to base wirings 41B, respectively. Similarly, one first capacitive element 51 and one resistive element 55 are connected to each of the three base electrodes 40B. The two first capacitive elements 51 connected to the two base electrodes 40B at both ends are located at different positions in the first direction D1 and at the same position in the second direction D2. The first capacitive element 51 connected to the central base electrode 40B is arranged at a position shifted in the second direction D2 with respect to the two first capacitive elements 51 connected to the two base electrodes 40B at both ends, respectively. When viewed from the second direction of the plurality of bipolar transistors, the first capacitive element 51 connected to the central base electrode 40B is arranged to partially overlap the other two first capacitive elements 51. The area of the first capacitor element 51 connected to the central base electrode 40B in a plan view is about twice the area of each of the other two first capacitor elements 51 in a plan view. The resistance element 55 connected to the central base electrode 40B has a width in plan view approximately twice as large as the width of each of the other two resistance elements 55 in plan view.

Next, the excellent effects of the fourth embodiment will be explained.

In the fourth embodiment, as in the third embodiment, one first capacitor element 51 and one resistor element 55 are connected to the plurality of base electrodes 40B, respectively. Therefore, collapse of the uniformity of the base current among the plurality of base electrode main portions 40BF can be suppressed. In the fourth embodiment, as in the third embodiment, the two first capacitance elements 51 connected to the two base electrodes 40B adjacent to each other in the first direction are arranged at positions shifted in the second direction D2, and are arranged so as to partially overlap each other when viewed from the plurality of bipolar transistors in the second direction D2. Therefore, the area of the region occupied by the plurality of first capacitance elements 51 can be reduced.

In the fourth embodiment, an input signal is supplied from the base electrode 40B at the center to the emitter regions 33e (fig. 2) corresponding to two emitter mesa layers 34, and an input signal is supplied from the base electrodes 40B at both ends to the emitter regions 33e (fig. 2) corresponding to one emitter mesa layer 34. Therefore, approximately twice the bias current and the high-frequency current flow through the base electrode 40B at the center as compared with the base electrodes 40B at both ends.

Since the area of the first capacitor element 51 connected to the central base electrode 40B in plan view is about twice as large as the area of the other two first capacitor elements 51 in plan view, the capacitance of the first capacitor element 51 connected to the central base electrode 40B is also about twice as large as the capacitance of the other two first capacitor elements 51. Since the resistance element 55 connected to the central base electrode 40B has a width in plan view approximately twice that of the other two resistance elements 55, the resistance value of the resistance element 55 connected to the central base electrode 40B is approximately 1/2 of the resistance values of the other two resistance elements 55. Therefore, the impedance connected to the central base electrode 40B is about 1/2 times the impedance connected to the other two base electrodes 40B. Since the impedance connected to the central base electrode 40B is approximately 1/2, the voltage generated at the central base electrode 40B is equal to the voltage generated at the base electrodes 40B at both ends. In this way, even if the three base electrodes 40B are separated from each other, they operate as one base electrode connected to each other.

Next, a modified example of the fourth embodiment will be explained.

In the fourth embodiment, two emitter mesa layers 34 included in one bipolar transistor 30 are provided, but three or more emitter mesa layers may be provided. In this case, the number of base electrodes 40B may be one more than that of emitter mesa layers 34. Thereby, the base electrode main portion 40BF of the base electrode 40B can be arranged on both sides of each of the plurality of emitter mesa layers 34.

[ fifth embodiment ]

Next, a power amplifying element according to a fifth embodiment will be described with reference to fig. 11 and 12. Hereinafter, the same configuration as that of the power amplifying element (fig. 1 to 5) of the first embodiment will be omitted from description.

Fig. 11 is a diagram showing a positional relationship in a plan view of two bipolar transistors among a plurality of bipolar transistors constituting a power amplification element according to a fifth embodiment, and a capacitor element and a resistor element connected to the two bipolar transistors. In the first embodiment, one first capacitive element 51 and one resistive element 55 are connected to the plurality of base electrodes 40B, respectively. In contrast, in the fifth embodiment, the second capacitance elements 52 are further connected to the plurality of base electrodes 40B, respectively.

In each base wiring 41B, a widened portion 41Bb serving as a lower electrode of the second capacitor element 52 is provided in addition to the widened portion 41Ba serving as a lower electrode of the first capacitor element 51. The ground line 64 is arranged to overlap the plurality of widened portions 41Bb in a plan view. The ground line 64 extends in the first direction D1. Ground line 64 is connected to ground line 62 (fig. 4) to which the emitter of bipolar transistor 30 is connected. The bipolar transistor 30, the ground line 64, the high-frequency signal input wiring 61, and the base bias input wiring 42 are arranged in this order in the second direction D2.

The second capacitive element 52 is formed at a position where the widened portion 41Bb of the base wiring 41B and the ground line 64 overlap each other. The two second capacitance elements 52 connected to the two base electrodes 40B adjacent to each other in the first direction D1 are disposed at different positions when viewed in the first direction D1, and are disposed so as to partially overlap with respect to the first direction D1.

Fig. 12 is an equivalent circuit diagram of a part of the power amplifying element of the fifth embodiment. In the fifth embodiment, a second capacitance element 52 connected between the base and emitter of the bipolar transistor 30 is added to the power amplification element of the first embodiment (fig. 5). The second capacitive element 52 has a function of improving the efficiency of the bipolar transistor 30.

Next, the excellent effects of the fifth embodiment will be explained.

In the fifth embodiment, the plurality of second capacitance elements 52 are arranged so as to be offset in the second direction D2, similarly to the plurality of first capacitance elements 51, so that the area of the region occupied by the plurality of second capacitance elements 52 can be reduced.

It is needless to say that each embodiment is an example, and partial replacement or combination of the structures shown in different embodiments can be performed. The same operational effects brought about by the same constitutions of the plurality of embodiments are not mentioned in turn for each embodiment. The present invention is not limited to the above-described embodiments. For example, it will be apparent to those skilled in the art that various alterations, modifications, combinations, and the like can be made.