阅读说明：本技术 一种用于优化堆叠开关管耐压均匀性的射频开关电路 (Radio frequency switch circuit for optimizing voltage withstanding uniformity of stacked switch tubes ) 是由 沈宇 管剑铃 谢婷婷 王玉娇 周德杭 倪成东 倪文海 徐文华 于 2021-08-24 设计创作，主要内容包括：本发明公开了一种用于优化堆叠开关管耐压均匀性的射频开关电路,涉及射频集成电路技术领域。本发明包括：串联支路模块：包括2N个第一开关晶体管、第一偏置晶体管、第一源漏电阻、第一栅极偏置电阻,2N-1个第一栅极串联电阻和1个第一栅极公共端电阻；并联支路模块：由2M个第二开关晶体管、第二偏置晶体管、第二源漏电阻、第二栅极偏置电阻,2M-1个第二栅极串联电阻和1个第二栅极公共端电阻；本发明结构可以降低射频开关前几级和后几级开关晶体管承担的最大峰值电压,提高射频开关各级开关晶体管的耐压均匀性以及射频开关的最大输入功率,尤其提高了并联支路模块各级开关晶体管的耐压均匀性。(The invention discloses a radio frequency switch circuit for optimizing the voltage withstanding uniformity of stacked switch tubes, and relates to the technical field of radio frequency integrated circuits. The invention comprises the following steps: a series branch module: the circuit comprises 2N first switch transistors, first bias transistors, first source-drain resistors, first grid bias resistors, 2N-1 first grid series resistors and 1 first grid common end resistor; a parallel branch module: the transistor comprises 2M second switch transistors, second bias transistors, second source-drain resistors, second grid bias resistors, 2M-1 second grid series resistors and 1 second grid common end resistor; the structure of the invention can reduce the maximum peak voltage born by the front stage and the rear stage of the switch transistors of the radio frequency switch, improve the voltage withstanding uniformity of each stage of the switch transistors of the radio frequency switch and the maximum input power of the radio frequency switch, and especially improve the voltage withstanding uniformity of each stage of the switch transistors of the parallel branch circuit module.)

1. A radio frequency switch circuit for optimizing stack switch tube voltage withstand uniformity, comprising:

a series branch module: the circuit comprises 2N first switch transistors (M11), 2N first bias transistors (M21), 2N first source-drain resistors (Rds1), 2N first gate bias resistors (R1), 2N-1 first gate series resistors (R2) and 1 first gate common terminal resistor (R3); n is a positive integer; a drain of the 1 st stage first switching transistor (M11) is connected to the first radio frequency input output port (RF1), a source of the 1 st stage first switching transistor (M11) is connected to a drain of the 2 nd stage first switching transistor (M11), a source of the 1 st stage first switching transistor (M11), the drain electrode of the first-stage first switch transistor (M11) is connected with the drain electrode of the first-stage first bias transistor (M21), the drain electrode of the first-stage first bias transistor (M21) is connected with the grid electrode, the source electrode of the first-stage first bias transistor (M21) is connected with the grid electrode of the first-stage first switch transistor (M11), the grid electrode of the first-stage first switch transistor (M11) is connected with one end of the first-stage first grid bias resistor (R1), and the other end of the first-stage first grid bias resistor (R1) is connected with one end of the first-stage first grid series resistor (R2); by analogy, the connection modes of the first switch transistor (M11), the first bias transistor (M21), the first source-drain resistor (Rds1), the first gate bias resistor (R1) and the first gate series resistor (R2) from the 2 nd stage to the 2N-1 nd stage are the same as those described above; the drain of the 2N-th stage first switch transistor (M11) is connected with the source of the 2N-1-th stage first switch transistor (M11), the source of the 2N-th stage first switch transistor (M11) is connected with the second radio frequency input/output port (RF2), the source and the drain of the 2N-th stage first switch transistor (M11) are respectively connected with two ends of a first source-drain resistor (Rds1), the body of the 2N-th stage first switch transistor (M11) is connected with the drain of the 2N-th stage first bias transistor (M21), the drain of the 2N-th stage first bias transistor (M21) is connected with the gate, the source of the 2N-th stage first bias transistor (M21) is connected with the gate of the 2N-th stage first switch transistor (M11), the gate of the 2N-th stage first switch transistor (M11) is connected with one end of the 2N-th stage first gate bias resistor (R1), and the other end of the 2N-stage first switch transistor (M1) is connected with the gate of the 2N-1-stage first bias resistor (R21) in series One end of the resistor (R2) is connected;

a parallel branch module:

the circuit is composed of 2M second switch transistors (M12), 2M second bias transistors (M22), 2M second source-drain resistors (Rds2), 2M second gate bias resistors (R4), 2M-1 second gate series resistors (R5) and 1 second gate common terminal resistor (R6); m is a positive integer;

the drain of the 1 st stage second switching transistor (M12) is connected to the first radio frequency input/output port (RF1), the source of the 1 st stage second switching transistor (M12) is connected to the drain of the 2 nd stage second switching transistor (M12), the source of the 1 st stage second switching transistor (M12), the drain electrode of the first-stage second switch transistor (M12) is connected with the drain electrode of the first-stage second bias transistor (M22), the drain electrode of the first-stage second bias transistor (M22) is connected with the grid electrode, the source electrode of the first-stage second bias transistor (M22) is connected with the grid electrode of the first-stage second switch transistor (M12), the grid electrode of the first-stage second switch transistor (M12) is connected with one end of the first-stage second grid bias resistor (R4), and the other end of the first-stage second grid bias resistor (R4) is connected with one end of the first-stage second grid series resistor (R5); by analogy, the connection modes of the second switch transistor (M12), the second bias transistor (M22), the second source-drain resistor (Rds2), the second gate bias resistor (R4) and the second gate series resistor (R5) from the 2 nd stage to the 2M-1 st stage are the same as above; a drain of the 2M-th stage second switching transistor (M12) is connected to a source of the 2M-1-th stage second switching transistor (M12), a source of the 2M-th stage second switching transistor (M12) is connected to ground, a source of the 2M-th stage second switching transistor (M12), the drain electrode of the second source-drain resistor (Rds2) is connected with two ends of the second source-drain resistor (Rds2), the body region of the second 2M-stage switch transistor (M12) is connected with the drain electrode of the second 2M-stage bias transistor (M22), the drain electrode of the second 2M-stage bias transistor (M22) is connected with the grid electrode, the source electrode of the second 2M-stage bias transistor (M22) is connected with the grid electrode of the second 2M-stage switch transistor (M12), the grid electrode of the second 2M-stage switch transistor (M12) is connected with one end of the second 2M-stage gate bias resistor (R4), and the other end of the second 2M-stage gate bias resistor (R4) is connected with one end of the second 2M-1-stage gate series resistor (R5).

2. The RF switch circuit of claim 1, wherein one end of the N-th stage first gate bias resistor (R1) is connected to one end of a first gate common terminal resistor (R3), and the other end of the first gate common terminal resistor (R3) is connected to a first gate control voltage (VG 1).

Technical Field

The invention belongs to the technical field of radio frequency integrated circuits, and particularly relates to a radio frequency switch circuit for optimizing the voltage withstanding uniformity of stacked switch tubes.

Background

With the continuous development of wireless mobile communication technology, the rf switch plays an increasingly important role in the multiband front-end module and the antenna tuner. Especially in multi-scenario applications of antenna tuners, high power handling capability has become an important research direction for radio frequency switches.

Stacked transistors are a common method of increasing the power handling capability of rf switches. Taking the simplest single-pole single-throw SPST type RF switch as an example, the drawback is that VG 1-VG 2-2.5V in the off state of the RF switch, when a high-power RF signal enters from RF1 or RF2, the maximum peak voltage borne by the switching transistor of each stage of the stack of the series-arm module and the parallel-arm module is not uniform, and especially, the maximum peak voltage borne by the switching transistor of the first and the last stages of the stack of transistors is much larger than the average value, so that the maximum input power that the RF switch can handle is reduced, and even the transistor devices inside the RF switch are damaged.

Therefore, the invention optimizes the withstand voltage uniformity of the stacked transistor by changing the grid bias resistance network, can reduce the maximum peak voltage born by the front and rear stages of switch transistors of the stacked transistor, and particularly improves the withstand voltage uniformity of each stage of switch transistors of the parallel branch module, thereby improving the maximum input power of the radio frequency switch.

Disclosure of Invention

The invention provides a radio frequency switch circuit for optimizing the voltage withstanding uniformity of stacked switch tubes, which solves the problems.

In order to solve the technical problems, the invention is realized by the following technical scheme:

the invention relates to a radio frequency switch circuit for optimizing the voltage resistance uniformity of stacked switch tubes, which comprises:

a series branch module: the circuit comprises 2N first switch transistors, 2N first bias transistors, 2N first source-drain resistors, 2N first grid bias resistors, 2N-1 first grid series resistors and 1 first grid common end resistor; n is a positive integer; the drain electrode of the 1 st-stage first switch transistor is connected with the first radio frequency input/output port, the source electrode of the 1 st-stage first switch transistor is connected with the drain electrode of the 2 nd-stage first switch transistor, the source electrode and the drain electrode of the 1 st-stage first switch transistor are respectively connected with two ends of a first source-drain resistor, the body area of the 1 st-stage first switch transistor is connected with the drain electrode of the 1 st-stage first bias transistor, the drain electrode of the 1 st-stage first bias transistor is connected with the grid electrode, the source electrode of the 1 st-stage first bias transistor is connected with the grid electrode of the 1 st-stage first switch transistor, the grid electrode of the 1 st-stage first switch transistor is connected with one end of the 1 st-stage first grid bias resistor, and the other end of the 1 st-stage first grid bias resistor is connected with one end of the 1 st-stage first grid electrode series resistor; by analogy, the connection modes of the first switch transistor, the first bias transistor, the first source-drain resistor, the first grid bias resistor and the first grid series resistor from the 2 nd level to the 2N-1 th level are the same as those described above; the drain electrode of the 2N-th-stage first switch transistor is connected with the source electrode of the 2N-1-th-stage first switch transistor, the source electrode of the 2N-th-stage first switch transistor is connected with the second radio frequency input/output port, the source electrode and the drain electrode of the 2N-th-stage first switch transistor are respectively connected with two ends of a first source-drain resistor, the body region of the 2N-th-stage first switch transistor is connected with the drain electrode of the 2N-th-stage first bias transistor, the drain electrode of the 2N-th-stage first bias transistor is connected with the grid electrode, the source electrode of the 2N-th-stage first bias transistor is connected with the grid electrode of the 2N-th-stage first switch transistor, the grid electrode of the 2N-th-stage first switch transistor is connected with one end of the 2N-stage first grid bias resistor, and the other end of the 2N-stage first grid bias resistor is connected with one end of the 2N-1-stage first grid resistor in series;

a parallel branch module:

the transistor comprises 2M second switch transistors, 2M second bias transistors, 2M second source-drain resistors, 2M second grid bias resistors, 2M-1 second grid series resistors and 1 second grid public end resistor; m is a positive integer;

the drain electrode of the 1 st-stage second switch transistor is connected with the first radio frequency input/output port, the source electrode of the 1 st-stage second switch transistor is connected with the drain electrode of the 2 nd-stage second switch transistor, the source electrode and the drain electrode of the 1 st-stage second switch transistor are respectively connected with two ends of a second source-drain resistor, the body area of the 1 st-stage second switch transistor is connected with the drain electrode of the 1 st-stage second bias transistor, the drain electrode of the 1 st-stage second bias transistor is connected with the grid electrode, the source electrode of the 1 st-stage second bias transistor is connected with the grid electrode of the 1 st-stage second switch transistor, the grid electrode of the 1 st-stage second switch transistor is connected with one end of the 1 st-stage second grid bias resistor, and the other end of the 1 st-stage second grid bias resistor is connected with one end of the 1 st-stage second grid electrode series resistor; by analogy, the connection modes of the second switch transistor, the second bias transistor, the second source-drain resistor, the second grid bias resistor and the second grid series resistor from the 2 nd level to the 2M-1 th level are the same as the connection modes of the second switch transistor, the second bias transistor, the second source-drain resistor, the second grid bias resistor and the second grid series resistor; the drain electrode of the 2M-level second switch transistor is connected with the source electrode of the 2M-1-level second switch transistor, the source electrode of the 2M-level second switch transistor is connected with the ground, the source electrode and the drain electrode of the 2M-level second switch transistor are respectively connected with two ends of a second source-drain resistor, the body region of the 2M-level second switch transistor is connected with the drain electrode of the 2M-level second bias transistor, the drain electrode of the 2M-level second bias transistor is connected with the grid electrode, the source electrode of the 2M-level second bias transistor is connected with the grid electrode of the 2M-level second switch transistor, the grid electrode of the 2M-level second switch transistor is connected with one end of the 2M-level second grid electrode bias resistor, and the other end of the 2M-level second grid electrode bias resistor is connected with one end of the 2M-1-level second grid electrode series resistor.

Furthermore, one end of the nth stage first gate bias resistor is connected to one end of the first gate common end resistor, and the other end of the first gate common end resistor is connected to the first gate control voltage.

Compared with the prior art, the invention has the following beneficial effects:

the invention improves the voltage-withstanding uniformity of each stacked tube of the radio frequency switch by changing the grid resistance network structures of the serial branch and the parallel branch, and simultaneously, the grid bias voltage VG1 of the serial branch is connected with the middle Nth stage to meet the application mode of multiple scenes, namely when a radio frequency signal enters from an RF1 or an RF2 end, each stacked tube of the radio frequency switch can keep relatively uniform voltage withstanding, the maximum peak voltage born by the front and rear stages of switch transistors of the radio frequency switch can be reduced, the voltage-withstanding uniformity of each stage of switch transistors of the radio frequency switch and the maximum input power of the radio frequency switch are improved, and particularly the voltage-withstanding uniformity of each stage of switch transistors of the parallel branch module is improved.

Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a block diagram of an RF switching circuit for optimizing stack switch voltage uniformity in accordance with the present invention;

FIG. 2 is a block diagram of a conventional SPST RF switch;

fig. 3 is a comparison graph of the withstand voltage distribution curves of the rf switch according to the present invention and the conventional rf switch series branch module;

fig. 4 is a comparison graph of voltage-withstanding distribution curves of the rf switch according to the present invention and the conventional rf switch parallel branch module;

in fig. 1, the list of components represented by the various reference numbers is as follows:

r1-first gate bias resistor, R2-first gate series resistor, R3-first gate common terminal resistor, RF 1-first radio frequency input/output port, RF 2-second radio frequency input/output port, Rds 1-first source-drain resistor, M11-first switch transistor, M21-first bias transistor, VG 1-first gate control voltage, R3-first gate common terminal resistor, R4-second gate bias resistor, R5-second gate series resistor, R6-second gate common terminal resistor, M12-second switch transistor, Rds 2-second source-drain resistor, M12-second switch transistor, M22-second bias transistor, VG 2-second gate control voltage.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 2, a conventional single-pole single-throw SPST type RF switch has a disadvantage that when the RF switch is in an off state, VG 1-VG 2-2.5V, when a high-power RF signal enters from RF1 or RF2, the maximum peak voltage borne by the switching transistor of each stage of the stack of the series-arm module and the parallel-arm module is not uniform, and especially, the maximum peak voltage borne by the switching transistor of the first and the last stages of the stack of transistors is much larger than the average value, so that the maximum input power that the RF switch can handle is reduced, and even the transistor device inside the RF switch is damaged; therefore, the invention optimizes the withstand voltage uniformity of the stacked transistor by changing the grid bias resistance network, can reduce the maximum peak voltage born by the front and rear stages of switch transistors of the stacked transistor, and particularly improves the withstand voltage uniformity of each stage of switch transistors of the parallel branch module, thereby improving the maximum input power of the radio frequency switch;

referring to fig. 1, a radio frequency switch circuit for optimizing the uniformity of the voltage resistance of stacked switch transistors according to the present embodiment is implemented by using a 110nm SOI CMOS process, and includes:

a series branch module: the circuit comprises 2N first switch transistors M11, 2N first bias transistors M21, 2N first source-drain resistors Rds1, 2N first gate bias resistors R1, 2N-1 first gate series resistors R2 and 1 first gate common terminal resistor R3; n is a positive integer; the drain of the 1 st-stage first switch transistor M11 is connected to the first RF input/output port RF1, the source of the 1 st-stage first switch transistor M11 is connected to the drain of the 2 nd-stage first switch transistor M11, the source and the drain of the 1 st-stage first switch transistor M11 are connected to two ends of the first source-drain resistor Rds1, the body of the 1 st-stage first switch transistor M11 is connected to the drain of the 1 st-stage first bias transistor M21, the drain of the 1 st-stage first bias transistor M21 is connected to the gate, the source of the 1 st-stage first bias transistor M21 is connected to the gate of the 1 st-stage first switch transistor M11, the gate of the 1 st-stage first switch transistor M11 is connected to one end of the 1 st-stage first gate bias resistor R1, and the other end of the 1 st-stage first gate bias resistor R1 is connected to one end of the 1 st-stage first gate series resistor R2; in analogy, the connection modes of the first switching transistor M11, the first bias transistor M21, the first source-drain resistor Rds1, the first gate bias resistor R1 and the first gate series resistor R2 from the 2 nd stage to the 2N-1 nd stage are the same as those described above; the drain of the 2N-th stage first switching transistor M11 is connected to the source of the 2N-1 st stage first switching transistor M11, the source of the 2N-th stage first switching transistor M11 is connected to the second radio frequency input output port RF2, the source of the 2N-th stage first switching transistor M11, the drain electrode of the first source-drain resistor Rds1 is connected to the two ends of the first source-drain resistor Rds1, the body region of the 2N-th stage first switch transistor M11 is connected to the drain electrode of the 2N-th stage first bias transistor M21, the drain electrode of the 2N-th stage first bias transistor M21 is connected to the gate electrode, the source electrode of the 2N-th stage first bias transistor M21 is connected to the gate electrode of the 2N-th stage first switch transistor M11, the gate electrode of the 2N-th stage first switch transistor M11 is connected to one end of the 2N-th stage first gate bias resistor R1, and the other end of the 2N-th stage first gate bias resistor R1 is connected to one end of the 2N-1-th stage first gate series resistor R2;

a parallel branch module:

the circuit is composed of 2M second switch transistors M12, 2M second bias transistors M22, 2M second source-drain resistors Rds2, 2M second gate bias resistors R4, 2M-1 second gate series resistors R5 and 1 second gate common terminal resistor R6; m is a positive integer;

the drain of the 1 st-stage second switch transistor M12 is connected to the first RF input/output port RF1, the source of the 1 st-stage second switch transistor M12 is connected to the drain of the 2 nd-stage second switch transistor M12, the source and the drain of the 1 st-stage second switch transistor M12 are connected to two ends of the second source-drain resistor Rds2, the body of the 1 st-stage second switch transistor M12 is connected to the drain of the 1 st-stage second bias transistor M22, the drain of the 1 st-stage second bias transistor M22 is connected to the gate, the source of the 1 st-stage second bias transistor M22 is connected to the gate of the 1 st-stage second switch transistor M12, the gate of the 1 st-stage second switch transistor M12 is connected to one end of the 1 st-stage second gate bias resistor R4, and the other end of the 1 st-stage second gate bias resistor R4 is connected to one end of the 1 st-stage second gate series resistor R5; in analogy, the connection modes of the second switch transistor M12, the second bias transistor M22, the second source-drain resistor Rds2, the second gate bias resistor R4 and the second gate series resistor R5 from the 2 nd stage to the 2M-1 st stage are the same as above; a drain of the 2M-th stage second switching transistor M12 is connected to a source of the 2M-1 st stage second switching transistor M12, a source of the 2M-th stage second switching transistor M12 is connected to ground, a source of the 2M-th stage second switching transistor M12, the drain of the second source-drain resistor Rds2 is connected to the two ends of the second source-drain resistor Rds2, the body of the second 2M-stage switch transistor M12 is connected to the drain of the second 2M-stage bias transistor M22, the drain of the second 2M-stage bias transistor M22 is connected to the gate, the source of the second 2M-stage bias transistor M22 is connected to the gate of the second 2M-stage switch transistor M12, the gate of the second 2M-stage switch transistor M12 is connected to one end of the second 2M-stage gate bias resistor R4, and the other end of the second 2M-stage gate bias resistor R4 is connected to one end of the second 2M-1-stage gate series resistor R5.

One end of the nth stage first gate bias resistor R1 is connected to one end of the first gate common terminal resistor R3, and the other end of the first gate common terminal resistor R3 is connected to the first gate control voltage VG 1.

One end of the second gate bias resistor R4 of the 2M-th stage is connected with one end of the second gate common terminal resistor R6, and the other end of the second gate common terminal resistor R6 is connected with a second gate control voltage VG 2;

the single-pole single-throw SPST type radio frequency switch circuit is simulated based on a 110nm SOI CMOS process. The simulation conditions were as follows: the value of N is 13, the value of M is 14, and the value ranges of the first source-drain resistance Rds1, the first gate bias resistance R1, the second gate bias resistance R4, the first gate series resistance R2, the second gate series resistance R5, the first gate common end resistance R3 and the second gate common end resistance R6 are between 1K and 100K; the first gate control voltage VG1 and the second gate control voltage VG2 are-2.5V, the RF power signal enters from the first RF input/output port RF1, and the maximum input power is set to 48.5 dBm. Based on the simulation parameters, the radio frequency switch circuit provided by the invention carries out PSS simulation.

Fig. 3 is a comparison graph of the withstand voltage distribution curves of the rf switch according to the present invention and the conventional rf switch series branch module; the abscissa of the figure represents the number of the first switching transistor M11 stages stacked in the series-arm module, the total number of stages is 26, and the ordinate represents the maximum peak voltage Vds borne between the source and the drain of the single-stage first switching transistor M11.

Fig. 4 is a comparison graph of voltage-withstanding distribution curves of the rf switch according to the present invention and the conventional rf switch parallel branch module; the abscissa of the figure is the series of the second switching transistor M12 stacked in parallel branch modules, the total series is 28, and the ordinate is the maximum peak voltage Vds borne between the source and the drain of the single-stage second switching transistor M12.

According to the simulation result, the voltage-resistant distribution curve of the radio frequency switch circuit structure provided by the invention is smoother than that of the traditional radio frequency switch circuit structure, namely the radio frequency switch circuit structure improves the voltage-resistant uniformity of each stage of stacked tubes of the radio frequency switch.

Has the advantages that:

according to the invention, the second harmonic value of the radio frequency switch is reduced by changing the grid resistance network structures of the serial branch and the parallel branch, the voltage withstanding uniformity and the harmonic performance of each stage of stacked tubes of the radio frequency switch and the maximum input power of the radio frequency switch are improved, and meanwhile, the grid bias voltage VG1 of the serial branch is connected with the middle Nth stage, so that the application mode of multiple scenes is met, namely when a radio frequency signal enters from the RF1 or RF2 end, each stage of stacked tubes of the radio frequency switch can keep relatively uniform voltage withstanding.

The preferred embodiments of the invention disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.