阅读说明：本技术 一种可配置分数分频器 (Configurable fractional frequency divider ) 是由 王科迪 陈雷 李学武 张彦龙 孙华波 单程奕 杨铭谦 祁逸 周雷 刘银萍 李智 于 2021-06-30 设计创作，主要内容包括：本发明涉及一种可配置分数分频器,包括上升沿参考时钟选择电路、下降沿参考时钟选择电路、低电平控制电路、高电平控制电路、状态选择电路和输出电路,上升沿参考时钟选择电路和下降沿参考时钟选择电路采用相同的电路结构,低电平控制电路和高电平控制电路采用相同的电路结构；可配置分数分频器接收L个输入时钟CLKMP,通过配置信号控制输出时钟边沿翻转时刻和高低电平持续时间,产生所需频率的输出时钟CLKOUT；CLKMP需满足频率相同相位相差360°/L的要求。本发明的可配置分数分频器,采用加法器、减法计数器和简单的控制逻辑实现,电路复杂度低,减小了电路所需面积和功耗。(The invention relates to a configurable fractional frequency divider, which comprises a rising edge reference clock selection circuit, a falling edge reference clock selection circuit, a low level control circuit, a high level control circuit, a state selection circuit and an output circuit, wherein the rising edge reference clock selection circuit and the falling edge reference clock selection circuit adopt the same circuit structure, and the low level control circuit and the high level control circuit adopt the same circuit structure; the configurable fractional frequency divider receives L input clocks CLKMP, controls the edge turning moment and the high-low level duration of an output clock through a configuration signal, and generates an output clock CLKOUT with required frequency; CLKMP is required to satisfy the requirement of the same frequency and 360 DEG/L phase difference. The configurable fractional frequency divider is realized by adopting the adder, the subtraction counter and simple control logic, has low circuit complexity and reduces the area and the power consumption required by the circuit.)

1. A configurable fractional frequency divider, comprising a rising edge reference clock selection circuit (101), a falling edge reference clock selection circuit (102), a low level control circuit (103), a high level control circuit (104), a state selection circuit (105) and an output circuit (106),

the rising edge reference clock selection circuit (101) and the falling edge reference clock selection circuit (102) adopt the same circuit structure, and the low level control circuit (103) and the high level control circuit (104) adopt the same circuit structure;

the configurable fractional frequency divider receives L input clocks CLKMP, controls the edge turning moment and the high-low level duration of an output clock through a configuration signal, and generates an output clock CLKOUT with required frequency; CLKMP is required to satisfy the requirement of the same frequency and 360 DEG/L phase difference.

2. A configurable fractional divider as claimed in claim 1, characterized in that the rising edge reference clock selection circuit (101) selects one of the L clock input signals CLKMP to be output to the internal clock signal RISE CLK by configuring the control of the input signals PROG _ SEL _ R [ M:0], PROG _ FRAC [ M:0] and the internal control signal RISE WAIT, the RISE CLK being transmitted to the low level control circuit (103) and the state selection circuit (105) to be used as a reference clock for the inversion time of the rising edge of CLKOUT.

3. A configurable fractional frequency divider as claimed in claim 1, wherein the falling edge reference clock selection circuit (102) selects one of the L clock input signals CLKMP to output to the internal clock signal FALL _ CLK by configuring the control of the input signals PROG _ SEL _ F [ M:0], PROG _ FRAC [ M:0] and the internal control signal FALL _ WAIT, which is transmitted to the high level control circuit (104) and the state selection circuit (105) to serve as a reference clock for the falling edge flip time of CLKOUT.

4. The configurable fractional frequency divider according to claim 1, wherein the LOW level control circuit (103) receives a configuration input signal PROG _ LOW [ N:0], the internal control signal RISE _ WAIT and the internal clock signal RISE _ CLK, and when RISE _ WAIT is high, the LOW level control circuit (103) prepares a LOW level initial count value PROG _ LOW [ N:0 ]; when RISE _ WAIT is low, the low level control circuit (103) performs a low level count value minus 1 at each rising edge of RISE _ CLK until minus 0; when the low-level count value is 0, the low-level control circuit (103) counts the high-level pulses of the indication signal DIVR which are outputted in synchronization by half the RISE _ CLK clock period width.

5. A configurable fractional frequency divider according to claim 1, characterized in that the HIGH level control circuit (104) receives a configuration input signal PROG _ HIGH [ N:0], an internal control signal FALL _ WAIT and an internal clock signal FALL _ CLK, the HIGH level control circuit (104) preparing a HIGH level initial count value PROG _ HIGH [ N:0] when the FALL _ WAIT is HIGH; when FALL _ WAIT is at a low level, the high level control circuit (104) performs a high level count value minus 1 at each rising edge of FALL _ CLK until minus 0; when the high-level count value is 0, the high-level control circuit (104) counts the high-level pulse of half the clock period width of the FALL _ CLK outputted synchronously by the indication signal DIVF.

6. A configurable fractional divider according to claim 1, characterized in that the state selection circuit (105) receives the configuration input signal PROG _ CTRL _ R, PROG _ CTRL _ F, the internal control signals DIVR, DIVF and the internal clock signals RISE _ CLK, FALL _ CLK; level switching is carried out on RISE _ WAIT and FALL _ WAIT through control of PROG _ CTRL _ R, PROG _ CTRL _ F, RISE _ CLK and FALL _ CLK at edges of DIVR and DIVF, and control over the working state of the configurable fractional frequency divider is achieved.

7. A configurable fractional frequency divider according to claim 1, wherein the output circuit (106) receives internal control signals DIVR, DIVF, CLKOUT going from low to high when the DIVR is high and the DIVF is low; when DIVR is low and DIVF is high, CLKOUT is changed from high to low; when DIVR and DIVF are both low, CLKOUT output remains unchanged; thereby achieving the correct fractional division function.

8. The configurable fractional frequency divider of claim 1, wherein, in the values of the configuration signal, meaning that the rounding is done down,indicating rounding up and M, N indicating the number of bits of the signal.

Technical Field

The invention relates to a configurable fractional frequency divider, in particular to a configurable fractional frequency divider for multiphase clock input, belonging to the technical field of integrated circuits.

Background

In circuit design, a frequency divider is usually used to generate another low-frequency output clock from a high-frequency input clock to meet the frequency requirements of different units in the circuit for the clock. Frequency dividers are generally divided into integer dividers and fractional dividers. The integer frequency divider can be realized by a counter generally, and the realization method is simple.

The fractional frequency divider generally controls integer frequency division by sigma-delta modulation, so that the average value of the integer frequency division reaches the target of fractional frequency division, thereby realizing the function of fractional frequency division. However, the fractional frequency divider designed by sigma-delta modulation has a complex circuit structure, requires a large circuit area and power consumption, has a unique frequency division value, and needs to consider the suppression of quantization noise.

Disclosure of Invention

The technical problem solved by the invention is as follows: the configurable fractional frequency divider overcomes the defects of the prior art, reduces the complexity of the fractional frequency divider, reduces the area and power consumption of the fractional frequency divider, improves the flexibility of a fractional frequency division value, and can be widely applied to the design of programmable logic and reconfigurable circuits.

The technical scheme of the invention is as follows:

a configurable fractional frequency divider comprises a rising edge reference clock selection circuit, a falling edge reference clock selection circuit, a low level control circuit, a high level control circuit, a state selection circuit and an output circuit,

the rising edge reference clock selection circuit and the falling edge reference clock selection circuit adopt the same circuit structure, and the low level control circuit and the high level control circuit adopt the same circuit structure;

the configurable fractional frequency divider receives L input clocks CLKMP, controls the edge turning moment and the high-low level duration of an output clock through a configuration signal, and generates an output clock CLKOUT with required frequency; CLKMP is required to satisfy the requirement of the same frequency and 360 DEG/L phase difference.

Further, the rising edge reference clock selection circuit selects one of the L clock input signals CLKMP to output to the internal clock signal RISE _ CLK by configuring the control of the input signals PROG _ SEL _ R [ M:0], PROG _ FRAC [ M:0] and the internal control signal RISE _ WAIT, and RISE _ CLK is transmitted to the low level control circuit and the state selection circuit to be used as a reference clock for the rising edge inversion time of CLKOUT.

Further, the falling edge reference clock selection circuit selects one of the L clock input signals CLKMP to output to the internal clock signal FALL _ CLK by configuring the control of the input signals PROG _ SEL _ F [ M:0], PROG _ FRAC [ M:0] and the internal control signal FALL _ WAIT, and the FALL _ CLK is transmitted to the high level control circuit and the state selection circuit to be used as a reference clock at the time of the falling edge inversion of CLKOUT.

Further, the LOW level control circuit receives a configuration input signal PROG _ LOW [ N:0], an internal control signal RISE _ WAIT and an internal clock signal RISE _ CLK, and when RISE _ WAIT is at a high level, the LOW level control circuit prepares a LOW level initial count value PROG _ LOW [ N:0 ]; when RISE _ WAIT is low, the low level control circuit executes the subtraction of 1 from the low level count value until 0 is subtracted at each rising edge of RISE _ CLK; when the low-level count value is 0, the low-level control circuit counts the high-level pulses of the indication signal DIVR which are synchronously output for half the RISE _ CLK clock period width.

Further, the HIGH level control circuit receives a configuration input signal PROG _ HIGH [ N:0], an internal control signal FALL _ WAIT, and an internal clock signal FALL _ CLK, and when FALL _ WAIT is at a HIGH level, the HIGH level control circuit prepares a HIGH level initial count value PROG _ HIGH [ N:0 ]; when FALL _ WAIT is at a low level, the high level control circuit performs the subtraction of the high level count value by 1 at each rising edge of FALL _ CLK until the subtraction is 0; when the high-level count value is 0, the high-level control circuit counts the indication signal DIVF to synchronously output a high-level pulse of half the clock period width of the well _ CLK.

Further, the state selection circuit receives configuration input signals PROG _ CTRL _ R, PROG _ CTRL _ F, internal control signals DIVR, DIVF, and internal clock signals RISE _ CLK, FALL _ CLK; level switching is carried out on RISE _ WAIT and FALL _ WAIT through control of PROG _ CTRL _ R, PROG _ CTRL _ F, RISE _ CLK and FALL _ CLK at edges of DIVR and DIVF, and control over the working state of the configurable fractional frequency divider is achieved.

Further, the output circuit receives internal control signals DIVR and DIVF, and when the DIVR is at a high level and the DIVF is at a low level, the CLKOUT is switched from the low level to the high level; when DIVR is low and DIVF is high, CLKOUT is changed from high to low; when DIVR and DIVF are both low, CLKOUT output remains unchanged; thereby achieving the correct fractional division function.

Furthermore, in the value of the configuration signal,meaning that the rounding is done down,indicating rounding up and M, N indicating the number of bits of the signal.

Compared with the prior art, the invention has the beneficial effects that:

(1) the configurable fractional frequency divider is realized by adopting the adder, the subtraction counter and simple control logic, has low circuit complexity and reduces the area and power consumption required by the circuit;

(2) the configurable fractional frequency divider adopts the configurable control signal to configure the fractional frequency division value, improves the universality and the flexibility of the fractional frequency divider, and can be more widely applied to the design of programmable logic and reconfigurable circuits.

Drawings

Fig. 1 is a schematic diagram of an overall structure of a configurable fractional frequency divider according to the present invention;

FIG. 2 is a schematic diagram of a rising edge reference clock selection circuit and a falling edge reference clock selection circuit in the configurable fractional frequency divider according to the present invention;

FIG. 3 is a schematic diagram of a low level control circuit and a high level control circuit in the configurable fractional frequency divider according to the present invention;

FIG. 4 is a schematic diagram of a state selection circuit in the configurable fractional frequency divider according to the present invention;

FIG. 5 is a schematic diagram of an output circuit of the configurable fractional frequency divider according to the present invention;

fig. 6 is a waveform diagram of the eight-phase clock 5.375 frequency division according to an embodiment of the present invention.

Detailed Description

The invention is further illustrated by the following examples.

Fig. 1 is a schematic diagram of an overall structure of a configurable fractional frequency divider according to the present invention. The fractional divider includes a rising edge reference clock selection circuit 101, a falling edge reference clock selection circuit 102, a low level control circuit 103, a high level control circuit 104, a state selection circuit 105, and an output circuit 106. The rising edge reference clock selection circuit 101 and the falling edge reference clock selection circuit 102 have the same circuit configuration, and the low level control circuit 103 and the high level control circuit 104 have the same circuit configuration.

A fractional divide value is defined as I.F, where I is the integer portion of the divide value and F is the fractional portion of the divide value. The configurable fractional divider receives L: (L ≧ 4) phase clock CLKMP, by configuration signal PROG _ CTRL _ R, PROG _ CTRL _ F, PROG _ SEL _ R [ M:0]、PROG_SEL_F[M:0]、PROG_FRAC[M:0]、PROG_LOW[N:0]、PROG_HIGH[N:0]The output clock edge inversion time and the high-low level duration are controlled to realize the frequency division function, and a frequency division output signal CLKOUT is generated. The values of the configuration signal are shown in table 1, wherein,meaning that the rounding is done down,indicating rounding up. The L-phase clock CLKMP needs to satisfy the requirement of the same frequency and the phase difference of 360 °/L, and can be derived from a numerical control delay chain, a voltage-controlled oscillator, or other circuits that can generate the same frequency multi-phase clock. The value of L determines the divide value precision of the configurable fractional divider. The precision of the frequency division value is defined as P, and P is 1/L.

Table 1 configuration signal values

The rising edge reference clock selection circuit 101 receives a clock input signal CLKMP, configuration input signals PROG _ SEL _ R [ M:0], PROG _ FRAC [ M:0], and an internal control signal RISE _ WAIT. One of the clock signals is selected from the L CLKMP signals to be output to the internal clock signal RISE _ CLK by the control of PROG _ SEL _ R [ M:0], PROG _ FRAC [ M:0] and RISE _ WAIT. RISE _ CLK is transmitted to the low level control circuit 103 and the state selection circuit 105 to be used as a reference clock at the timing of the CLKOUT rising edge inversion.

The falling edge reference clock selection circuit 102 receives a clock input signal CLKMP, configuration input signals PROG _ SEL _ F [ M:0], PROG _ FRAC [ M:0], and an internal control signal FALL _ WAIT. One of the clock signals is selected from the L CLKMP and output to the internal clock signal FALL _ CLK by the control of PROG _ SEL _ F [ M:0], PROG _ FRAC [ M:0], and FALL _ WAIT. The FALL _ CLK is transmitted to the high level control circuit 104 and the state selection circuit 105 to be used as a reference clock at the falling edge inversion timing of CLKOUT.

The LOW level control circuit 103 receives a configuration input signal PROG _ LOW [ N:0], an internal control signal RISE _ WAIT, and an internal clock signal RISE _ CLK. When RISE _ WAIT is high, the LOW level control circuit 103 prepares a LOW level initial count value PROG _ LOW [ N:0 ]; when RISE _ WAIT is low, the low level control circuit 103 performs a subtraction of 1 from the low level count value until 0 is subtracted at each rising edge of RISE _ CLK. When the low-level count value is 0, the low-level control circuit 103 counts the high-level pulses of the indication signal DIVR synchronously outputted by half the RISE _ CLK clock period width.

The HIGH level control circuit 104 receives a configuration input signal PROG _ HIGH [ N:0], an internal control signal FALL _ WAIT, and an internal clock signal FALL _ CLK. When FALL _ WAIT is HIGH, the HIGH level control circuit 104 prepares a HIGH level initial count value PROG _ HIGH [ N:0 ]; when the FALL _ WAIT is low, the high level control circuit 104 performs the subtraction of the high level count value by 1 until it is subtracted to 0 at each rising edge of the FALL _ CLK. When the high-level count value is 0, the high-level control circuit 104 counts the high-level pulse of half the clock period width of the FALL _ CLK output synchronously with the instruction signal DIVF.

The state selection circuit 105 receives the configuration input signal PROG _ CTRL _ R, PROG _ CTRL _ F, the internal control signals DIVR, DIVF, and the internal clock signals RISE _ CLK, FALL _ CLK. Level switching is carried out on RISE _ WAIT and FALL _ WAIT through control of PROG _ CTRL _ R, PROG _ CTRL _ F, RISE _ CLK and FALL _ CLK at edges of DIVR and DIVF, and control over the working state of the configurable fractional frequency divider is achieved.

The output circuit 106 receives internal control signals DIVR, DIVF. When DIVR is high and DIVF is low, CLKOUT is changed from low to high; when DIVR is low and DIVF is high, CLKOUT is changed from high to low; the CLKOUT output remains unchanged when both DIVR and DIVF are low. Thereby achieving the correct fractional division function.

Fig. 2 is a schematic diagram of a rising edge reference clock selection circuit and a falling edge reference clock selection circuit in the configurable fractional frequency divider according to the present invention. The reference clock selection circuit includes an adder 201 and a multiplexer 202.

The adder 201 has inputs connected to PROG _ SEL _ R [ M:0]/PROG _ SEL _ F [ M:0], PROG _ FRAC [ M:0], RISE _ WAIT/FALL _ WAIT, RISE _ CLK/FALL _ CLK, and an output connected to the selection signals RISE _ SEL [ M:0]/FALL _ SEL [ M:0] of the multiplexer 202. The configuration signals PROG _ SEL _ R [ M:0]/PROG _ SEL _ F [ M:0] are initial values of selection signals RISE _ SEL [ M:0]/FALL _ SEL [ M:0], and on the first rising edge of RISE _ CLK/FALL _ CLK after RISE _ WAIT/FALL _ WAIT is high level, the adder performs an addition operation and outputs the addition operation to RISE _ SEL [ M:0]/FALL _ SEL [ M:0], so that RISE _ SEL [ M:0]/FALL _ SEL [ M:0] + PROG _ FRAC [ M:0] is realized.

The input end of the multiplexer 202 is connected with an L-phase clock CLKMP and selection signals RISE _ SEL [ M:0]/FALL _ SEL [ M:0], and the CLKMP of the corresponding phase is selected and output to RISE _ CLK/FALL _ CLK according to the control of the selection signals RISE _ SEL [ M:0]/FALL _ SEL [ M:0 ].

Fig. 3 is a schematic diagram of a low-level control circuit and a high-level control circuit in the configurable fractional frequency divider according to the present invention. The level control circuit includes a delay circuit 301, a load circuit 302, a down counter 303, and a detection circuit 304.

The input end of the delay circuit 301 is connected with RISE _ WAIT/FALL _ WAIT and RISE _ CLK/FALL _ CLK, and the output end is connected with RISE _ WAIT _ DL/FALL _ WAIT _ DL. The delay circuit 301 is an asynchronous set and synchronous reset circuit. When RISE _ WAIT/far _ WAIT switches from low level to high level, RISE _ WAIT _ DL/far _ WAIT _ DL immediately switches from low level to high level; when RISE _ WAIT/FALL _ WAIT switches from high to low, RISE _ WAIT _ DL/FALL _ WAIT _ DL switches from high to low upon encountering a rising edge of RISE _ CLK/FALL _ CLK.

The input end of the loading circuit 302 is connected with PROG _ LOW [ N:0]/PROG _ HIGH [ N:0], RISE _ WAIT _ DL/FALL _ WAIT _ DL, and the output end is connected with LOW _ INIT [ N:0]/HIGH _ INIT [ N:0 ]. When RISE _ WAIT _ DL/FALL _ WAIT _ DL is HIGH, the load circuit 302 transfers PROG _ LOW [ N:0]/PROG _ HIGH [ N:0] to LOW _ INIT [ N:0]/HIGH _ INIT [ N:0], and sets a value to the down counter 303; when RISE _ WAIT _ DL/FALL _ WAIT _ DL is LOW, the LOW _ INIT [ N:0]/HIGH _ INIT [ N:0] outputs are 0.

The down counter 303 has an input terminal connected to LOW _ INIT [ N:0]/HIGH _ INIT [ N:0], RISE _ WAIT _ DL/FALL _ WAIT _ DL, RISE _ CLK/FALL _ CLK, and an output terminal connected to LOW _ CNT [ N:0]/HIGH _ CNT [ N:0 ]. When RISE _ WAIT _ DL/FALL _ WAIT _ DL is HIGH, the LOW _ CNT [ N:0]/HIGH _ CNT [ N:0] outputs are 0; when RISE _ WAIT _ DL/FALL _ WAIT _ DL is LOW, the down counter 303 performs a count down of 1 every time RISE _ CLK/FALL _ CLK rising edge starts from the initial values LOW _ INIT [ N:0]/HIGH _ INIT [ N:0] until it is decremented to 0.

The input end of the detection circuit 304 is connected with LOW _ CNT [ N:0]/HIGH _ CNT [ N:0], RISE _ WAIT _ DL/FALL _ WAIT _ DL and RISE _ CLK/FALL _ CLK, and the output end is connected with DIVR/DIVF. When RISE _ WAIT _ DL/FALL _ WAIT _ DL is at high level, the DIVR/DIVF outputs low level; when RISE _ WAIT/FALL _ WAIT is LOW, the detection circuit 304 detects LOW _ CNT [ N:0]/HIGH _ CNT [ N:0], if LOW _ CNT [ N:0]/HIGH _ CNT [ N:0] is 0, DIVR/DIVF outputs a HIGH pulse half the RISE _ CLK/FALL _ CLK clock period width, otherwise DIVR/DIVF continues to output LOW.

Fig. 4 is a schematic diagram of a state selection circuit in the configurable fractional frequency divider according to the present invention. The state selection circuit includes inverters 401, 402, 404, 407, 411, 412, 414, 417, and gates 405, 415, nor gates 406, 416, clocked RS flip-flops 403, 413, RS flip-flops 408, 418, and an initialization circuit 400. The input end of the inverter 401 is connected with the output end of the RS trigger 408; the input end of the inverter 402 is connected to the rising edge indication signal DIVR; the clock end of the RS flip-flop 403 with the clock end is connected with a rising edge reference clock RISE _ CLK, the low level effective reset input end is connected with the output end of the inverter 401, and the low level effective set input end is connected with the output end of the inverter 402; the input end of the inverter 404 is connected with a configuration signal PROG _ CTRL _ F; one input end of the and gate 405 is connected with the output end of the inverter 404, and the other input end is connected with the falling edge indication signal DIVF; one input end of the nor gate 406 is connected with the output end of the and gate 405, and the other input end is connected with the output end of the clock end RS flip-flop 413; the input end of the inverter 407 is connected with the output end of the clock end RS flip-flop 403; the low level effective reset input end of the RS flip-flop 408 is connected to the output end of the nor gate 406, the low level effective set input end is connected to the output end of the inverter 407, and the output end is connected to the rising edge waiting signal RISE _ WAIT. The input end of the inverter 411 is connected with the output end of the RS flip-flop 418; the input end of the inverter 412 is connected with the falling edge indication signal DIVF; the clock end of the RS flip-flop with clock end 413 is connected to the falling edge reference clock FALL _ CLK, the active low reset input is connected to the output of the inverter 411, and the active low set input is connected to the output of the inverter 412; the input end of the inverter 414 is connected with a configuration signal PROG _ CTRL _ R; one input terminal of the and gate 415 is connected to the output terminal of the inverter 414, and the other input terminal is connected to the rising edge indication signal DIVR; one input end of the nor gate 416 is connected with the output end of the and gate 415, and the other input end is connected with the output end of the clock end RS flip-flop 403; the input end of the inverter 417 is connected with the output end of the clock end RS trigger 413; the RS flip-flop 418 has an active low reset input coupled to the output of the nor gate 416, an active low set input coupled to the output of the inverter 417, and an output coupled to the falling edge WAIT signal FALL _ WAIT. The output terminal of the initialization circuit 400 is connected to RISE _ WAIT and FALL _ WAIT. Truth tables for the clocked RS flip-flops 403,413 are shown in table 2. The truth table for the RS flip-flops 408, 418 is shown in table 3.

The initialization circuit 400 initializes RISE _ WAIT and FALL _ WAIT to a high level and controls RISE _ WAIT to switch from the high level to a low level when the configurable fractional divider starts to operate. After the configurable fractional frequency divider starts to work, according to the difference between PROG _ CTRL _ R and PROG _ CTRL _ F, RISE _ WAIT and FALL _ WAIT switch the level at the edges of DIVR and DIVF, thereby realizing the control of the working state of the configurable fractional frequency divider. When PROG _ CTRL _ R is 0, at the DIVR rising edge, far _ WAIT switches from high to low; on the DIVR falling edge, RISE _ WAIT switches from low to high. When PROG _ CTRL _ R is 1, RISE _ WAIT switches from low to high and FALL _ WAIT switches from high to low on the DIVR falling edge. When PROG _ CTRL _ F is 0, RISE _ WAIT switches from high to low on the rising edge of DIVF; at the falling edge of DIVF, FALL _ WAIT switches from low to high. When PROG _ CTRL _ F is 1, RISE _ WAIT switches from high to low and FALL _ WAIT switches from low to high on the falling edge of DIVF.

Fig. 5 is a schematic diagram of an output circuit in the configurable fractional frequency divider according to the present invention. The output circuit includes inverters 501-502, an RS flip-flop 503, and a buffer 504. The input end of the inverter 501 is connected with a falling edge indication signal DIVF; the input end of the inverter 502 is connected with a rising edge indication signal DIVR; the low-level effective reset input end of the RS trigger 503 is connected with the output end of the inverter 501, and the low-level effective set input end is connected with the output end of the inverter 502; the input terminal of the buffer 504 is connected to the output terminal of the RS flip-flop 503, and the output terminal is connected to the frequency-divided output signal CLKOUT. The truth table for the RS flip-flop 503 is shown in table 3. The flip of CLKOUT is controlled by the trigger of DIVR and DIVF, thereby realizing the frequency division function.

TABLE 2 truth table of RS flip-flops 403 and 413 with clock terminals

TABLE 3 RS flip-flops 408, 418, 503 truth table

RN	SN	Q
			0	0	1
0	1	0
			1	0	1
1	1	Holding

Fig. 6 is a waveform diagram of the eight-phase clock 5.375 frequency division according to an embodiment of the present invention. As shown in fig. 1, the precision P of the division value of the eight-phase clock is 0.125, the precision requirement of the division value is satisfied when the division value is 5.375, the number L of CLKMP clocks is 8, the phase difference is 45 °, the integer part I of the division value is 5, and the fractional part F of the division value is 375. M is 2, N is not less than 1, and the assignment condition of each configuration signal is as follows: PROG _ CTRL _ R is 0, PROG _ CTRL _ F is 0, PROG _ SEL _ R is 0, PROG _ SEL _ F is 5, PROG _ FRAC is 3, PROG _ LOW is 2, and PROG _ HIGH is 2. The 8 CLKMP clocks are CLKMP0 (phase is 0 °), CLKMP1 (phase is 45 °), CLKMP2 (phase is 90 °), CLKMP3 (phase is 135 °), CLKMP4 (phase is 180 °), CLKMP5 (phase is 225 °), CLKMP6 (phase is 270 °), and CLKMP7 (phase is 315 °), respectively.

Before time 0, the configurable fractional divider is in an initial state. The configuration of each configuration signal is completed according to a corresponding value, the CLKMP normally outputs an eight-phase clock, the RISE _ WAIT, FALL _ WAIT, RISE _ WAIT _ DL and FALL _ WAIT _ DL output HIGH levels, the DIVR, the DIVF and the CLKOUT output LOW levels, the RISE _ SEL is PROG _ SEL _ R (value is 0), the FALL _ SEL is PROG _ SEL _ F (value is 5), the LOW _ INIT is PROG _ LOW (value is 2), the HIGH _ INIT is PROG _ HIGH (value is 2), the LOW _ CNT is 0 and the HIGH _ CNT is 0.

At time 0, the configurable fractional divider begins to operate. RISE _ WAIT switches from high to low.

Under the control of RISE _ WAIT at time 1, the output RISE _ WAIT _ DL of the delay circuit 301 in the low level control circuit 103 switches from high level to low level on the rising edge of RISE _ CLK; under the control of RISE _ WAIT _ DL, the load circuit 302 in the LOW level control circuit 103 outputs LOW _ INIT to 0, and the down counter 303 in the LOW level control circuit 103 outputs LOW _ CNT to perform count down from 2.

At time 2, the down counter 303 in the LOW level control circuit 103 counts the output LOW _ CNT to 0; when a detection circuit 304 in the LOW-level control circuit 103 detects that LOW _ CNT is 0, the DIVR is output to output a high-level pulse with a half RISE _ CLK clock period width; when the DIVR is switched from a low level to a high level, the output fail _ WAIT of the state selection circuit 105 is switched from a high level to a low level, and the output CLKOUT of the output circuit 106 is switched from a low level to a high level.

At time 3, the DIVR's process of outputting a high pulse is complete, switching from high to low, and the output RISE _ WAIT of the state selection circuit 105 switches from low to high. Under the control of RISE _ WAIT, the delay circuit 301 in the low level control circuit 103 switches the RISE _ WAIT _ DL from low level to high level. Under the control of RISE _ WAIT _ DL, the load circuit 302 in the LOW level control circuit 103 outputs LOW _ INIT of 2.

At time 4, controlled by the FALL _ WAIT, the delay circuit 301 outputs the FALL _ WAIT _ DL to switch from the high level to the low level in the high level control circuit 104 on the rising edge of the FALL _ CLK. Under the control of the FALL _ WAIT _ DL, the load circuit 302 in the HIGH level control circuit 104 outputs HIGH _ INIT to 0, and the down counter 303 in the HIGH level control circuit 104 outputs HIGH _ CNT to perform count down from 2.

At the time 5, controlled by RISE _ WAIT, the adder 201 in the rising edge reference clock selection circuit 101 completes RISE _ SEL + PROG _ FRAC operation on RISE _ CLK rising edge, and outputs RISE _ SEL as 5; the multiplexer 202 in the rising edge reference clock selection circuit 101 selects CLKMP5 to be output to RISE _ CLK.

At time 6, the down counter 303 in the HIGH level control circuit 104 counts the output HIGH _ CNT to 0; when the detection circuit 304 in the HIGH level control circuit 104 detects that the HIGH _ CNT is 0, the output DIVF outputs a HIGH level pulse with a half of the clock period width of the well _ CLK; when the DIVF is switched from the low level to the high level, the output RISE _ WAIT of the state selection circuit 105 is switched from the high level to the low level, and the output CLKOUT of the output circuit 106 is switched from the high level to the low level.

At time 7, the process of outputting a high pulse from the DIVF is completed, the high level is switched to the low level, and the output of the state selection circuit 105, the FALL _ WAIT, is switched from the low level to the high level. Controlled by the fail _ WAIT, the delay circuit 301 in the high level control circuit 104 switches the output of the fail _ WAIT _ DL from the low level to the high level. Under the control of the FALL _ WAIT _ DL, the loading circuit 302 in the HIGH level control circuit 104 outputs HIGH _ INIT as 2.

At time 8, controlled by RISE _ WAIT, the delay circuit 301 in the low level control circuit 103 switches RISE _ WAIT _ DL from high to low on the rising edge of RISE _ CLK. Under the control of RISE _ WAIT _ DL, the load circuit 302 in the LOW level control circuit 103 outputs LOW _ INIT to 0, and the down counter 303 in the LOW level control circuit 103 outputs LOW _ CNT to perform count down from 2.

At time 9, controlled by FALL _ WAIT, the adder 201 in the falling edge reference clock selection circuit 102 completes the operation of FALL _ SEL + PROG _ FRAC on the rising edge of FALL _ CLK, and outputs FALL _ SEL as 0; the falling edge reference clock selection circuit 102 has a multiplexer 202 that selects CLKMP0 for output to FALL _ CLK.

At time 10, the down counter 303 in the LOW level control circuit 103 counts the output LOW _ CNT to 0; when a detection circuit 304 in the LOW-level control circuit 103 detects that LOW _ CNT is 0, the DIVR is output to output a high-level pulse with a half RISE _ CLK clock period width; when the DIVR is switched from a low level to a high level, the output fail _ WAIT of the state selection circuit 105 is switched from a high level to a low level, and the output CLKOUT of the output circuit 106 is switched from a low level to a high level.

To this end, the fractional divider may be configured from time 2 to time 10 to perform a frequency division of 5.375 once and cycle through subsequent frequency divisions.

Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.