阅读说明：本技术 一种长度3n四相非周期互补序列对信号生成方法及装置 (Method and device for generating length 3N four-phase aperiodic complementary sequence pair signal ) 是由 李国军 曾凡鑫 周晓娜 叶昌荣 于 2020-12-22 设计创作，主要内容包括：本发明属于通信系统技术领域,特别涉及一种长度3N四相非周期互补序列对信号生成方法及装置,其中所述装置包括控制电路、两个长度为N的输入移位寄存器、两个长度为3N的输出移位寄存器、七个乘法器、四个加法器以及两个开关,所述控制电路控制输入移位寄存器和输出移位寄存器的输入或/和输出以及控制开关的连接；本发明通过任意选取长度为N的二元戈莱互补序列对作为本发明的种子对,产生两路四相信号,将选取的二元戈莱互补序列对进行反相处理共形成三路二元信号,选择固定组合的三路信号从而获得序列长度3N、具有像冲激的非周期自相关函数和的四相非周期互补序列对；能够广泛应用于通信系统、雷达等装置中。(The invention belongs to the technical field of communication systems, and particularly relates to a 3N-length four-phase non-periodic complementary sequence pair signal generation method and a device, wherein the device comprises a control circuit, two input shift registers with the length of N, two output shift registers with the length of 3N, seven multipliers, four adders and two switches, wherein the control circuit controls the input or/and output of the input shift registers and the output shift registers and the connection of the control switches; according to the method, a binary Golay complementary sequence pair with the length of N is randomly selected to serve as a seed pair of the method, two paths of four-phase signals are generated, the selected binary Golay complementary sequence pair is subjected to phase inversion processing and is conformal to form three paths of binary signals, and the three paths of signals in fixed combination are selected, so that a four-phase non-periodic complementary sequence pair with the sequence length of 3N and an impulse-like non-periodic autocorrelation function is obtained; the method can be widely applied to devices such as communication systems and radars.)

1. A method for generating a length-3N four-phase aperiodic complementary pair signal, comprising the steps of:

s1, under the control of the control circuit, dividing the output code element of the first input shift register into three signals; dividing an output code element of the second input shift register into two paths of signals;

s2, outputting the first path of signal of the first input shift register to a first node, outputting the second path of signal to a seventh multiplier, outputting the signal to a second node after phase inversion, and outputting the third path of signal to the first multiplier;

s3, outputting the first path of signal of the second input shift register to a second multiplier, and outputting the second path of signal to a fifth node;

s4, outputting the output signal of the first multiplier to the first adder and the third multiplier, mixing the output signals of the second multiplier and the third multiplier, inputting the mixed signals to the second adder, and outputting the mixed signals to the fifth multiplier and the sixth multiplier; outputting the aliasing result of the fifth multiplier and the first adder to a third adder, and outputting the aliasing result to a third node by the third adder;

s5, outputting the output signal of the first adder to a fourth multiplier, multiplying the fourth multiplier by a coefficient, outputting the result to a fourth adder, multiplying the sixth multiplier by a coefficient, outputting the result to the fourth adder, and outputting the alias signal received by the fourth adder to a fourth node;

and S6, controlling the second switch to be connected with the first input shift register, controlling the first switch to be sequentially connected with the fifth node, the third node and the second node to output three paths of signals, controlling the second switch to be connected with the second input shift register, controlling the first switch to be respectively connected with the fifth node, the fourth node and the first node to output three paths of signals until a four-phase aperiodic complementary sequence pair with the sequence length of 3N is obtained.

2. The method according to claim 1, wherein the first input shift register and the second shift register store a binary golay complementary sequence pair of arbitrary length N, (c (0),.., c (k),.., c (N-1)) and d, (d (0),.., d (k),..,. d (N-1)) in the first input shift register and the second shift register.

3. The method as claimed in claim 1, wherein the control circuit divides the signal generating process into N time slots, each time slot controls a corresponding symbol in the binary golay complementary sequence pair with length N, the four-phase aperiodic complementary sequence pair with length N is generated according to the processes of steps S1-S6, and the symbol generating operation of the next time slot is performed until the N time slots are completed, and the four-phase aperiodic complementary sequence pair with length 3N generated by the first output shift register and the second output shift register are output respectively.

4. The device for generating the signal of the length 3N four-phase non-periodic complementary sequence pair comprises a control circuit, two input shift registers with the length N, two output shift registers with the length 3N, seven multipliers, four adders and two switches, wherein the control circuit controls the input or/and output of the input shift registers and the output shift registers and the connection of the control switches;

the first input shift register is divided into three paths of outputs which are respectively connected with the seventh multiplier, the first node and the first multiplier; the second input shift register is divided into two paths of outputs which are respectively connected with the second multiplier and the fifth node;

the first multiplier is divided into two paths of outputs which are respectively connected with the first adder and the third multiplier; the second multiplier is divided into two paths of outputs which are respectively connected with the first adder and the second adder;

the first adder is divided into two paths of outputs which are respectively connected with the third adder and the fourth multiplier; the third adder outputs to a third node; the fourth multiplier multiplies the coefficient and outputs the multiplied coefficient to a fourth adder;

the third multiplier multiplies the coefficient and outputs the multiplied coefficient to a second adder; the second adder is respectively connected with a fifth multiplier and a sixth multiplier; the fifth multiplier is multiplied by a coefficient and then connected with a third adder, and the sixth multiplier is multiplied by the coefficient and then output to a fourth adder; outputting an output signal of the fourth adder to a fourth node;

the first switch controls connection with a first node, a second node, a third node, a fourth node and a fifth node; the second switch controls connection with the first output shift register and the second output shift register, and the first switch is communicated with the second switch.

5. The apparatus according to claim 4, wherein the multiplication coefficient values of the first multiplier and the second multiplier are the same and the sum is 1; the multiplication coefficient values of the third multiplier, the sixth multiplier and the seventh multiplier are the same and the sum thereof is-3, and the multiplication coefficient values of the fourth multiplier and the fifth multiplier are imaginary units that are opposite numbers to each other and the sum thereof is 0.

Technical Field

The invention belongs to the technical field of communication systems, and particularly relates to a method and a device for generating a signal of a four-phase aperiodic complementary sequence pair with the length of 3N.

Background

The aperiodic complementary sequence pair is composed of two sequences of equal length, and the sum of the aperiodic autocorrelation functions of the two sequences is a discrete impulse function. The aperiodic complementary sequence pair plays an important role in communication, and can be used for synchronization, interference suppression, multi-carrier peak power control, and the like (s.y.sun, h.h Chen, and w.x.meng, "a survey on complimented MIMO CDMA wireless communications", IEEE com.surveys tuts, vol.17, No.1, pp.52-69,1st query 2015.). In radar, it can be applied to radar clutter suppression (G.Weathers and E.M.Holliday, "Group-compensated array coding for radar closure", IEEE trans.Aerosp.Electron.Syst, vol.AES-19, No.3, pp.369-379, May 1983.), radar resolution improvement (J.A.LeMieux and F.M.Ingels, "Analysis of FSK/PSK modulated radar signals using sample as arrays and complementary weather codes", Proc.Rec.IEEE int.radio Conf.,1990, pp.589-594), and so on. In addition, it can be used for digital watermarking (y.horii and t.kojima, "On digital watermarks based On complete complementary codes", proc.int.workhop Signal Design. command, 2009, pp.126-129), ultrasonic imaging (c.canon, j.hannah, and s.mclaughlin, "Segmented motion compensation for complementary encoded ultrasonic imaging", IEEE trans.ultrason, ferro-, freq.control, vol.57, No.5, pp.1039-1050, May be used), etc.

The aperiodic complementary sequence pair can be divided into a binary aperiodic complementary sequence pair, a four-phase aperiodic complementary sequence pair, and the like. In contrast, a four-phase aperiodic complementary sequence pair has more sequence length than a binary aperiodic complementary sequence pair. The length of the binary aperiodic complementary sequence must satisfy 2^α10^β26^γWherein α, β, γ are non-negative integers, and the length of the binary aperiodic complementary sequence must be the sum of the squares of 2 integers. The four-phase aperiodic complementary sequence has a length of 2,3,4,5,6,8,10,11,12,13,16,18,20,22,24,26, ….

It follows that there may still be four phases of aperiodic complementary sequence pairs over the length over which binary aperiodic complementary sequence pairs do not exist. Therefore, in application, the four-phase aperiodic complementary sequence pair can better meet the design requirements of users.

Four-phase aperiodic complementary Sequence pairs although studied for many years (p.z.fan and m.darnell, Sequence design for communications applications, John Wiley & Sons inc.,1996), the prior art has few methods for constructing four-phase aperiodic complementary Sequence pairs and cannot produce sequences of the full desired length, especially odd length; and the defects of complex construction process, difficult realization process and the like exist.

Disclosure of Invention

The invention provides a method and a device for generating a four-phase aperiodic complementary sequence pair signal with the length of 3N, in order to obtain a four-phase aperiodic complementary sequence pair with simple structure and easy realization.

The invention solves the technical problems mentioned in the background technology by the following technical proposal:

in a first aspect of the present invention, the present invention provides a length 3N four-phase aperiodic complementary sequence pair signal generation method, including the steps of:

s1, under the control of the control circuit, dividing the output code element of the first input shift register into three signals; dividing an output code element of the second input shift register into two paths of signals;

s2, outputting the first path of signal of the first input shift register to a first node, outputting the second path of signal to a seventh multiplier, outputting the signal to a second node after phase inversion, and outputting the third path of signal to the first multiplier;

s3, outputting the first path of signal of the second input shift register to a second multiplier, and outputting the second path of signal to a fifth node;

s4, outputting the output signal of the first multiplier to the first adder and the third multiplier, mixing the output signals of the second multiplier and the third multiplier, inputting the mixed signals to the second adder, and outputting the mixed signals to the fifth multiplier and the sixth multiplier; outputting the aliasing result of the fifth multiplier and the first adder to a third adder, and outputting the aliasing result to a third node by the third adder;

s5, outputting the output signal of the first adder to a fourth multiplier, multiplying the fourth multiplier by a coefficient, outputting the result to a fourth adder, multiplying the sixth multiplier by a coefficient, outputting the result to the fourth adder, and outputting the alias signal received by the fourth adder to a fourth node;

and S6, controlling the second switch to be connected with the first input shift register, controlling the first switch to be sequentially connected with the fifth node, the third node and the second node to output three paths of signals, controlling the second switch to be connected with the second input shift register, controlling the first switch to be respectively connected with the fifth node, the fourth node and the first node to output three paths of signals until a four-phase aperiodic complementary sequence pair with the sequence length of 3N is obtained.

Preferably, the control circuit divides the signal generating process into N time slots, each time slot controls a corresponding symbol in the binary golay complementary sequence pair with the length of N, generates a four-phase aperiodic complementary sequence pair of the time slot according to the processes of steps S1 to S6, performs symbol generating operation of the next time slot, and outputs the four-phase aperiodic complementary sequence pair with the length of 3N, which is generated by the first output shift register and the second output shift register, respectively, until the N time slots are operated completely.

In a second aspect of the present invention, the present invention further provides a length-3N four-phase aperiodic complementary sequence pair signal generating apparatus, which includes a control circuit, two length-N input shift registers, two length-3N output shift registers, seven multipliers, four adders and two switches, wherein the control circuit controls the input or/and output of the input shift register and the output shift register and the connection of the control switches;

the first input shift register is divided into three paths of outputs which are respectively connected with the seventh multiplier, the first node and the first multiplier; the second input shift register is divided into two paths of outputs which are respectively connected with the second multiplier and the fifth node;

the first multiplier is divided into two paths of outputs which are respectively connected with the first adder and the third multiplier; the second multiplier is divided into two paths of outputs which are respectively connected with the first adder and the second adder;

the first adder is divided into two paths of outputs which are respectively connected with the third adder and the fourth multiplier; the third adder outputs to a third node; the fourth multiplier multiplies the coefficient and outputs the multiplied coefficient to a fourth adder;

the third multiplier multiplies the coefficient and outputs the multiplied coefficient to a second adder; the second adder is respectively connected with a fifth multiplier and a sixth multiplier; the fifth multiplier is multiplied by a coefficient and then connected with a third adder, and the sixth multiplier is multiplied by the coefficient and then output to a fourth adder; outputting an output signal of the fourth adder to a fourth node;

the first switch controls connection with a first node, a second node, a third node, a fourth node and a fifth node; the second switch controls connection with the first output shift register and the second output shift register, and the first switch is communicated with the second switch.

The invention has the beneficial effects that:

the invention provides a method and a device for generating signals by using four-phase aperiodic complementary sequence pairs with the length of 3 N.A binary Golay complementary sequence c and d pair with the length of N is randomly selected as a seed pair of the method to generate two paths of four-phase signals, one of the selected binary Golay complementary sequence pair is subjected to phase inversion processing, three paths of binary signals are formed by the two paths of four-phase signals, and five paths of output nodes are formed; the five paths of output nodes comprise an output sequence c, a sequence-c, a sequence d and the other two sequences; the other two sequences which meet the conditions can be output by flexibly utilizing the adder and the multiplier; in the invention, three sequences in five sequence representations of a sequence c, a sequence-c, a sequence d and other two sequences are selected according to a combined mode, and a sequence e and a sequence f with the sequence length of 3N are finally obtained, wherein the sum of non-periodic autocorrelation functions of the two sequences e and f is an impulse function, so that the sequence e and the sequence f have four-phase non-periodic complementary sequence pairs like the sum of the non-periodic autocorrelation functions of the impulse; the seed pair in the invention can be directly used as a part of the final output sequence, so that the detection of the sequence generation result can be facilitated.

Drawings

FIG. 1 is a schematic block diagram of a length 3N four-phase aperiodic complementary pair signal and apparatus according to the present invention;

FIG. 2 is a flow chart of a method for generating a 3N-length four-phase aperiodic complementary pair signal according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a structural diagram of a length 3N four-phase aperiodic complementary sequence pair signal generating device according to the present invention, which, as shown in fig. 1, includes a control circuit, two length N input shift registers, two length 3N output shift registers, seven multipliers, four adders and two switches, wherein the control circuit controls the input or/and output of the input shift register and the output shift register and the connection of the control switches;

the first input shift register is divided into three paths of outputs which are respectively connected with the seventh multiplier, the first node and the first multiplier; the second input shift register is divided into two paths of outputs which are respectively connected with the second multiplier and the fifth node;

the first multiplier is divided into two paths of outputs which are respectively connected with the first adder and the third multiplier; the second multiplier is divided into two paths of outputs which are respectively connected with the first adder and the second adder;

the first adder is divided into two paths of outputs which are respectively connected with the third adder and the fourth multiplier; the third adder outputs to a third node; the fourth multiplier multiplies the coefficient and outputs the multiplied coefficient to a fourth adder;

the third multiplier multiplies the coefficient and outputs the multiplied coefficient to a second adder; the second adder is respectively connected with a fifth multiplier and a sixth multiplier; the fifth multiplier is multiplied by a coefficient and then connected with a third adder, and the sixth multiplier is multiplied by the coefficient and then output to a fourth adder; outputting an output signal of the fourth adder to a fourth node;

the first switch controls connection with a first node, a second node, a third node, a fourth node and a fifth node; the second switch controls connection with the first output shift register and the second output shift register, and the first switch is communicated with the second switch.

It is understood that, in fig. 1, for convenience of describing each device, the description of each device is modified accordingly, for example, the input shift register includes a first input shift register and a second input shift register, which refer to the input shift register a and the input shift register B, respectively; the output shift register comprises a first output shift register and a second output shift register which respectively refer to an output shift register A and an output shift register B; in addition, the nodes A, B, D, F and G represent a first node, a second node, a third node, a fourth node, and a fifth node in this order; multiplier 1 refers to the first multiplier, adder 1 refers to the first adder, and so on.

In a preferred embodiment, the multiplication coefficient values of the first multiplier and the second multiplier are the same and the sum thereof is 1; the multiplication coefficient values of the third multiplier, the sixth multiplier and the seventh multiplier are the same and the sum thereof is-3, and the multiplication coefficient values of the fourth multiplier and the fifth multiplier are imaginary units that are opposite numbers to each other and the sum thereof is 0.

In the generating apparatus diagram shown in fig. 1, it can be seen intuitively that the first node a directly outputs the sequence data in the first input shift register, the fifth node G directly outputs the sequence data in the second input shift register, and the second node directly outputs the inverted data of the sequence data in the first input shift register; the output data of the third node and the fourth node depend on the matching of each multiplier and each adder, the output data of three nodes are selected in sequence according to an organic combination mode, and the output data selected twice form a pair of four-phase non-periodic complementary sequence pair signals with the length of 3N.

On the basis of a generating device, in order to more intuitively show the generating method of the present invention, fig. 2 is a flowchart of a length-3N four-phase aperiodic complementary sequence pair signal generating method, as shown in fig. 2, and the steps of the signal generating method are shown in fig. 2:

s1, under the control of the control circuit, dividing the output code element of the first input shift register into three signals; dividing an output code element of the second input shift register into two paths of signals;

first, the sequences of the first input shift register and the second input shift register are both a pair of complementary sequences with a length of N, in this embodiment, a pair of binary golay complementary sequences with a length of N, c (0),. so, c (k),. so, c (N-1)) and d (0),. so, d (k),. so, d (N-1)) are taken as an example of a seed pair, the first input shift register stores c (0),. so, c (k),. so, c (N-1)), and the second input shift register stores d (0),. so, d (k),. so, d (N-1)).

In order to generate a four-phase aperiodic complementary sequence pair signal with the length of 3N, a control circuit designed by the invention divides the generation process into N time slots; in the k-th time slot, under the control of the control circuit, the first input shift register outputs a code element c (k-1) which is divided into three signals. Meanwhile, the second input shift register B outputs a symbol d (k-1), which is divided into two signals.

S2, outputting the first path of signal of the first input shift register to a first node, outputting the second path of signal to a seventh multiplier, outputting the signal to a second node after phase inversion, and outputting the third path of signal to the first multiplier;

the first path of signal of the first input shift register is sent to the first node A, the signal on the first node A is the code element c (k-1), the second path of signal is multiplied by-1 by the seventh multiplier and sent to the second node B, the signal on the second node B is the code element-c (k-1), the third path of signal is sent to the first multiplier and multiplied by 1/2, and the product signal is the code element c (k-1)/2.

And S3, outputting the first path of signal of the second input shift register to the second multiplier, and outputting the second path of signal to the fifth node.

The first signal of the second input shift register is sent to the fifth node G, the signal on the fifth node G is the code element d (k-1), the second signal is sent to the second multiplier to be multiplied by 1/2, and the product signal is the code element d (k-1)/2

S4, outputting the output signal of the first multiplier to the first adder and the third multiplier, mixing the output signals of the second multiplier and the third multiplier, inputting the mixed signals to the second adder, and outputting the mixed signals to the fifth multiplier and the sixth multiplier; outputting the aliasing result of the fifth multiplier and the first adder to a third adder, and outputting the aliasing result to a third node by the third adder;

the output signal c (k-1)/2 of the first multiplier is divided into two paths of signals, one path of signal is sent to the first adder, the other path of signal is sent to the third multiplier to be multiplied by-1, and the output signal [ c (k-1) + D (k-1) ]/2+ j [ D (k-1) -c (k-1) ]/2 of the third adder is sent to the third node D. The product of the two signals, namely, the product of the two signals, namely, k-1)/2.

S5, outputting the output signal of the first adder to a fourth multiplier, multiplying the fourth multiplier by a coefficient, outputting the result to a fourth adder, multiplying the sixth multiplier by a coefficient, outputting the result to the fourth adder, and outputting the alias signal received by the fourth adder to a fourth node;

output signal of the first adder [ c (k-1) + d (k-1)]A/2 is divided into two paths of signals, one path of signal is sent to a third adder, the other path of signal is sent to a fourth multiplier to be multiplied by-j, and the product of-j [ c (k-1) + d (k-1)]The/2 is sent to the fourth adder, where j is the imaginary unit, j²Output signal of the second adder [ d (k-1) -c (k-1) ] -1]A/2 is divided into two paths, one path is sent to a fifth multiplier to be multiplied by j, and the product of j [ d (k-1) -c (k-1)]The other signal is sent to a sixth multiplier to be multiplied by-1, and the product is d (k-1) -c (k-1)]And/2 is sent to the fourth adder. The output signal of the fourth adder-j [ c (k-1) + d (k-1)]/2-[d(k-1)-c(k-1)]And/2 to the fourth node F.

And S6, controlling the second switch to be connected with the first input shift register, controlling the first switch to be sequentially connected with the fifth node, the third node and the second node to output three paths of signals, controlling the second switch to be connected with the second input shift register, controlling the first switch to be respectively connected with the fifth node, the fourth node and the first node to output three paths of signals until a four-phase aperiodic complementary sequence pair with the sequence length of 3N is obtained.

In one embodiment, this embodiment presents a combined approach:

the control circuit controls the second switch K₂Connected to node H, a first switch K₁Connected to a fifth node G, a signal d (K-1) at the point G of the fifth node is stored in a first output shift register A, and then a first switch K₁Connected to the third node D, D is the signal [ c (k-1) + D (k-1)]/2+j[d(k-1)-c(k-1)]/2 is stored in the first output shift register A, then the first switch K₁Connected to the second node B, the B signal-c (K-1) is stored in the first output shift register A, and after the signal generation work of the first output shift register A in the K time slot is completed, the control circuit controls the second switch K₂Connected to node E, a first switch K₁Connected to the fifth node G, the G point signal d (K-1) is stored in the second output shift register B, and then the first switch K₁Connected to a fourth node F, F is a signal-j [ c (k-1) + d (k-1)]/2-[d(k-1)-c(k-1)]/2 is stored in the second output shift register B, and then the first switch K₁Connected to the first node A, the signal c (K-1) at the point A is stored in the second output shift register B, and after the signal generation work of the second output shift register B at the kth time slot is completed, the switch is finally turned off, namely, the first switch K is connected₁Connected to node P, a second switch K₂Connected to node Q.

In some preferred embodiments, the control circuit controls to continue the symbol generation operation of the next time slot until the N time slots are completed, and the output first output shift register a and the output second output shift register B respectively generate signals of a four-phase sequence pair e and f with the length of 3N, wherein e and f form a four-phase aperiodic complementary sequence pair with the length of 3N.

In the description of the present invention, it is to be understood that the terms "coaxial", "bottom", "one end", "top", "middle", "other end", "upper", "one side", "top", "inner", "outer", "front", "center", "both ends", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "disposed," "connected," "fixed," "rotated," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; the terms may be directly connected or indirectly connected through an intermediate, and may be communication between two elements or interaction relationship between two elements, unless otherwise specifically limited, and the specific meaning of the terms in the present invention will be understood by those skilled in the art according to specific situations.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.