阅读说明：本技术 高精度两步型逐次逼近寄存器模数转换器 (High-precision two-step successive approximation register analog-to-digital converter ) 是由 姚剑锋 王自鑫 张顺 袁凤江 杨锐佳 胡炳翔 于 2020-12-18 设计创作，主要内容包括：本发明属于模拟集成电路技术领域,具体涉及一种高精度两步型逐次逼近寄存器模数转换器,包括采样保持电路、第一级子模数转换器、第二级子模数转换器、逐次逼近寄存器逻辑电路、并行转串行接口电路,采样保持电路与第一级子模数转换器连接,第一级子模数转换器与第二级子模数转换器连接,第一级子模数转换器和第二级子模数转换器分别与逐次逼近寄存器逻辑电路连接,逐次逼近寄存器逻辑电路与并行转串行接口电路连接,第一级子模数转换器和第二级子模数转换器还分别与动态比较器连接,在连接第一级子模数转换器与第二级子模数转换器的电路上还设置有余量放大器和数字校准模块。本发明在大幅度提高SAR ADC精度的同时,改善了其总体性能。(The invention belongs to the technical field of analog integrated circuits, and particularly relates to a high-precision two-step successive approximation register analog-digital converter which comprises a sampling holding circuit, a first-stage sub analog-digital converter, a second-stage sub analog-digital converter, a successive approximation register logic circuit and a parallel-to-serial interface circuit, wherein the sampling holding circuit is connected with the first-stage sub analog-digital converter, the first-stage sub analog-digital converter is connected with the second-stage sub analog-digital converter, the first-stage sub analog-digital converter and the second-stage sub analog-digital converter are respectively connected with the successive approximation register logic circuit, the successive approximation register logic circuit is connected with the parallel-to-serial interface circuit, the first-stage sub analog-digital converter and the second-stage sub analog-digital converter are also respectively connected with, and a margin amplifier and a digital calibration module are also arranged on a circuit connecting the first-stage sub analog-digital converter and the second-stage sub analog-digital converter. The invention improves the overall performance of the SAR ADC while greatly improving the precision of the SAR ADC.)

1. The utility model provides a high accuracy two-step type successive approximation register analog-to-digital converter, includes sample hold circuit, second level sub analog-to-digital converter, successive approximation register logic circuit, parallel changes serial interface circuit, its characterized in that: the device also comprises a first-stage sub analog-digital converter; the sampling holding circuit is connected with the first-stage sub analog-to-digital converter, the first-stage sub analog-to-digital converter is connected with the second-stage sub analog-to-digital converter, the first-stage sub analog-to-digital converter and the second-stage sub analog-to-digital converter are respectively connected with the successive approximation register logic circuit, the successive approximation register logic circuit is connected with the parallel-to-serial interface circuit, the first-stage sub analog-to-digital converter and the second-stage sub analog-to-digital converter are respectively connected with the dynamic comparator, a margin amplifier and a digital calibration module are further arranged on a circuit connecting the first-stage sub analog-to-digital converter and the second-stage sub analog-to-digital converter, one end of the margin amplifier is connected with the first-stage sub analog-to-digital converter through a first switch.

2. A high accuracy two-step successive approximation register analog-to-digital converter as claimed in claim 1, wherein: the first-stage sub analog-digital converter comprises a positive capacitor array consisting of 14 capacitors, a negative capacitor array consisting of 14 capacitors and a comparator; in the positive capacitor array and the negative capacitor array, the first 8 capacitors are divided into one group, the last five capacitors are divided into another group, and the other capacitor is used as a matched capacitor; the lower plate of the capacitor is connected to a differential input voltage, the upper plate of the capacitor is selectively connected to a reference voltage or grounded through an analog switch, and the upper plate of the capacitor is provided with two reference voltages, one of the two reference voltages is used as the reference voltage of the first 8 capacitors, and the other reference voltage is used as the reference voltage of the last five capacitors; the upper-level plate of the matching capacitor is connected with the reference voltages of the first 8 capacitors; the comparator outputs signals by comparing the differential input voltage of the lower plate of the positive capacitor array with the differential input voltage of the lower plate of the negative capacitor array.

3. The high accuracy two-step successive approximation register analog-to-digital converter of claim 2, wherein said second stage sub-analog-to-digital converter comprises a positive capacitance array of 8 capacitors, a negative capacitance array of 8 capacitors, and a comparator; the lower plate of the capacitor is connected to a differential input voltage and has a reference voltage, and the upper plate is selectively connected to the reference voltage or ground through an analog switch.

Technical Field

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a high-precision two-step successive approximation register analog-to-digital converter.

Background

A successive approximation register analog-to-digital converter (SAR ADC), also called binary analog-to-digital converter, is an integrated circuit structure that converts an analog quantity into a digital quantity that can be recognized by an information processing device such as a computer. The SAR ADC is widely used due to its small area, low power consumption, and the like.

The SAR ADC has many technical indexes including resolution, effective number of bits (ENOB), precision, slew rate, differential non-linear error (DNL), integral non-linear error (INL), signal-to-noise ratio, power consumption, and chip area. In the method, some technical indexes are difficult to be compatible, and taking precision and chip area as an example, in isolation, the higher the precision of the SAR ADC is, the better the chip area is, but the improvement of the precision often causes the increase of the chip area, thereby affecting the overall performance of the SAR ADC. Therefore, the accuracy of the SAR ADC commonly used in current production and scientific practice is 8-10 bits. The specific reasons are as follows:

the improvement of the precision of the SAR ADC can cause the high-order capacitance to be obviously increased, so that the matching degree of the capacitance is reduced or the area is increased. Although the size of the high-order capacitor can be reduced by building the capacitor array in a bridge manner, in the bridge capacitor array, the size of the bridge capacitor is not integral multiple of the unit capacitor, so that the matching degree of the capacitor is reduced, and the conversion accuracy of the SAR ADC is also reduced. If the conventional capacitor array is used, the size of the capacitor is increased by 2^ i (i is the power of 2 and i is the precision digit) with the improvement of precision, so that the size of the capacitor with the highest bit is obviously increased, the area of a chip is increased, the power consumption of a circuit is increased, the time required for sampling is shortened, and the like, and the performances of the chip are affected.

Disclosure of Invention

The object of the present invention is to effectively improve the accuracy of SAR ADCs and to improve their overall performance, thus overcoming the drawbacks of the prior art mentioned above. The purpose is realized by the following technical scheme:

a high-precision two-step successive approximation register analog-to-digital converter comprises a sampling holding circuit, a first-stage sub analog-to-digital converter, a second-stage sub analog-to-digital converter, a successive approximation register logic circuit and a parallel-to-serial interface circuit, wherein the sampling holding circuit is connected with the first-stage sub analog-to-digital converter, the first-stage sub analog-to-digital converter is connected with the second-stage sub analog-to-digital converter, the first-stage sub analog-to-digital converter and the second-stage sub analog-to-digital converter are respectively connected with the successive approximation register logic circuit, the successive approximation register logic circuit is connected with the parallel-to-serial interface circuit, the first-stage sub analog-to-digital converter and the second, and a margin amplifier (RA) and a digital calibration module are also arranged on a circuit connecting the first-stage sub analog-digital converter and the second-stage sub analog-digital converter, and one end of the margin amplifier passes through the first switch (S)._DMC1) Connected with the first-stage sub analog-digital converter, and the other end of the residue amplifier passes through a second switch (S)_DMC2) And is connected with the second-stage sub analog-digital converter.

On the basis of the technical scheme, the invention can be added with the following technical means so as to better or more specifically realize the purpose of the invention:

the first-stage sub analog-digital converter comprises a positive capacitor array consisting of 14 capacitors, a negative capacitor array consisting of 14 capacitors and a comparator; in the positive capacitor array and the negative capacitor array, the first 8 capacitors are divided into one group, the last five capacitors are divided into another group, and the other capacitor is used as a matched capacitor; the lower plate of the capacitor is connected with differential input voltage (VP, VN), the upper plate is selectively connected with reference voltage or Ground (GND) through an analog switch, and the lower plate of the capacitor is provided with two reference voltages (VR, VR1), one is used as the reference Voltage (VR) of the first 8 capacitors, and the other is used as the reference voltage (VR1) of the last five capacitors; the upper plate of the matching capacitor is connected with the reference Voltages (VR) of the first 8 capacitors; the comparator outputs signals by comparing the magnitude of the differential input Voltage (VP) of the lower plate of the positive capacitor array with the magnitude of the differential input Voltage (VN) of the lower plate of the negative capacitor array.

Further, the second-stage sub analog-digital converter comprises a positive capacitor array consisting of 8 capacitors, a negative capacitor array consisting of 8 capacitors and a comparator; the lower plate of the capacitor is connected to a differential input voltage and has a reference Voltage (VR), and the upper plate is selectively connected to the reference voltage or ground through an analog switch.

The invention has the following beneficial effects:

the invention utilizes a comparator to compare the differential input voltage VP and VN of the lower stage plate of the positive and negative capacitor array to generate output, and then the SAR logic circuit generates a control signal to switch the switch of the upper stage plate of the capacitor array, so that the signal is connected to a reference voltage (VR or VR1) or Ground (GND). Due to the special capacitor array structure of the first-stage sub ADC, the maximum capacitor array is 2^7C (unit capacitance), and under the high precision of 22 bits, the capacitor in the invention is not too large, thereby being beneficial to reducing the chip area and the circuit power consumption. In conclusion, the SAR ADC precision is greatly improved, and the overall performance of the SAR ADC is improved.

Drawings

FIG. 1 is a schematic diagram of the general structure of the present invention;

FIG. 2 is a schematic diagram of a first stage sub-ADC capacitor array according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a second-stage sub-ADC capacitor array according to an embodiment of the invention.

Detailed Description

The technical solution and the working method thereof of the present invention are described in detail below by an embodiment with reference to the accompanying drawings.

As shown in FIG. 1, the high-precision two-step successive approximation register analog-to-digital converter of the present invention comprises a sample-and-hold circuit (SH), a first-stage sub analog-to-digital converter (first-stage sub ADC), and a second-stage sub analog-to-digital converter (second-stage sub ADC)The system comprises a second-stage sub-ADC (analog-to-digital converter), a successive approximation register logic circuit (SAR) and a parallel-to-serial interface circuit, wherein a sampling holding circuit is connected with a first-stage sub-analog-to-digital converter, the first-stage sub-analog-to-digital converter is connected with a second-stage sub-analog-to-digital converter, the first-stage sub-analog-to-digital converter and the second-stage sub-analog-to-digital converter are respectively connected with the successive approximation register logic circuit, the successive approximation register logic circuit is connected with the parallel-to-serial interface circuit, the first-stage sub-analog-to-digital converter and the second-stage sub-analog-to-digital converter are also respectively connected with a dynamic comparator, a margin amplifier RA and a digital calibration module are further arranged on a_DMC1The other end of the margin amplifier is connected with the first-stage sub analog-digital converter through a second switch S_DMC2And is connected with the second-stage sub analog-digital converter.

As shown in fig. 2, in this embodiment, the structure of the first-stage sub analog-to-digital converter is as follows:

a forward capacitor array including 13 capacitors CP12-CP0 and 1 matching capacitor CP (the black dots in the figure represent the omitted capacitors CP 1-CP 3, CP7-CP 10); the 8 capacitors CP12-CP5 are used as a first group, and the capacitance values are reduced from CP12 to CP5 in sequence; the remaining capacitances CP4-CP0 serve as a second set, with capacitance values decreasing in order from CP4 to CP 0. The lower plate of the forward capacitor array is connected with the differential input voltage VP, and the upper plate is connected with one end of the forward control switch group SP12-SP 0; the other end of the control switch group SP12-SP0 will be selectively connected to a reference voltage (VR or VR1) or Ground (GND) as controlled by the SAR logic.

A negative capacitance array comprising 13 capacitances CN12-CN0 and 1 matching capacitance CN (the black dots in the figure represent the omitted capacitances CN 1-CN 3, CN7-CN 10)); wherein, 8 capacitors CN12-CN5 are used as a first group, and the capacitance values are reduced from CN12 to CN5 in sequence; the remaining capacitors CN4-CN0 are used as a second group, and the capacitance values are reduced from CN4 to CN0 in sequence; the lower plate of the negative capacitor array is connected with a differential input voltage VN, and the upper plate is connected with one end of the positive control switch group SN12-SN 0; the other end of the control switch bank SN12-SN0 will be selected to be connected to a reference voltage (VR or VR1) or Ground (GND) as controlled by the SAR logic.

The first-stage sub analog-to-digital converter is also connected with a dynamic comparator, and the dynamic comparator is used for comparing voltage values of lower-stage plates of capacitors controlled by the SAR logic circuit, so that an output value is generated and then enters the SAR logic circuit.

In the first-stage sub-ADC, the capacitance value of the first 8 capacitors CP12-CP5 (or CN12-CN5) is CPi ═ 2^ (i-5) C, and the reference voltage connected with it is VR; the remaining 5 capacitors CP4-CP1 (or CN4-CN1) have a capacitance value CPi ^ (i-1) C, CP0 ^ CP1 and a connected reference voltage VR1 ═ VR/8.

The matching capacitor CP (or CN) is 17C, and the steps in the first 14-bit conversion process comprise the following two stages:

in the first stage, the lower plate of the positive and negative capacitor array is connected to differential input voltages VP and VN, and the switch of the upper plate is connected to VR or VR1 for sampling, so that the capacitors are charged;

in the second stage, the lower-level board switch is disconnected and is in a virtual empty state, the upper-level board switch is unchanged, the upper-level board switch is in a holding state, the total charge is redistributed due to the fact that values of VR and VR1 are different, and the voltage calculation formula of the lower-level board is as follows:

the VP and VN sizes can be compared according to the above formula.

In the third stage, when VP > VN, the upper plate of the first capacitor CP12 in the forward capacitor array is connected to GND, the switching state of the lower plate capacitor remains unchanged, the forward capacitor array will perform capacitor allocation, and the voltage of the lower plate of the forward capacitor array changes:

the voltage of the lower plate of the negative capacitor array is not changed, and V can be obtained_P-V_NAndthe magnitude relationship of (1); when in useWhen the comparator outputs 1, whenThe comparator outputs 0.

A fourth stage after which V is obtained_P-V_NAndif it is appropriateNext, the upper board of the second capacitor CP11 of the forward capacitor array is connected to GND, and then:

at this time, V can be obtained_P-V_NAndthe magnitude relationship of (1);

if when it is usedNext, the upper board of the second capacitor CN11 of the negative capacitor array is connected to the ground GND, and then:

at this time, V can be obtained_P-V_NAndthe magnitude relationship of (1).

The remaining capacitors of the capacitor array will continue to cycle through the above steps until the output of the comparator is obtained when the upper board of the CP0 or CN0 is compared with the ground GND, and the value conversion of the first 14 bits is completed. During the transition, the upper plates of matching capacitors CP and CN will remain connected to VR at all times.

As shown in fig. 3, in the present embodiment, the structure of the second-stage sub analog-to-digital converter is as follows:

a forward capacitive array comprising 8 capacitances CP7-CP 0; the capacitor array structure is a traditional structure, the lower-stage plate of the capacitor array is connected with a differential input voltage VP, and the upper-stage plate of the capacitor array is connected with one end of the forward control switch group SP7-SP 0; the other end of the control switch group SP7-SP0 is selectively connected with a reference voltage or a ground wire through the control of the SAR logic circuit.

A negative capacitance array comprising 8 capacitances CN7-CN 0; the capacitor array structure is a traditional structure, a lower-level plate of the capacitor array is connected with a differential input voltage VN, and an upper-level plate of the capacitor array is connected with one end of the forward control switch group SN7-SN 0; the other end of the control switch bank SN7-SN0 will be selectively connected to a reference voltage or ground, controlled by SAR logic.

The second-stage sub analog-to-digital converter is also connected with a dynamic comparator, and the dynamic comparator is used for comparing voltage values of lower-stage plates of capacitors controlled by the SAR logic circuit, so that an output value is generated and then enters the SAR logic circuit. The circuit working process of the second-stage sub analog-digital converter is similar to that of the first-stage sub analog-digital converter, and comprises sampling, holding and bit-by-bit comparison to output digital codes.

Before entering the second-stage sub analog-digital converter, the difference output margin signal of the first-stage sub analog-digital converter needs to be restored in proportion through a margin amplifier, and then the restored signal is sent to a capacitor array for comparison. And finally, combining the two stages of sub analog-to-digital converters to obtain a 22-bit digital code to represent the value of the input level. Then the parallel data is converted into serial data to be output through an interface circuit.