阅读说明：本技术 多位并行逐次逼近(sa)闪速模数转换器(adc)电路 (Multi-bit parallel Successive Approximation (SA) flash analog-to-digital converter (ADC) circuit ) 是由 B·L·普赖斯 于 2019-07-12 设计创作，主要内容包括：公开了多位并行逐次逼近(SA)闪速模数转换器(ADC)电路。在一个方面,多位并行SA闪速ADC电路包括数模转换器(DAC)电路,其接收参考电压和试验位代码并生成DAC模拟信号。SA闪速ADC电路包括并行比较器级,其各自包括等于二(2)的对应并行比较器级的数字位数目次幂的量减去一(1)的一个或多个比较器电路。每个比较器电路接收模拟输入信号和对应的DAC模拟信号,并且生成数字信号。如果模拟输入信号具有与对应的DAC模拟信号相比更大的电压,则每个比较器电路的数字信号为逻辑高,并且如果模拟输入信号具有更小的电压,则每个比较器电路的数字信号为逻辑低。与每个并行比较器级相对应的数字信号被用于生成数字输出信号。(Multi-bit parallel Successive Approximation (SA) flash analog-to-digital converter (ADC) circuits are disclosed. In one aspect, a multi-bit parallel SA flash ADC circuit includes a digital-to-analog converter (DAC) circuit that receives a reference voltage and a test bit code and generates a DAC analog signal. The SA flash ADC circuit includes parallel comparator stages each including one or more comparator circuits equal to two (2) to the power of the number of digital bits of the corresponding parallel comparator stage minus one (1). Each comparator circuit receives an analog input signal and a corresponding DAC analog signal and generates a digital signal. The digital signal of each comparator circuit is logic high if the analog input signal has a larger voltage than the corresponding DAC analog signal, and logic low if the analog input signal has a smaller voltage. The digital signal corresponding to each parallel comparator stage is used to generate a digital output signal.)

1. A multi-bit parallel Successive Approximation (SA) flash analog-to-digital converter (ADC) circuit, comprising:

a digital-to-analog converter (DAC) circuit configured to:

receiving a reference voltage; and

generating a plurality of DAC analog signals, wherein each DAC analog signal is based on the reference voltage;

a system comparison circuit comprising a plurality of parallel comparator stages, wherein each parallel comparator stage of the plurality of parallel comparator stages comprises:

one or more comparator circuits, wherein:

the number of the one or more comparator circuits of each parallel comparator stage is equal to two (2) less one (1) to the power of the number of digital bits of the corresponding parallel comparator stage; and is

Each comparator circuit of the one or more comparator circuits is configured to:

receiving an analog input signal;

receiving a corresponding DAC analog signal; and

generating a digital signal, wherein:

the digital signal has a logic high value if the analog input signal has a greater voltage than the corresponding DAC analog signal; and is

The digital signal has a logic low value if the analog input signal has a smaller voltage than the corresponding DAC analog signal; and is

The system comparison circuit is configured to generate one or more digital bits corresponding to each parallel comparator stage based on each corresponding digital signal, wherein the one or more digital bits collectively generate a digital output signal that is a digital representation of the analog input signal.

2. The multi-bit parallel SA flash ADC circuit of claim 1, wherein the DAC circuit comprises a plurality of DAC arrays, each DAC array of the plurality of DAC arrays corresponding to a parallel comparator stage of the plurality of parallel comparator stages and comprising a number of single-output DAC circuits, wherein:

the number of single output DAC circuits of each DAC array is equal to the number of the one or more comparator circuits of the corresponding parallel comparator stage;

each single output DAC circuit of the DAC array corresponding to a most significant bit of the digital output signal is configured to:

receiving a corresponding trial bit code comprising a sequence of digital bits having values defined for one or more digital bits corresponding to the digital output signal; and

generating the corresponding DAC analog signals, wherein each corresponding DAC analog signal is based on the reference voltage and the corresponding trial bit code; and is

Each single output DAC circuit of the plurality of DAC arrays other than the DAC array corresponding to the most significant bit is configured to:

receiving a corresponding trial bit code and one or more digital bits for each parallel comparator stage; and

generating the plurality of DAC analog signals, wherein each DAC analog signal is based on the reference voltage, the corresponding trial bit code, and the corresponding one or more digital bits.

3. The multi-bit parallel SA flash ADC circuit of claim 2, wherein the system comparison circuit further comprises a thermometer-to-binary (TTB) circuit configured to:

receiving the digital signal from the one or more comparator circuits of each of the plurality of parallel comparator stages; and

generating the one or more digital bits corresponding to each parallel comparator stage, wherein the one or more digital bits collectively generate the digital output signal that is the digital representation of the analog input signal.

4. The multi-bit parallel SA flash ADC circuit of claim 1, wherein the DAC circuit comprises a multi-output DAC circuit comprising a plurality of DAC stages, wherein:

each DAC stage of the plurality of DAC stages corresponds to a parallel comparator stage of the plurality of parallel comparator stages; and is

Each DAC stage of the plurality of DAC stages is configured to:

receiving a corresponding top voltage and a corresponding bottom voltage, wherein a voltage range of the corresponding top voltage and the corresponding bottom voltage is based on the reference voltage; and

generating a number of DAC analog signals based on the corresponding top voltage and the corresponding bottom voltage, wherein the number of DAC analog signals is equal to the number of the one or more comparator circuits in each corresponding parallel comparator stage.

5. The multi-bit parallel SA flash ADC circuit of claim 4, wherein the system comparison circuit further comprises a thermometer-to-binary (TTB) circuit configured to:

receiving the digital signal from the one or more comparator circuits of each of the plurality of parallel comparator stages; and

generating the one or more digital bits corresponding to each parallel comparator stage, wherein the one or more digital bits collectively generate the digital output signal that is the digital representation of the analog input signal.

6. The multi-bit parallel SA flash ADC circuit of claim 4, wherein the number of DAC analog signals generated by each of the plurality of DAC stages has a value that is a division of the voltage range.

7. The multi-bit parallel SA flash ADC circuit of claim 4, wherein each of the plurality of DAC stages comprises a resistor rotation circuit configured to generate a corresponding number of DAC analog signals by generating a division of the voltage range.

8. The multi-bit parallel SA flash ADC circuit of claim 7, wherein the resistor rotation circuit of each DAC stage comprises:

a top voltage input node configured to receive the corresponding top voltage;

a bottom voltage input node configured to receive the corresponding bottom voltage;

a decoder circuit configured to:

receiving the one or more digital bits of the corresponding parallel comparator stage; and

generating a number of decoded signals based on the one or more digital bits, wherein the number of decoded signals is equal to two (2) to the power of the number of the one or more digital bits;

a plurality of inverters, wherein each inverter is configured to:

receiving a corresponding decoded signal; and

generating a corresponding inverse decoded signal;

a plurality of switches, wherein:

a number of switches configured to receive the corresponding inverse decoded signals; and is

A number of switches configured to receive the corresponding decoded signals; and

a plurality of resistors alternately connected in series with the number of switches configured to receive the corresponding inverse decoded signal, wherein the plurality of resistors are arranged such that the plurality of resistors divide the voltage range into the number of DAC analog signals and the top and bottom voltages provided to a next DAC stage.

9. The multi-bit parallel SA flash ADC circuit of claim 1, comprising four (4) parallel comparator stages, wherein each parallel comparator stage comprises three (3) comparator circuits, such that the multi-bit parallel SA flash ADC circuit is configured to generate a twelve (12) bit digital output signal.

10. The multi-bit parallel SA flash ADC circuit of claim 1, comprising two (2) parallel comparator stages, wherein each parallel comparator stage comprises three (3) comparator circuits, such that the multi-bit parallel SA flash ADC circuit is configured to generate a six (6) bit digital output signal.

11. The multi-bit parallel SA flash ADC circuit of claim 1 integrated into an Integrated Circuit (IC).

12. The multi-bit parallel SA flash ADC circuit of claim 1, integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a Global Positioning System (GPS) device; a mobile phone; a cellular telephone; a smart phone; session Initiation Protocol (SIP) phones; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; personal Digital Assistants (PDAs); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; digital Video Disc (DVD) players; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multi-axis helicopter.

13. A multi-bit parallel Successive Approximation (SA) flash analog-to-digital converter (ADC) circuit, comprising:

means for converting a digital value to an analog value configured to:

receiving a reference voltage;

generating a plurality of analog-to-digital converter (DAC) analog signals, wherein each DAC analog signal is based on the reference voltage;

apparatus for generating digital bits comprising a plurality of means for comparing values in parallel, wherein each means for comparing values in parallel comprises:

a number of means for comparing, wherein:

the number of means for comparing in each means for comparing values in parallel is equal to two (2) less one (1) to the amount to the power of the number of digits of the corresponding means for comparing values in parallel; and is

Each means for comparing is configured to:

receiving an analog input signal;

receiving a corresponding DAC analog signal; and

generating a digital signal; wherein

The digital signal has a logic high value if the analog input signal has a greater voltage than the corresponding DAC analog signal; and is

The digital signal has a logic low value if the analog input signal has a smaller voltage than the corresponding DAC analog signal;

the means for generating digital bits is configured to generate one or more digital bits corresponding to each means for comparing values in parallel, wherein the one or more digital bits collectively generate a digital output signal that is a digital representation of the analog input signal.

14. The multi-bit parallel SA flash ADC circuit of claim 13, wherein the means for converting the digital value to the analog value comprises a plurality of DAC arrays, each DAC array of the plurality of DAC arrays corresponding to the means for comparing values in parallel and comprising a number of single output means for converting digital values to analog values, wherein:

the number of single output means of each DAC array for converting the digital value to the analog value is equal to the number of means for comparing in the corresponding means for comparing values in parallel;

each single output device of the DAC array corresponding to a most significant bit of the digital output signal for converting the digital value to the analog value is configured to:

receiving a trial bit code comprising a sequence of digital bits having values defined for the one or more digital bits corresponding to the digital output signal; and

generating a corresponding plurality of DAC analog signals, wherein each corresponding DAC analog signal is based on the reference voltage and the corresponding trial bit code; and is

Each single output device of the plurality of DAC arrays other than the DAC array corresponding to the most significant bit for converting the digital value to the analog value is configured to:

receiving a corresponding trial bit code and one or more of the one or more digital bits generated by the means for comparing values in parallel; and

generating the plurality of DAC analog signals, wherein each DAC analog signal is based on the reference voltage, the corresponding trial bit code, and the corresponding one or more digital bits.

15. The multi-bit parallel SA flash ADC circuit of claim 13, wherein the means for generating digital bits further comprises means for binary conversion configured to:

receiving a digital signal from one or more comparator circuits of each of a plurality of parallel comparator stages; and

generating one or more digital bits corresponding to each parallel comparator stage, wherein the one or more digital bits collectively generate the digital output signal that is the digital representation of the analog input signal.

16. The multi-bit parallel SA flash ADC circuit of claim 13, wherein the means for converting the digital values to the analog values comprises a multi-output device for converting digital values to analog values, the multi-output device comprising a plurality of DAC stages, wherein:

each DAC stage of the plurality of DAC stages corresponds to the means for comparing values in parallel; and is

Each DAC stage of the plurality of DAC stages is configured to:

receiving a corresponding top voltage and a corresponding bottom voltage, wherein a voltage range of the corresponding top voltage and the corresponding bottom voltage is based on the reference voltage; and

generating a number of DAC analog signals based on the corresponding top voltages and the corresponding bottom voltages, wherein the number of DAC analog signals is equal to the number of means for comparing in the corresponding means for comparing values in parallel.

17. The multi-bit parallel SA flash ADC circuit of claim 16, wherein the comparison circuit further comprises a thermometer-to-binary (TTB) circuit configured to:

receiving the digital signal from the one or more comparator circuits of each of the plurality of parallel comparator stages; and

generating the one or more digital bits corresponding to each parallel comparator stage, wherein the one or more digital bits collectively generate the digital output signal that is the digital representation of the analog input signal.

18. The multi-bit parallel SA flash ADC circuit of claim 16, wherein the number of DAC analog signals generated by each of the plurality of DAC stages has a value that is a division of the voltage range.

19. The multi-bit parallel SA flash ADC circuit of claim 16, wherein each DAC stage of the plurality of DAC stages comprises a means for dividing a voltage, the means for dividing a voltage configured to generate a corresponding number of DAC analog signals by generating a division of the voltage range.

20. A method for converting an analog input signal to a digital output signal, wherein a plurality of digital bits of the digital output signal are determined in parallel, the method comprising:

receiving a reference voltage;

generating a plurality of digital-to-analog converter (DAC) analog signals, wherein each DAC analog signal is based on the reference voltage;

receiving the analog input signal;

generating one or more digital signals in a plurality of parallel comparator stages, wherein:

each digital signal is generated by comparing the analog input signal with a corresponding DAC analog signal;

each digital signal has a logic high value if the analog input signal has a greater voltage than the corresponding DAC analog signal; and is

Each digital signal has a logic low value if the analog input signal has a smaller voltage than the corresponding DAC analog signal; and

generating one or more digital bits corresponding to each parallel comparator stage based on the one or more digital signals of the corresponding parallel comparator stage, wherein the one or more digital bits collectively generate a digital output signal that is a digital representation of the analog input signal.

21. The method of claim 20, wherein the DAC circuit comprises a plurality of DAC arrays, the method further comprising:

receiving a trial bit code comprising a sequence of digital bits having values defined for the one or more digital bits corresponding to the digital output signal; and

generating a number of DAC analog signals corresponding to a most significant bit of the digital output signal, wherein each corresponding DAC analog signal is based on the reference voltage and a corresponding trial bit code; and

generating remaining DAC analog signals that do not correspond to the most significant bits of the digital output signal, wherein each remaining DAC analog signal is based on the reference voltage, a corresponding trial bit code, and a corresponding one or more digital bits.

22. The method of claim 20, further comprising:

receiving a corresponding top voltage and a corresponding bottom voltage, wherein a voltage range of the corresponding top voltage and the corresponding bottom voltage is based on the reference voltage; and

generating a number of DAC analog signals based on the corresponding top voltage and the corresponding bottom voltage, wherein the number of DAC analog signals is equal to the number of digital signals.

23. The method of claim 22, wherein the number of DAC analog signals have values that are divisions of the voltage range.

Technical Field

The technology of the present disclosure relates generally to analog-to-digital converter (ADC) circuits, and in particular to Successive Approximation (SA) Flash (Flash) ADC circuits.

Background

Processor-based systems employ analog-to-digital conversion of signals in conjunction with performing various functions. One method of implementing such analog-to-digital conversion is to use flash analog-to-digital converter (ADC) circuitry. Operation of the flash ADC circuit involves paralleling a plurality of comparators to compare an input voltage signal with a series of analog signals generated in parallel from a reference voltage during a conversion process. In particular, each comparator in the flash ADC circuit operates asynchronously such that each comparison is performed without a reference clock signal. The flash ADC circuit uses each comparison of the input voltage signal and the analog signal to generate a final value of the digital output signal.

For example, a conventional flash ADC circuit employs 2^N-1 comparator circuit, where N is the number of bits in the digital output signal. Additionally, the reference voltage is divided into 2^N-1 generated analog signal, the analog signal being distributed across a range of reference voltages. Each analog signal is provided to a correspondingOne input of the comparator circuit and the input analog signal is provided to the other input of each comparator circuit. In this manner, for each comparator circuit, if the generated analog signal has a voltage greater than the voltage of the input analog signal, the output of the corresponding comparator circuit has a logic low "0" value. Conversely, if the generated analog signal has a voltage that is less than the voltage of the input analog signal, the output of the corresponding comparator circuit has a logic high "1" value. The output signal of each comparator circuit is used to create a digital output signal that is a digital representation of the input voltage signal.

In this regard, conventional flash ADC circuits have relatively fast conversion times. However, since the conventional flash ADC circuit is designed to generate a digital output signal having a larger number of bits (i.e., a higher number of bits N), the number of circuit elements employed in the conventional flash ADC circuit increases geometrically, resulting in more chip area being used and power being consumed. Therefore, it may be advantageous to trade off the switching time for chip area and power reduction.

Disclosure of Invention

Aspects disclosed in the detailed description include a multi-bit parallel Successive Approximation (SA) flash analog-to-digital converter (ADC) circuit. In one aspect, a multi-bit parallel SA flash ADC circuit is configured to generate a digital output signal having a number of digital bits, where the digital output signal is a digital representation of an analog input signal. To perform such conversion, the multi-bit parallel SA flash ADC circuit includes a multi-output digital-to-analog converter (DAC) circuit that receives a reference voltage and generates a plurality of DAC analog signals using the reference voltage and digital bits generated by the parallel comparator stages of the system comparison circuit. Each of the parallel comparator stages includes a number of comparator circuits equal to two (2) less one (1) to the power of the number of digital output bits of the corresponding parallel comparator stage. Each comparator circuit receives an analog input signal and a corresponding DAC analog signal and generates a digital signal based on comparing the analog input signal and the DAC analog signal. In particular, the digital signal of each comparator will have a logic high value if the analog input signal has a larger voltage than the corresponding DAC analog signal, and the digital signal of each comparator will have a logic low value if the analog input signal has a smaller voltage than the corresponding DAC analog signal. The system comparison circuit uses the digital signal from the comparator circuit of each parallel comparator stage to generate a digital bit corresponding to each parallel comparator stage, where one or more digital bits collectively generate a digital output signal. In the examples disclosed herein, the multi-bit parallel SA flash ADC circuit has similar conversion times to conventional flash ADC circuits for the same number of digital bits.

In this regard, in one exemplary aspect, a multi-bit parallel SA flash ADC circuit is provided. The multi-bit parallel SA flash ADC circuit includes a DAC circuit configured to receive a reference voltage and generate a plurality of DAC analog signals, wherein each DAC analog signal is based on the reference voltage. The multi-bit parallel SA flash ADC circuit also includes a system compare circuit including a plurality of parallel comparator stages. Each parallel comparator stage of the plurality of parallel comparator stages comprises one or more comparator circuits, wherein the number of the one or more comparator circuits of each parallel comparator stage is equal to two (2) less one (1) to the power of the number of digital bits of the corresponding parallel comparator stage. Each of the one or more comparator circuits is configured to receive an analog input signal, receive a corresponding DAC analog signal, and generate a digital signal. The digital signal has a logic high value if the analog input signal has a greater voltage than the corresponding DAC analog signal, and a logic low value if the analog input signal has a lower voltage than the corresponding DAC analog signal. The system comparison circuit is configured to generate one or more digital bits corresponding to each parallel comparator stage based on each corresponding digital signal, wherein the one or more digital bits collectively generate a digital output signal that is a digital representation of the analog input signal.

In another exemplary aspect, a multi-bit parallel SA flash ADC circuit is provided. The multi-bit parallel SA flash ADC circuit includes means for converting a digital value to an analog value configured to receive a reference voltage and generate a plurality of DAC analog signals, wherein each DAC analog signal is based on the reference voltage. The multi-bit parallel SA flash ADC circuit further comprises means for generating digital bits comprising a plurality of means for comparing values in parallel. Each means for comparing values in parallel comprises a number of means for comparing, wherein the number of means for comparing in each means for comparing values in parallel is equal to two (2) less one (1) to the amount to the power of the number of digital bits of the corresponding means for comparing values in parallel. Each means for comparing is configured to receive an analog input signal, receive a corresponding DAC analog signal, and generate a digital signal. The digital signal has a logic high value if the analog input signal has a larger voltage than the corresponding DAC analog signal, and a logic low value if the analog input signal has a smaller voltage than the corresponding DAC analog signal. The means for generating digital bits is configured to generate one or more digital bits corresponding to each means for comparing values in parallel, wherein the one or more digital bits collectively generate a digital output signal that is a digital representation of the analog input signal.

In another exemplary aspect, a method for converting an analog input signal to a digital output signal is provided, wherein a plurality of digital bits of the digital output signal are determined in parallel. The method includes receiving a reference voltage and generating a plurality of DAC analog signals, wherein each DAC analog signal is based on the reference voltage. The method also includes receiving an analog input signal and generating one or more digital signals in a plurality of parallel comparator stages. Each digital signal is generated by comparing the analog input signal with a corresponding DAC analog signal, wherein each digital signal has a logic high value if the analog input signal has a greater voltage than the corresponding DAC analog signal, and a logic low value if the analog input signal has a lesser voltage than the corresponding DAC analog signal. The method also includes generating one or more digital bits corresponding to each parallel comparator stage based on one or more digital signals of the corresponding parallel comparator stage, wherein the one or more digital bits collectively generate a digital output signal that is a digital representation of the analog input signal.

Drawings

FIG. 1 is a circuit diagram of an exemplary multi-bit parallel Successive Approximation (SA) flash analog-to-digital converter (ADC) circuit configured to convert an analog input signal to a digital output signal, wherein multiple bits of the digital output signal are generated in parallel;

FIG. 2 is a circuit diagram of an exemplary two (2) bit parallel four (4) bit SA flash ADC circuit configured to convert an analog input signal to a four (4) bit digital output signal, employing a single output digital-to-analog converter (DAC) circuit corresponding to each comparator circuit;

FIG. 3 is a flow diagram illustrating an exemplary process that may be performed by the multi-bit parallel SA flash ADC circuit of FIG. 1 to convert an analog input signal to a digital output signal;

FIG. 4 is a circuit diagram of an exemplary multi-bit parallel SA flash ADC circuit employing a multi-output DAC circuit instead of a single-output DAC circuit for each corresponding comparator circuit;

FIG. 5 is a circuit diagram of an exemplary resistor rotation circuit that may be employed for each DAC stage of the multi-output DAC circuit of FIG. 4;

FIG. 6 is a circuit diagram of another exemplary multi-bit parallel SA flash ADC circuit that employs another multi-output DAC circuit instead of a single-output DAC circuit for each corresponding comparator circuit;

FIG. 7 is a block diagram of an exemplary processor-based system that may include the multi-bit parallel SA flash ADC circuits of FIGS. 1, 2, 4, and 6; and

fig. 8 is a block diagram of an exemplary wireless communication device including Radio Frequency (RF) components formed in an Integrated Circuit (IC), where the RF components may include elements employing the multi-bit parallel SA flash ADC circuits of fig. 1, 2, 4, and 6.

Detailed Description

Referring now to the drawings, several exemplary aspects of the disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

Aspects disclosed in the detailed description include a multi-bit parallel Successive Approximation (SA) flash analog-to-digital converter (ADC) circuit. In one aspect, a multi-bit parallel SA flash ADC circuit is configured to generate a digital output signal having a number of digital bits, where the digital output signal is a digital representation of an analog input signal. To perform such conversion, the multi-bit parallel SA flash ADC circuit includes a multi-output digital-to-analog converter (DAC) circuit that receives a reference voltage and generates a plurality of DAC analog signals using the reference voltage and digital bits generated by the parallel comparator stages of the system comparison circuit. Each of the parallel comparator stages includes one or more comparator circuits, the number of the one or more comparator circuits being equal to two (2) less one (1) to the power of the number of digital output bits of the corresponding parallel comparator stage. Each comparator circuit receives an analog input signal and a corresponding DAC analog signal and generates a digital signal based on comparing the analog input signal and the DAC analog signal. In particular, the digital signal of each comparator will have a logic high value if the voltage of the analog input signal is greater than the voltage of the corresponding DAC analog signal, and the digital signal of each comparator will have a logic low value if the voltage of the analog input signal is less than the voltage of the corresponding DAC analog signal. The system comparison circuit uses the digital signals from the one or more comparator circuits of each parallel comparator stage to generate digital bits corresponding to each parallel comparator stage, wherein the one or more digital bits collectively generate a digital output signal. In the examples disclosed herein, the multi-bit parallel SA flash ADC circuit has similar conversion times to conventional flash ADC circuits for the same number of digital bits.

In this regard, fig. 1 is a circuit diagram of an exemplary multi-bit parallel SA flash ADC circuit 100 configured to convert an analog input signal VIN to a digital output signal DOUT having digital bits DG (a) -DG (1), wherein several digital bits DG (a) -DG (1) are generated in parallel. In aspects described herein, digital bits DG (a) (e.g., the most numbered digital bits DG) are the Most Significant Bits (MSB) of digital output signal DOUT, and digital bits DG (1) (e.g., the least numbered digital bits DG) are the Least Significant Bits (LSB) of digital output signal DOUT. To perform the conversion, the multi-bit parallel SA flash ADC circuit 100 employs a DAC circuit 102 configured to receive a reference voltage VREF, and in this regard, uses a plurality of trial bit codes 104(1) (C) from (1) to (B) (C). As discussed in more detail below, each trial bit code 104(1), (1) -104(B) (C) includes a unique sequence of digital bits having values defined for one or more digital bits and allows for the successive approximation property of the multi-bit parallel SA flash ADC circuit 100. DAC circuit 102 is configured to generate DAC analog signals 106(1) and (1) -106(B) (C) based on reference voltage VREF, trial bit codes 104(1) -104(B) (C), and a subset of digital bits DG (1) -DG (a) generated by parallel comparator stages 108(1) -108(B) of system comparison circuit 109. DAC analog signals 106(1) -106(B) (C) are provided to each corresponding parallel comparator stage 108(1) -108 (B). In this aspect, DAC circuit 102 employs DAC arrays 110(1) -110(B), each of which corresponds to a parallel comparator stage 108(1) -108(B) and includes a corresponding single-output DAC circuit 112(1) -112(B) (C). However, as described below, DAC circuit 102 in other aspects may employ a multi-output DAC circuit in place of DAC array 110(1) -110 (B). It should also be noted that the DAC arrays 110(1) -110(B) and their corresponding parallel comparator stages 108(1) -108(B) may each generate a different number of respective DAC analog signals 106(1), (1) -106(B) (C) and digital signals.

With continued reference to fig. 1, each of the parallel comparator stages 108(1) -108(B) includes a number C of corresponding comparator circuits 114(1) (C) -114(B) (C), where C is equal to two (2) raised to the power D of the number D of digital bits DG (1) -DG (a) of the corresponding parallel comparator stages 108(1) -108(B) minus one (1) (i.e., C ═ 2^ D) -1). In this example, a ═ B × D, and thus the digital bits DG (a- (B-1) D) -DG (1) have D bits. As used herein, the numbers A, B, C and D are positive integers. For example, if the parallel comparator stage 108(1) corresponds to two (2) digital bits DG (a), DG (a-1) of the digital output signal DOUT, the parallel comparator stage 108(1) comprises three (3) comparator circuits 114(1), (1) - (114), (1), (3) (e.g., (2^2) -1 ═ 3). As discussed in detail below, the number D may be the same in one or more of the parallel comparator stages 108(1) -108(B), such that the number C is the same in one or more of the parallel comparator stages 108(1) -108(B) and the DAC arrays 110(1) -110 (B). Alternatively, the number D may be different in each parallel comparator stage 108(1) -108(B), such that the number C is different in each parallel comparator stage 108(1) -108(B) and DAC array 110(1) -110 (B). Each comparator circuit 114(1) -114(B) (C) receives the analog input signal VIN and the corresponding DAC analog signal 106(1) -106(B) (C) and generates a digital signal 116(1) -116(B) (C) based on comparing the analog input signal VIN with the DAC analog signal 106(1) (106) (1) -106(B) (C). In particular, if the analog input signal VIN has a larger voltage than the corresponding DAC analog signal 106(1), (1) -106(B) (C), each comparator circuit 114(1) -114(B) (C) digital signal 116(1) -116(B) (C) has a logic high "1" value, and if the analog input signal VIN has a smaller voltage than the corresponding DAC analog signal 106(1) -106(B) (C), each comparator circuit 114(1) -114(B) (C) digital signal 116(1) has a logic low "0" value. System comparison circuitry 109 is configured to generate digital bits DG (1) -DG (a) corresponding to each parallel comparator stage 108(1) -108(B), where digital bits DG (1) -DG (a) collectively generate a digital output signal DOUT. In particular, in this aspect, system comparison circuitry 109 includes thermometer to binary converter (TTB) circuitry 118 configured to receive digital signals 116(1) (C) from comparator circuitry 114(1) -114(B) (C) of each parallel comparator stage 108(1) -108 (B). The TTB circuitry 118 is further configured to generate digital bits DG (1) -DG (a) corresponding to each of the parallel comparator stages 108(1) -108(B) to generate a digital output signal DOUT.

With continued reference to FIG. 1, operational details of the multi-bit parallel SA flash ADC circuit 100 are now provided. In particular, for converting the analog input signal VIN into the digital output signal DOUT, the parallel comparator stage 108(1) is configured to calculate D most significant digital bits DG (a) -DG (a-D +1) of the digital output signal DOUT. For calculating the digital bits DG (A) -DG (A-D +1), the trial bit codes 104(1) -104(1) (C) are provided to the DAC array 110(1), wherein the corresponding trial bit codes 104(1) -104(1) (C) each represent a unique sequence of digital bits DG (A) -DG (A-D + 1). Using the trial bit code 104(1), (1) -104(1), (C) and the reference voltage VREF, the DAC array 110(1) generates the corresponding DAC analog signal 106(1), (1) -106(1), (C). In addition, the parallel comparator stage 108(1) compares each of the DAC analog signals 106(1) -106(1) (C) with the analog input signal VIN to generate a corresponding digital signal 116(1) -116(1) (C), which digital signal 116(1) (116) (1) (C) is converted to digital bits DG (a) -DG (a-D +1) by the stage 120(1) of the TTB circuit 118.

With continued reference to FIG. 1, it is important to note that the multi-bit parallel SA flash ADC circuit 100 is asynchronous (i.e., not controlled by a clock signal). Specifically, each DAC array 110(2) -110(B) is configured to receive the output of a stage 120(1) -120(B) generated as a digital bit DG (1) -DG (a) generated in each previous parallel comparator stage 108(1) -108 (B). In this manner, each DAC array 110(2) -110(B) generates a corresponding DAC analog signal 106(2) (1) -106(B) (C) in response to stabilization of the digital bits DG (1) -DG (a) of the previous parallel comparator stage 108(1) -108 (B). To this end, the parallel comparator stage 108(2) is configured to compute the next D most significant digital bits DG (a-D) -DG (a-2D +1) of the digital output signal DOUT. To calculate the digital bits DG (A-D) -DG (A-2D +1), the trial bit codes 104(2) (1) -104(2) (C) are provided to the DAC array 110(2), where the trial bit codes 104(2) (1) -104(2) (C) each represent a unique sequence of digital bits DG (A-D) -DG (A-2D + 1). In addition, digital bits DG (A) -DG (A-D +1) are also provided to DAC array 110 (2). Using the trial bit code 104(2) (1) -104(2) (C), the digital bits DG (a) -DG (a-D +1), and the reference voltage VREF, the DAC array 110(2) generates the corresponding DAC analog signal 106(2) (1) -106(2) (C). In addition, the parallel comparator stage 108(2) compares each of the DAC analog signals 106(2) (1) -106(2) (C) with the analog input signal VIN to generate a corresponding digital signal 116(2) (1) -116(2) (C), which digital signal 116(2) (1) -116(2) (C) is converted to digital bits DG (a-D) -DG (a-2D +1) by the stage 120(2) of the TTB circuit 118. For the remaining digital bits DG (A-2D-1) -DG (1), the above sequence continues using the remaining DAC arrays 110(3) -110(B), parallel comparator stages 108(3) -108(B), and stages 120(3) -120(B) of TTB circuit 118.

With continued reference to fig. 1, as described above, the number D may be the same or vary for each parallel comparator stage 108(1) -108(B), such that the number C may also vary for each parallel comparator stage 108(1) -108(B) and DAC array 110(1) -110 (B). For example, DAC array 110(1), parallel comparator stage 108(1), and stage 120(1) may correspond to the M number of MSBs of digital bits DG (1) -DG (a). Therefore, DAC array 110(1) receives trial bit code 104(1) and (1) 104(1) ((2^ M) -1), includes single output DAC circuit 112(1) and (1) 112(1) ((2^ M) -1) and generates DAC analog signal 106(1) ((2^ M) -1) and (106 (1) ((1). In addition, the parallel comparator stage 108(1) includes (2^ M) -1 comparator circuits 114(1) -114(1) ((2^ M) -1), and generates digital signals 116(1) -116(1) ((2^ M) -1). Stage 120(1) then generates the M number MSBs of digital bits DG (1) -DG (a). DAC array 110(2), parallel comparator stage 108(2), and stage 120(2) correspond to N number of digital bits within DG (1) -DG (a), while DAC array 110(3), parallel comparator stage 108(3), and stage 120(3) correspond to P number of digital bits within DG (1) -DG (a). Further, DAC array 110(B-1), parallel comparator stage 108(B-1), and stage 120(B-1) correspond to the number of Q digital bits within DG (1) -DG (A), while DAC array 110(B), parallel comparator stage 108(B), and stage 120(B) correspond to the number of R digital bits within DG (1) -DG (A). Configuring the multi-bit parallel SA flash ADC circuit 100 to implement different numbers M, N, P, Q and R provides the designer with the ability to self-define the level of parallelism at a particular granularity based on the needs of a particular application.

Certain aspects of the multi-bit parallel SA flash ADC circuit 100 of fig. 1 are now described to provide additional explanation. To this end, fig. 2 is a circuit diagram of an exemplary two (2) bit parallel four (4) bit SA flash ADC circuit 200 configured to convert an analog input signal VIN to a four (4) bit (i.e., digital bits DG (4) -DG (1)) digital output signal DOUT, employing a single output DAC circuit 112(1), (1) -112(2), (3) corresponding to each comparator circuit 114(1), (1) -114(2), (3). The two (2) bit parallel four (4) bit SA flash ADC circuit 200 includes common elements with the multi-bit parallel SA flash ADC circuit 100 of fig. 1, which are referred to with common element numbers in fig. 1 and 2 and therefore will not be described in detail herein.

With continued reference to fig. 2, to convert the analog input signal VIN to the digital output signal DOUT, the parallel comparator stage 108(1) is configured to compute the two (2) most significant digital bits DG (4) -DG (3) of the digital output signal DOUT. To calculate digital bits DG (4) -DG (3), three (3) trial bit codes 104(1) -104(1) (3) are provided to DAC array 110 (1). In particular, input ports 202(4) -202(3) of single-output DAC circuit 112(1) receive trial bit code 104(1) including bit sequence "11". In addition, input ports 202(4), 202(3) of single output DAC circuit 112(1), (2) receive trial bit code 104(1), (2), trial bit code 104(1), (2) includes a sequence of bits "10" corresponding to digital bits DG (4), DG (3), and input ports 202(4), 202(3) of single output DAC circuit 112(1), (3) receive trial bit code 104(1), (3), trial bit code 104(1), (3) includes a sequence of bits "01" corresponding to digital bits DG (4), DG (3). In addition, the input port 202(2), 202(1) of each of the single-output DAC circuits 112(1), (1) -112(1), (3) is electrically coupled to ground, which provides a logic low "0" value to each corresponding input port 202(2), 202 (1). Each DAC circuit 112(1), (1) -112(1), (3) further includes a voltage input node 204 configured to receive a reference voltage VREF. Using the trial bit code 104(1), (1) -104(1), (3) and the reference voltage VREF, the DAC array 110(1) generates the corresponding DAC analog signal 106(1), (1) -106(1), (3). In particular, the DAC circuit 102 is configured to generate DAC analog signals 106(1) to 106(1) to (3) having corresponding values that are a division of the voltage range between the reference voltage VREF and the ground signal. For example, if the reference voltage VREF is 1.0V, the DAC analog signal 106(1) -106(1) (3) is equal to 0.75V, 0.50V, and 0.25V, respectively.

With continued reference to fig. 2, each of the DAC analog signals 106(1), (1) - (106), (1), (3) is provided to each corresponding comparator circuit 114(1), (1) - (114), (1), (3). In this manner, the parallel comparator stage 108(1) compares each of the DAC analog signals 106(1) -106(1) (3) with the analog input signal VIN to generate corresponding digital signals 116(1) -116(1) (3). More specifically, the comparator circuit 114(1) generates the digital signal 116 by comparing the DAC analog signal 106(1) with the analog input signal VIN (1), and the comparator circuit 114(1) (2) generates the digital signal 116 by comparing the DAC analog signal 106(1) (2) with the analog input signal VIN (1) (2). In addition, the comparator circuit 114(1) (3) generates the digital signal 116 by comparing the DAC analog signal 106(1) (3) with the analog input signal VIN (1) (3). For example, if VREF is 1.0V and if the analog input signal VIN is equal to 0.57V, and DAC analog signal 106(1) 106(1) (3) is equal to 0.75V, 0.5V, and 0.25V, respectively, then digital signal 116(1) has a logic 0 value, digital signal 116(1) (2) has a logic 1 value, and digital signal 116(1) (3) has a logic 1 value. Digital signals 116(1) -116(1) (3) are converted to digital bits DG (4), DG (3) by stage 120(1) of TTB circuit 118. For example, the digital bits DG (4), DG (3) may have a value of "10". In this example, it may be all of DAC analog signals 106(1), (106), (1), (3) are "000", "001", "011" or "111" because digital signals 116(1), (1) and (3) generated by comparator circuits 114(1), (1) and (114) and (3) generate thermometer codes based on which threshold in DAC analog signals 106(1), (1) and (106), (1) and (3) the input VIN is greater. To this end, TTB circuit 118 and stage 120(1) generate digital bits DG (4), DG (3) "00" for comparator output "000" of digital signal 116(1), (1) -116(1), (3); it generates digital bits DG (4), "01" of DG (3) for comparator output "001" of digital signal 116(1), (1) -116(1), (3); it generates "10" of digital bits DG (4), DG (3) for comparator output "011" of digital signals 116(1) -116(1) (3); and it generates "11" of the digital bits DG (4), DG (3) for the comparator output "111" of digital signal 116(1), (1) -116(1), (3).

For example, with continued reference to fig. 2, in this aspect, to generate the digital bits DG (4), DG (3), stage 120 of TTB circuit 118 (1) employs inverters 206(1), 206(1) (2), AND-based gates 208(1), 208(1) (2) (e.g., AND gates 208(1), 208(1), AND (2)) AND OR-based gates 210(1), 210(1) (2) (e.g., OR gates 210(1), 210(1), (2)). Digital signal 116(1) (e.g., 0 value) is provided to inverter 206(1) (1), such that inverter 206(1) (1) generates inverted digital signal 116 '(1) (1) (e.g., 1 value), AND inverted digital signal 116' (1) (1) is provided to AND gate 208(1), 208(1) (2). In addition, the digital signal 116(1), (2) (e.g., 1 value) is provided to the AND gate 208(1), (1). In this example, the AND gate 208(1) generates the intermediate digital signal 212(1), the intermediate digital signal 212(1) has a logic high "1" value in this example. Intermediate digital signal 212(1) (e.g., 1 value) is provided to inverter 206(1) (2), wherein inverter 206(1) (2) generates inverted intermediate digital signal 212 '(1) (1) (e.g., 0 value), AND inverted intermediate digital signal 212' (1) (1) is provided to AND gate 208(1) (2). Inverted digital signal 116' (1) (1) is also provided to AND gate 208(1) (2), where AND gate 208(1) (2) generates intermediate digital signal 212(1) (2), AND in this example, if digital signals 116(1) (1), 116(1) (2) each have a logic low "0" value, AND digital signals 116(1) (3) have a logic high "1" value, intermediate digital signal 212(1) AND (2) have a logic high "1" value, AND otherwise have a logic low "0" value. Digital signal 116(1) (e.g., 0 value) and intermediate digital signal 212(1) (e.g., 1 value) are provided to OR gate 210(1) (e.g., 1 value), where OR gate 210(1) generates digital bits DG (4) (e.g., 1 value) of digital output signal DG (4). In addition, digital signals 116(1) (e.g., 0 values) and intermediate digital signals 212(1) (2) (e.g., 0 values) are provided to OR gates 210(1) (2), where OR gates 210(1) (2) generate digital bits DG (3) (e.g., 0 values) of digital output signal DG (3).

With continued reference to fig. 2, the parallel comparator stage 108(2) is configured to compute the two (2) least significant digital bits DG (2), DG (1) of the digital output signal DOUT in response to the digital bits DG (4), DG (3) settling to a stable value. To calculate the digital bits DG (2), DG (1), three (3) trial bit codes 104(2) (1) -104(2) (3) are provided to DAC array 110(2), where each single output DAC circuit 112(2) (1) -112(2) (3) includes input ports 202(1) -202 (4). Each DAC 112(2), (1) -112(2), (3) further includes a voltage input node 204 configured to receive a reference voltage VREF. Each single-output DAC circuit 112(2) (1) -112(2) has an input port 202(4), 202(3) configured to receive the generated digital bits DG (4), DG (3). However, input ports 202(2), 202(1) of single-output DAC circuit 112(2), (1) receive trial bit code 104(2), (1), and trial bit code 104(2) (1) includes bit sequences "11" corresponding to DAC inputs DG (2), DG (1). In addition, input ports 202(2), 202(1) of single output DAC circuit 112(2) receive trial bit code 104(2), trial bit code 104(2) includes a sequence of bits "10" corresponding to DAC inputs DG (2), DG (1), and input ports 202(2), 202(1) of single output DAC circuit 112(2) (3) receive trial bit code 104(2) (3), trial bit code 104(2) (3) includes a sequence of bits "01" corresponding to digital bits DG (2), DG (1). DAC array 110(2) uses trial bit code 104(2) (1) -104(2) (3), reference voltage VREF, and digital bits DG (1) -DG (4) from the previous parallel stage(s) to generate corresponding DAC analog signals 106(2) (1) -106(2) (3). For example, the DAC analog signals 106(2) (1) -106(2) (3) in this example are equal to 0.6875V, 0.625V, and 0.5625V, respectively.

With continued reference to fig. 2, each of the DAC analog signals 106(2) (1) -106(2) (3) is provided to each corresponding comparator circuit 114(2) (1) -114(2) (3). In this manner, the parallel comparator stage 108(2) compares each of the DAC analog signals 106(2) (1) - (106) (2) (3) with the analog input signal VIN to generate corresponding digital signals 116(2) (1) - (116) (2) (3). More specifically, the comparator circuit 114(2) (1) generates the digital signal 116(2) (e.g., a logic 0 value) by comparing the DAC analog signal 106(2) (1) (e.g., a 0.6875V value) with the analog input signal VIN (0.57V) (2) (1), and the comparator circuit 114(2) generates the digital signal 116(2) (e.g., a logic 0 value) by comparing the DAC analog signal (e.g., a 0.625V value) with the analog input signal VIN. In addition, the comparator circuit 114(2) (3) generates the digital signal 116(2) (e.g., logic 1 value) by comparing the DAC analog signal 106(2) (3) (e.g., 0.5625V value) with the analog input signal VIN (2) (3). Digital signals 116(2) (1) -116(2) (3) are converted into digital bits DG (2), DG (1) by stages 120(2) of TTB circuitry 118.

For example, with continued reference to fig. 2, in this aspect, to generate digital bits DG (2), DG (1), stage 120(2) of TTB circuit 118 employs inverters 206(2) (1), 206(2), AND-based gates 208(2) (1), 208(2) (e.g., AND gates 208(2), (1), 208(2), AND (2)) AND OR-based gates 210(2) (1), 210(2) (e.g., OR gates 210(2) (1), 210 (2)). Digital signal 116(2) (1) (e.g., 0 value) is provided to inverter 206(2) (1), such that inverter 206(2) (1) generates complementary digital signal 116 '(2) (1) (e.g., 1 value), AND complementary digital signal 116' (2) (1) is provided to AND gate 208(2) (1), 208 (2). In addition, the digital signal 116(2) (e.g., 0 value) is provided to the AND gate 208(2) (1). In this manner, the AND gate 208(2) (1) generates the intermediate digital signal 212(2) (1), AND if the digital signal 116(2) (1) has a logic low "0" value AND the digital signal 116(2) has a logic high "1" value, the intermediate digital signal 212(2) (1) has a logic high "1" value. Intermediate digital signal 212(2) (1) (e.g., 0 value) is provided to inverter 206(2), wherein inverter 206(2) generates complementary intermediate digital signal 212 '(2) (1) (e.g., 1 value), AND complementary intermediate digital signal 212' (2) (1) is provided to AND gate 208 (2). Digital signals 116(2), (3) (e.g., 1 value) are also provided to AND gates 208(2), wherein AND gates 208(2), (2) generate intermediate digital signals 212(2), AND if digital signals 116(2) (1), 116(2), (2) each have a logic low "0" value AND digital signals 116(2), (3) have a logic high "1" value, intermediate digital signals 212(2), (2) have a logic high "1" value, otherwise have a logic low "0" value. Digital signals 116(2) (e.g., 0 values) and intermediate digital signals 212(2) (1) (e.g., 0 values) are provided to OR gates 210(2) (1), where OR gates 210(2) (1) generate digital bits DG (2) (e.g., 0 values) of digital output signal DOUT. Additionally, digital signals 116(2) (1) (e.g., a value of 0) and intermediate digital signals 212(2) (e.g., a value of 1) are provided to OR gate 210(2), where OR gate 210(2) generates digital bits DG (1) (e.g., a value of 1) of digital output signal DOUT such that digital output signal DOUT is equal to "1001" in this example.

Fig. 3 illustrates an exemplary process 300 used by the multi-bit parallel SA flash ADC circuit 100 of fig. 1 to convert an analog input signal VIN to a digital output signal DOUT. The process 300 includes receiving a reference voltage VREF (block 302). The process 300 further includes receiving a plurality of trial bit codes 104(1) -104(B) (C), wherein each trial bit code 104(1) -104(B) (C) of the plurality of trial bit codes 104(1) -104(B) (C) includes a sequence of digital bits having values defined for one or more of the digital bits DG (1) -DG (a) (block 304). Additionally, the process 300 includes generating a plurality of DAC analog signals 106(1), (1) -106(B) (C), where each DAC analog signal 106(1), (1) -106(B) (C) is based on the reference voltage VREF and the corresponding test bit code 104(1), (1) -104(B) (C) (block 306). The process 300 also includes receiving an analog input signal VIN (block 308). The process 300 further includes generating one or more digital signals 116(1) -116(B) (C) in the plurality of parallel comparator stages 108(1) -108(B) (block 310). As described above, each digital signal 116(1), (1) -116(B) (C) is generated by comparing the analog input signal VIN with the corresponding DAC analog signal 106(1) -106(B) (C) such that each digital signal 116(1) -116(B) (C) has a logic high "1" value if the analog input signal VIN has a larger voltage than the corresponding DAC analog signal 106(1) -106(B) (C), and each digital signal 116(1) -116(B) (C) has a logic low "0" value if the analog input signal VIN has a larger voltage than the corresponding DAC analog signal 106(1) -106(B) (C). Process 300 also includes generating one or more digital bits DG (1) -DG (a) corresponding to each parallel comparator stage 108(1) -108(B) based on digital signals 116(1) -116(B) (C) of the corresponding parallel comparator stage 108(1) -108(B), where the one or more digital bits DG (1) -DG (a) collectively generate a digital output signal DOUT that is a digital representation of the analog input signal VIN (block 312). As described above, in this example, the TTB circuitry 118 in fig. 1 is configured to receive the digital signals 116(1) -116(B) (C) from the comparator circuitry 114(1) -114(B) (C) of each parallel comparator stage 108(1) -108 (B). The TTB circuitry 118 is further configured to generate digital bits DG (1) -DG (a) corresponding to each of the parallel comparator stages 108(1) -108(B) to generate a digital output signal DOUT.

As described above, the DAC circuit 102 in the multi-bit parallel SA flash ADC circuit 100 of fig. 1 may employ one multi-output DAC circuit instead of the DAC arrays 110(1) -110(B), thereby reducing the overall area consumption. In this regard, fig. 4 illustrates an exemplary multi-bit parallel SA flash ADC circuit 400 that employs a multi-output DAC circuit 402 for DAC circuit 102, rather than a single-output DAC circuit 112(1) (112 (B) (C)) as in each corresponding comparator circuit 114(1) -114(B) (C) in multi-bit parallel SA flash ADC circuit 100 of fig. 1. The multi-bit parallel SA flash ADC circuit 400 is in this aspect a two (2) bit parallel eight (8) bit SA flash ADC circuit 400, where the multi-output DAC circuit 402 employs DAC stages 404(1) -404(4) corresponding to each of the parallel comparator stages 108(1) -108 (4). Other aspects of employing multi-output DAC circuit 402 may include any number of DAC stages 404(1) -404(B), where each DAC stage 404(1) -404(B) corresponds to a parallel comparator stage 108(1) - (108 (B). The multi-bit parallel SA flash ADC circuit 400 includes common elements with the multi-bit parallel SA flash ADC circuit 100 of fig. 1, the common elements being referred to with common element numbers in fig. 1 and 4 and therefore will not be described in detail herein.

With continued reference to fig. 4, each DAC stage 404(1) -404(4) is configured to generate a corresponding DAC voltage VDAC (1) -VDAC (3), wherein each DAC voltage VDAC (1) -VDAC (3) of each DAC stage 404(1) -404(4) is provided to a corresponding comparator circuit 114(1), (1) -114(4) (3) in each corresponding parallel comparator stage 108(1) -108 (4). In particular, each DAC stage 404(1) -404(4) is configured to receive a corresponding top voltage VTOP (1) -VTOP (4) and a corresponding bottom voltage VBOT (1) -VBOT (4). Each DAC stage 404(1) -404(4) is further configured to generate each DAC voltage VDAC (1) -VDAC (3) by dividing the voltage range of each corresponding top voltage VTOP (1) -VTOP (4) and each corresponding bottom voltage VBOT (1) -VBOT (4). For example, the reference voltage VREF is provided to DAC stage 404(1) as top voltage VTOP (1), and the ground signal is provided to DAC stage 404(1) as bottom voltage VBOT (1). Thus, the DAC voltages VDAC (1) -VDAC (3) of DAC stage 404(1) are a division of the range between the reference voltage VREF and the ground signal. In this manner, the parallel comparator stage 108(1) generates a digital signal 116(1) -116(1) (3) based on each division of the reference voltage VREF such that digital bits DG (8), DG (7) are generated based on whether the analog input voltage VIN is greater or less than each corresponding DAC voltage VDAC (1) -VDAC (3). In this manner, the DAC voltages VDAC (1) -VDAC (3) eliminate the need for trial bit code 104(1), (1) -104(1), (3) discussed with reference to fig. 1. Further, while each DAC stage 404(1) -404(4) in this aspect is configured to generate a set of DAC voltages VDAC (1) -VDAC (3), other aspects may be configured to generate any number N of DAC voltages VDAC (1) -VDAC (N).

With continued reference to fig. 4, the digital bits DG (8) -DG (3) are used to determine the top voltages VTOP (2) -VTOP (4) and the bottom voltages VBOT (2) -VBOT (4) for subsequent DAC stages 404(2) -404 (4). For example, in response to digital bits DG (8), DG (7) reaching steady state, DAC stage 404(1) provides top voltage VTOP (2) and bottom voltage VBOT (2) from output nodes RA (1), RB (1) for DAC stage 404 (2). In addition, digital bits DG (6) -DG (5) are used by DAC stage 404(2) to determine a top voltage VTOP (3) and a bottom voltage VBOT (3) to be provided to DAC stage 404(3) from output nodes RA (2), RB (2). Furthermore, the digital bits DG (4), DG (3) are used by DAC stage 404(3) to determine the top voltage VTOP (4) and the bottom voltage VBOT (4) to be provided from output nodes RA (3), RB (3) to DAC stage 404 (4). Using the digital bits DG (8), DG (7) in this manner generates a top voltage VTOP (2) and a bottom voltage VBOT (2) having a voltage range within which the analog input voltage VIN falls. Accordingly, the top voltages VTOP (1) -VTOP (4) and the bottom voltages VBOT (1) -VBOT (4) are generated such that the multi-bit parallel SA flash ADC circuit 400 can use successive approximation in generating the digital bits DG (8) -DG (1). In addition, digital bits DG (6) -DG (5) are used by DAC stage 404(2) to determine a top voltage VTOP (3) and a bottom voltage VBOT (3) to be provided to DAC stage 404(3) from output nodes RA (2), RB (2). Furthermore, the digital bits DG (4), DG (3) are used by DAC stage 404(3) to determine the top voltage VTOP (4) and the bottom voltage VBOT (4) to be provided from output nodes RA (3), RB (3) to DAC stage 404 (4). Digital bits DG (2), DG (1) are not provided to DAC stage 404(4) because DAC stage 404(4) (i.e., final DAC stage 404(4) of multi-output DAC circuit 402) does not provide a voltage to a subsequent DAC stage. In contrast, in this aspect, resistor 406 is electrically coupled to output nodes RA (4), RB (4) of DAC stage 404 (4).

With continued reference to fig. 4, it is noted that certain aspects of the multi-bit parallel SA flash ADC circuit 400 may be designed such that the number D of digital bits DG (1) -DG (a) of each corresponding parallel comparator stage 108(1) -108(B) is equal to one (1). Thus, the number C is equal to one (1) (e.g., C ^ D) -1 ^1) -1 ^1), such that each parallel comparator stage 108(1) -108(B) includes one (1) corresponding comparator circuits 114(1) and (1) -114(B) (1). In such an aspect, system comparison circuitry 109 does not include TTB circuitry 118 because each corresponding comparator circuit 114(1) digital signal 116 of (1) -114(B) (1) digital signal 116(1) of (1) -116(B) (1) serves as corresponding digital bit DG (1) -DG (a).

Employing the multi-output DAC circuit 402 as described above reduces the area consumption of the DAC circuit 102 compared to employing the DAC arrays 110(1) -110(B) illustrated in fig. 1, because each DAC stage 404(1) -404(4) may be implemented using less circuitry than each DAC array 110(1) -110(B) in fig. 1. In this regard, fig. 5 illustrates an exemplary resistor rotation circuit 500 that may be employed in each of the DAC stages 404(1) -404(4) of fig. 4. The resistor rotation circuit 500 is configured to receive a TOP voltage VTOP on a TOP voltage input node TOP and a bottom voltage VBOT on a bottom voltage input node BOT. Resistor rotation circuit 500 also includes a decoder circuit 502, decoder circuit 502 configured to receive digital bits DG (2), DG (1) of corresponding parallel comparator stages 108 and generate decoded signals DS (1) -DS (4) based on digital bits DG (2), DG (1). In this respect, decoder circuit 502 is a one-way decoder, wherein for any given value of digital bits DG (2), DG (1), only one of decoded signals DS (1) -DS (4) has a logic high "1" value. For example, the decoded signals DS (1) -DS (4) are generated according to the following logic function: DS (1) ═ (inverted DG (2) AND inverted DG (1)); DS (2) ═ (inverted DG (2) AND DG (1)); DS (3) ═ (DG (2) AND inverted DG (1)); AND DS (4) ═ DG (2) AND DG (1)). Resistor rotation circuit 500 further includes inverters 504(1) -504(4), inverters 504(1) -504(4) configured to receive corresponding decoded signals DS (1) -DS (4) and generate corresponding inverted decoded signals DS '(1) -DS' (4).

With continued reference to fig. 5, the resistor rotation circuit 500 further includes switches 506(1) -506(12), wherein a logic high "1" value closes the switches 506(1) -506(12), and a logic low "0" value opens the switches 506(1) -506 (12). The switches 506(1) -506(4) are configured to receive the corresponding inverse decoded signals DS '(1) -DS' (4). In addition, the switches 506(5), 506(7) are configured to receive the decoded signal DS (4), the switches 506(6), 506(9) are configured to receive the decoded signal DS (3), the switches 506(8), 506(11) are configured to receive the decoded signal DS (2), and the switches 506(10), 506(12) are configured to receive the decoded signal D (1). Also included is a resistor RADJ, wherein a first node 508(1) is electrically coupled to the top voltage output node RA, and a second node 508(2) is electrically coupled to the bottom voltage output node RB. The resistance of the resistor RADJ may be adjusted such that the parallel combination of the resistor RADJ and the desired resistance R _ NEXT of the NEXT DAC stage 404 is maintained at a desired constant value such that the resistor rotation circuit 500 generates the desired output. The resistance R _ NEXT is equal to the sum of the resistors 510(1) -510(4), and in this example, the resistance of the switches 506(1) -506(4) is assumed to be negligible in comparison. In addition, the resistor rotation circuit 500 includes resistors 510(1) -510(4) alternately coupled in series with corresponding switches 506(1) -506(4) and coupled in parallel with the switches 506(5) -506 (12). The resistance of resistor RADJ may be equal to the resistance of resistors 510(1) -510 (4). In particular, a first node 512(1) of the resistor 510(1) is electrically coupled to the switch 506(1), and a second node 512(1) (2) is electrically coupled to the switches 506(2), 506(6), and 506 (7). The first node 512(2) (1) of the resistor 510(2) is electrically coupled to the switch 506(2), and the second node 512(2) is electrically coupled to the first node 512(3) (1) of the resistor 510(3) and the switches 506(8), 506 (9). The first node 512(3) (1) of the resistor 510(3) is electrically coupled to the switches 506(8), (506) (9), and the second node 512(3) (2) is electrically coupled to the switch 506 (3). The first node 512(4) (1) of resistor 510(4) is electrically coupled to switches 506(3), 506(10), and 506(11), and the second node 512(4) (2) is electrically coupled to switch 506 (4). Note that the switches 506(1) - (506 (12)) may also be implemented using transistors with "sufficiently low" on-resistance.

With continued reference to fig. 5, the above configuration results in the resistor rotation circuit 500 generating DAC voltages VDAC (1) -VDAC (3), each of the DAC voltages VDAC (1) -VDAC (3) being within a voltage range between the top voltage VTOP and the bottom voltage VBOT. In this regard, resistors 510(1) -510(4) each have approximately equal resistance (e.g., 2 kiloohms (k Ω)), such that DAC voltages VDAC (1) -VDAC (3) are an equal division of the voltage range between top voltage VTOP and bottom voltage VBOT. Additionally, if the resistor rotation circuit 500 is used in fig. 4 for each DAC stage 404(1) - (404) (4), the resistance of the resistor 406 is eight (8) kiloohms (k Ω), and the resistor RADJ between the first node 508(1) and the second node 508(2) will have a value of 2.667k Ω. For example, if reference voltage VREF is equal to one (1.0) volt (V), DAC voltages VDAC (3) -VDAC (1) may be equal to 0.75V, 0.5V, and 0.25V, respectively, regardless of the values of digital bits DG (2), DG (1). In addition, the above configuration causes the resistor rotation circuit 500 to generate the next-stage TOP voltage VTOP 'on the TOP voltage output node TOP _ OUT and the next-stage bottom voltage VBOT' on the bottom voltage output node BOT _ OUT, wherein the next-stage TOP voltage VTOP 'and the next-stage bottom voltage VBOT' are determined according to which of the switches 506(1) -506(12) is opened or closed based on the digital bits DG (2), DG (1). Further, although resistor rotation circuit 500 in this aspect is configured to generate DAC voltages VDAC (1) -VDAC (3), other aspects may be configured to generate any number N of DAC voltages VDAC (1) -VDAC (N).

Fig. 6 illustrates another exemplary multi-bit parallel SA flash ADC circuit 600, the circuit 600 employing another topology of multi-output DAC circuits 602 in place of the single-output DAC circuits 112(1), (1) -112(B) (C) for each corresponding comparator circuit 114(1), (1) -114(B) (C) in the multi-bit parallel SA flash ADC circuit 100 of fig. 1. In this aspect, the multi-bit parallel SA flash ADC circuit 600 is a two (2) bit parallel four (4) bit SA flash ADC circuit 600. The multi-bit parallel SA flash ADC circuit 600 includes common elements with the multi-bit parallel SA flash ADC circuit 400 of fig. 4 and the resistor rotation circuit 500 of fig. 5, the common elements being referred to with common element numbers in fig. 4, 5, and 6, and thus will not be described in detail herein.

With continued reference to fig. 6, the multi-output DAC circuit 602 includes resistors 604(1) -604(16) connected in series, where resistor 604(16) (i.e., TOP resistor 604(16)) is electrically coupled to a TOP voltage input node TOP configured to receive a TOP voltage VTOP, and resistor 604(1) (i.e., bottom resistor 604(1)) is electrically coupled to a bottom voltage input node BOT configured to receive a bottom voltage VBOT. In this regard, each of the resistors 604(1) - (604) (16) has approximately the same resistance (e.g., 2k Ω), such that the divided voltages VDIV (1) -VDIV (15) corresponding to each pair of the resistors 604(1) - (604) (16) are approximately equal divisions of the voltage range VTOP-VBOT. For example, if the top voltage VTOP is approximately equal to 1.0V and the bottom voltage VBOT is approximately equal to 0V, the resistors 604(1) -604(16) are configured to generate the divided voltages VDIV (1) -VDIV (15) in increments differing by 0.0625V (e.g., 1/16V). Thus, the divided voltage VDIV (1) corresponding to the resistors 604(1), 604(2) is approximately equal to 0.0625V, the divided voltage VDIV (2) corresponding to the resistors 604(2), 604(3) is approximately equal to 0.125V, and the divided voltage VDIV (15) corresponding to the resistors 604(15), 604(16) is approximately equal to 0.9375V. In addition, the divided voltage VDIV (12) is provided to the comparator circuits 114(1) in the parallel comparator stage 108(1), the divided voltage VDIV (8) is provided to the comparator circuits 114(1) (2) in the parallel comparator stage 108(1), and the divided voltage VDIV (4) is provided to the comparator circuits 114(1) (3) in the parallel comparator stage 108 (1).

With continued reference to fig. 6, the multi-output DAC circuit 602 further includes switches 606(1) -606(12) electrically coupled to the parallel comparator stage 108 (2). Decoder circuit 502 is configured to receive digital bits DG (4), DG (3) of corresponding parallel comparator stage 108(1) and to generate decoded signals DS (4) -DS (1). The switches 606(1), 606(5), and 606(9) are configured to receive the decoded signal DS (4), and the switches 606(2), 606(6), and 606(10) are configured to receive the decoded signal DS (3). In addition, the switches 606(3), 606(7), and 606(11) are configured to receive the decoded signal DS (2), and the switches 606(4), 606(8), and 606(12) are configured to receive the decoded signal DS (2). The divided voltages VDIV (15), VDIV (11), VDIV (7), and VDIV (3) are provided to switches 606(1) -606(4), respectively, where the switches 606(1) -606(4) are electrically coupled to the comparator circuits 114(2) (1) in the parallel comparator stage 108 (2). The divided voltages VDIV (14), VDIV (10), VDIV (6), and VDIV (2) are provided to switches 606(5) -606(8), respectively, where switches 606(5) -606(8) are electrically coupled to comparator circuits 114(2) in parallel comparator stage 108 (2). Further, the divided voltages VDIV (13), VDIV (9), VDIV (5), and VDIV (1) are provided to switches 606(9) -606(12), respectively, where switches 606(9) -606(12) are electrically coupled to comparator circuits 114(2) (3) in parallel comparator stage 108 (2). Employing the multi-output DAC circuit 602 as described above reduces area consumption of the DAC circuit 102 compared to employing the DAC arrays 110(1) -110(B) (C) depicted in fig. 1, because the multi-output DAC circuit 602 may be implemented with less circuitry than each DAC array 110(1) -110(B) (C) in fig. 1.

The elements described herein are sometimes referred to as means for performing a specified function. To this end, DAC circuit 102 is sometimes referred to herein as a "means for converting digital values to analog values configured to receive a reference voltage and generate a plurality of DAC analog signals, where each DAC analog signal is based on the reference voltage. "parallel comparator stages 108(1) - (108B) are sometimes referred to herein as" means for comparing values in parallel ". Comparator circuit 114(1), (1) -114(B) (C) is sometimes referred to herein as "means for comparing values", wherein "each means for comparing values in parallel comprises a number of means for comparing, wherein the number of means for comparing for each means for comparing values in parallel is equal to two (2) raised to the power of the number of digital bits of the corresponding means for comparing values in parallel minus one (1). "additionally," each means for comparing is configured to receive an analog input signal, receive a corresponding DAC analog signal, and generate a digital signal, "wherein" the digital signal has a logic high value if the analog input signal has a greater voltage than the corresponding DAC analog signal, and the digital signal has a logic low value if the analog input signal has a lesser voltage than the corresponding DAC analog signal. "TTB circuit 118, sometimes referred to herein as a" means for binary conversion, "is configured to receive a digital signal from several of each of a plurality of means for comparing values in parallel and generate one or more digital bits corresponding to each of the means for comparing values in parallel, wherein the one or more digital bits collectively generate a digital output signal that is a digital representation of an analog input signal. The "multi-output DAC circuit 402 is sometimes referred to herein as a" multi-output device for converting digital values to analog values. Resistor rotation circuit 500 is sometimes referred to herein as a "means for dividing voltages configured to generate a corresponding number of DAC analog signals by generating a division of a voltage range. "

The multi-bit parallel SA flash ADC circuit according to aspects disclosed herein may be provided or integrated in any processor-based device. Examples include, but are not limited to, a set top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a Global Positioning System (GPS) device, a mobile phone, a cellular phone, a smartphone, a Session Initiation Protocol (SIP) phone, a tablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smartwatch, a health product or fitness tracker, glasses, etc.), a desktop computer, a Personal Digital Assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a Digital Video Disc (DVD) player, a portable digital video player, an automobile, a vehicle component, a, Avionics systems, unmanned aircraft, and multi-axis helicopters.

In this regard, fig. 7 illustrates one example of a processor-based system 700 that may include elements that employ the multi-bit parallel SA flash ADC circuits 100, 200, 400, and 600 of fig. 1, 2, 4, and 6, respectively. In this example, the processor-based system 700 includes one or more Central Processing Units (CPUs) 702, each of which includes one or more processors 704. The CPU(s) 702 may have a cache memory 706 coupled to the processor(s) 704 for fast access to temporarily stored data. The CPU(s) 702 is coupled to a system bus 708 and may couple master and slave devices included in the processor-based system 700 to each other. As is well known, CPU(s) 702 communicate with these other devices by exchanging address, control, and data information over system bus 708. For example, CPU(s) 702 may communicate a bus transaction request to memory controller 710, which is an example of a slave device. Although not illustrated in fig. 7, multiple system buses 708 may be provided, with each system bus 708 constituting a different fabric.

Other master and slave devices may be connected to the system bus 708. As shown in fig. 7, these devices may include, for example, a memory system 712, one or more input devices 714, one or more output devices 716, one or more network interface devices 718, and one or more display controllers 720. Input device(s) 714 may include any type of input device, including but not limited to input keys, switches, speech processors, etc.Output device(s) 716 may include any type of output device, including but not limited to audio, video, other visual indicators, and the like. Network interface device(s) 718 may be any device configured to allow data exchange with network 722. Network 722 may be any type of network including, but not limited to, a wired or wireless network, a private or public network, a Local Area Network (LAN), a Wireless Local Area Network (WLAN), a Wide Area Network (WAN), BLUETOOTH^TMNetworks, and the internet. The network interface device(s) 718 may be configured to support any type of communication protocol desired. Memory system 712 may include one or more memory units 724(0) -724 (N).

The CPU(s) 702 may also be configured to access the display controller(s) 720 over the system bus 708 to control information sent to the display(s) 726. Display controller(s) 720 sends information to display(s) 726 for display via one or more video processors 728, which video processors 728 process the information to be displayed into a format suitable for display(s) 726. Display(s) 726 may include any type of display including, but not limited to, a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), a plasma display, a Light Emitting Diode (LED) display, and the like.

Fig. 8 illustrates an exemplary wireless communication device 800 that includes Radio Frequency (RF) components formed in an Integrated Circuit (IC)802, where the RF components may include elements that employ the multi-bit parallel SA flash ADC circuits 100, 200, 400, and 600 of fig. 1, 2, 4, and 6, respectively. To this end, the wireless communication device 800 may be provided in an IC 802. As an example, the wireless communication device 800 may include or be provided in any of the above-mentioned reference devices. As shown in fig. 8, the wireless communication device 800 includes a transceiver 804 and a data processor 806. The data processor 806 may include memory for storing data and program code. The transceiver 804 includes a transmitter 808 and a receiver 810 that support bi-directional communication. In general, the wireless communication device 800 may include any number of transmitters 808 and/or receivers 810 for any number of communication systems and frequency bands. All or a portion of the transceiver 804 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed signal ICs, and the like.

The transmitter 808 or receiver 810 may be implemented using a super-heterodyne architecture or a direct conversion architecture. In the super-heterodyne architecture, for receiver 810, a signal is frequency converted between RF and baseband in multiple stages, e.g., from RF to an Intermediate Frequency (IF) in one stage and then from IF to baseband in another stage. In the direct conversion architecture, the signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the wireless communication device 800 of fig. 8, the transmitter 808 and the receiver 810 are implemented with a direct conversion architecture.

In the transmit path, data processor 806 processes the data to be transmitted and provides I and Q analog output signals to transmitter 808. In the exemplary wireless communication device 800, the data processor 806 includes DACs 812(1), 812(2) for converting digital signals generated by the data processor 806 into I and Q analog output signals, e.g., I and Q output currents, for further processing.

Within transmitter 808, low pass filters 814(1), 814(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by previous digital to analog conversion. Amplifiers (AMP)816(1), 816(2) amplify the signals from low pass filters 814(1), 814(2), respectively, and provide I and Q baseband signals. Upconverter 818 upconverts the I and Q baseband signals with I and Q Transmit (TX) Local Oscillator (LO) signals from TX LO signal generator 822 through mixers 820(1), 820(2) to provide an upconverted signal 824. Filter 826 filters upconverted signal 824 to remove undesired signals caused by frequency upconversion as well as noise in the receive band. A Power Amplifier (PA)828 amplifies the upconverted signal 824 from filter 826 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 830 and transmitted via an antenna 832.

In the receive path, an antenna 832 receives signals transmitted by base stations and provides a received RF signal, which is routed through a duplexer or switch 830 and provided to a Low Noise Amplifier (LNA) 834. Duplexer or switch 830 is designed to operate with a particular Receive (RX) to TX duplexer frequency spacing such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 834 and filtered by filter 836 to obtain the desired RF input signal. Downconversion mixers 838(1), 838(2) mix the output of filter 836 with I and Q RX LO signals (i.e., LO _ I and LO _ Q) from an RX LO signal generator 840 to generate I and Q baseband signals. The I and Q baseband signals are amplified by Amplifiers (AMP)842(1), 842(2) and further filtered by low pass filters 844(1), 844(2) to obtain I and Q analog input signals, which are provided to data processor 806. In this example, the data processor 806 includes ADCs 846(1), 846(2) for converting analog input signals to digital signals for further processing by the data processor 806.

In the wireless communication device 800 of fig. 8, a TX LO signal generator 822 generates I and Q TX LO signals for frequency upconversion, and an RX LO signal generator 840 generates I and Q RX LO signals for frequency downconversion. Each LO signal is a periodic signal with a particular fundamental frequency. TX phase-locked loop (PLL) circuit 848 receives timing information from data processor 806 and generates control signals that adjust the frequency and/or phase of the TX LO signals from TX LO signal generator 822. Similarly, RX PLL circuit 850 receives timing information from data processor 806 and generates control signals that are used to adjust the frequency and/or phase of the RX LO signals from RX LO signal generator 840.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, memory or another computer-readable medium storing instructions that are executed by a processor or other processing device, or combinations of both. As an example, the master and slave devices described herein may be employed in any circuit, hardware component, Integrated Circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented may be related to the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

Aspects disclosed herein may be embodied in hardware and instructions stored in hardware and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), electrically programmable ROM (eprom), electrically erasable programmable ROM (eeprom), registers, hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in many different sequences other than those illustrated. Further, operations described in a single operational step may actually be performed in several different steps. Additionally, one or more of the operational steps discussed in the exemplary aspects may be combined. It should be understood that many different modifications of the operational steps shown in the flow chart diagrams may be made as would be apparent to one skilled in the art. Those of skill in the art would further appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.