阅读说明：本技术 芯片的扫频装置、方法和电子设备 (Frequency sweeping device and method for chip and electronic equipment ) 是由 严献平 杨鑫 于 2019-10-10 设计创作，主要内容包括：本申请实施例公开了一种芯片的扫频装置、方法和电子设备,能够提高芯片的工作频率和算力。该芯片的扫频装置包括：N组芯片,设置于电路板上,其中,该N组芯片中的每组芯片包括至少一个芯片,N为大于1的正整数；控制器,连接于该N组芯片,用于依次对该N组芯片进行扫频测试,并确定该N组芯片中每组芯片的工作频率。(The embodiment of the application discloses a frequency sweeping device and method of a chip and electronic equipment, and the frequency sweeping device and method can improve the working frequency and computing power of the chip. The frequency sweeping device of the chip comprises: the chip module comprises N groups of chips arranged on a circuit board, wherein each group of chips in the N groups of chips comprises at least one chip, and N is a positive integer greater than 1; and the controller is connected with the N groups of chips and is used for sequentially carrying out frequency sweep test on the N groups of chips and determining the working frequency of each group of chips in the N groups of chips.)

1. A frequency sweeping device of a chip is characterized by comprising:

the chip module comprises N groups of chips arranged on a circuit board, wherein each group of chips in the N groups of chips comprises at least one chip, and N is a positive integer greater than 1;

and the controller is connected with the N groups of chips and is used for sequentially carrying out frequency sweep test on the N groups of chips and determining the working frequency of each group of chips in the N groups of chips.

2. A sweeping device according to claim 1, wherein the data lines of the N groups of chips are connected in series, the circuit board includes M voltage domains, M being a positive integer greater than 1, and the at least one chip is located in the M voltage domains.

3. A sweeping device according to claim 2, wherein each of the N groups of chips includes M chips, and the M chips are respectively located in the M voltage domains.

4. A sweeping device according to claim 3, wherein the N groups of chips are arranged in N columns on the circuit board, and the chips in the M voltage domains are arranged in M rows on the circuit board.

5. A frequency sweeping device according to any one of claims 2 to 4, wherein chips located in the same voltage domain on the circuit board are not subjected to frequency sweeping testing at the same time.

6. A sweeping device according to any one of claims 1 to 5, wherein the controller is configured to:

and sequentially carrying out frequency sweep test on the N groups of chips according to the position sequence from the a group of chips in the N groups of chips, wherein a is more than or equal to 1 and less than or equal to N, and a is a positive integer.

7. A sweeping device according to any one of claims 1 to 6, wherein the controller is configured to:

for a kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as the ith test frequency in X test frequencies, and sending test data to the kth group of chips, wherein the X test frequencies are sequentially increased in an increasing manner, X is a positive integer greater than 1, i is more than or equal to 2 and less than or equal to X, and i is a positive integer;

and acquiring and judging whether the number of random numbers of each chip in the kth group of chips is within a first threshold range so as to determine the working frequency of the kth group of chips, wherein the random numbers are data generated after each chip in the kth group of chips receives test data.

8. A sweeping device according to claim 7, wherein the controller is configured to:

judging that the number of the random numbers of each chip in the kth group of chips is within a first threshold range, and when i +1 is not more than X, performing frequency sweep test on the kth group of chips by adopting the i +1 test frequency in the X test frequencies;

judging that the number of the random numbers of each chip in the kth group of chips is within a first threshold range, and when i +1 is greater than X, determining that the working frequency of the kth group of chips is the Xth test frequency in the X test frequencies;

and when the number of the random numbers of at least one chip in the kth group of chips is judged to be out of a first threshold range, determining the working frequency of the kth group of chips to be the i-1 test frequency in the X test frequencies.

9. A sweeping device according to claim 7 or 8, wherein the controller is further configured to:

and setting the test frequency of the chips of the other groups except the kth group of chips in the N groups of chips as the first test frequency in the X test frequencies.

10. A sweeping device according to any one of claims 1 to 6, wherein the controller is configured to:

for a kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as a jth test frequency in Y test frequencies, and sending test data to the kth group of chips, wherein the Y test frequencies are sequentially decreased progressively, Y is a positive integer more than 1, j is more than or equal to 2 and less than or equal to Y, and j is a positive integer;

and acquiring and judging whether the number of random numbers of each chip in the kth group of chips is within a first threshold range so as to determine the working frequency of the kth group of chips, wherein the random numbers are data generated after each chip in the kth group of chips receives test data.

11. A sweeping device as claimed in claim 10, wherein the controller is configured to:

judging that the number of random numbers of at least one chip in the kth group of chips is out of a first threshold range, and when j +1 is smaller than Y, performing frequency sweep test on the kth group of chips by adopting the j +1 test frequency in the Y test frequencies;

when the number of the random numbers of at least one chip in the kth group of chips is judged to be out of a first threshold range and j +1 is equal to Y, determining that the working frequency of the kth group of chips is the Yth test frequency in the Y test frequencies;

and when the number of the random numbers of each chip in the kth group of chips is judged to be within a first threshold range, determining the working frequency of the kth group of chips to be the jth test frequency in the Y test frequencies.

12. A sweeping device according to claim 10 or 11, wherein the controller is further configured to:

and setting the test frequency of the chips of the other groups except the kth group of chips in the N groups of chips as the Yth test frequency in the Y test frequencies.

13. A sweeping device according to any one of claims 1 to 6, wherein the controller is configured to:

for a kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as a w-th test frequency in Z test frequencies, and sending test data to the kth group of chips, wherein the Z test frequencies are sequentially increased or sequentially decreased, Z is a positive integer greater than 1, w is more than or equal to 2 and less than or equal to Z, and w is a positive integer;

and acquiring and judging whether the sum of the number of random numbers of all chips in the kth group of chips is within a second threshold range so as to determine the working frequency of the kth group of chips, wherein the random numbers are data generated after each chip in the kth group of chips receives test data.

14. A sweeping device according to any one of claims 1 to 13, further comprising: and the memory is used for storing the working frequency of each group of chips in the N groups of chips.

15. A frequency sweeping method of a chip is characterized by comprising the following steps:

sequentially carrying out frequency sweep test on N groups of chips on a circuit board, wherein each group of chips in the N groups of chips comprises at least one chip, and N is a positive integer greater than 1;

and determining the working frequency of each group of chips in the N groups of chips.

16. A sweeping method according to claim 15, wherein the data lines of the N groups of chips are connected in series, the circuit board includes M voltage domains, M being a positive integer greater than 1, and the at least one chip is located in the M voltage domains.

17. A frequency sweeping method according to claim 16, wherein each of the N groups of chips is equal in number and includes M chips, and the M chips are respectively located in the M voltage domains.

18. A frequency sweeping method according to claim 17, wherein the N groups of chips are arranged in N columns on the circuit board, and the chips in the M voltage domains are arranged in M rows on the circuit board.

19. A frequency sweeping method according to any one of claims 16 to 18, wherein chips located in the same voltage domain on the circuit board are not subjected to frequency sweeping testing at the same time.

20. A frequency sweeping method according to any one of claims 15 to 19, wherein the sequentially performing frequency sweeping tests on N groups of chips comprises:

and sequentially carrying out frequency sweep test on the N groups of chips according to the position sequence from the a group of chips in the N groups of chips, wherein a is more than or equal to 1 and less than or equal to N, and a is a positive integer.

21. A frequency sweeping method according to any one of claims 15 to 20, wherein the sequentially performing frequency sweeping tests on N groups of chips comprises:

for a kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as the ith test frequency in X test frequencies, and sending test data to the kth group of chips, wherein the X test frequencies are sequentially increased in an increasing manner, X is a positive integer greater than 1, i is more than or equal to 2 and less than or equal to X, and i is a positive integer;

and acquiring and judging whether the number of random numbers of each chip in the kth group of chips is within a threshold range so as to determine the working frequency of the kth group of chips, wherein the random numbers are data generated after each chip in the kth group of chips receives test data.

22. A sweeping method according to claim 21, wherein the obtaining and judging whether the number of random numbers of each chip in the kth group of chips is within a threshold range to determine the operating frequency of the kth group of chips comprises:

judging that the number of the random numbers of each chip in the kth group of chips is within a first threshold range, and when i +1 is not more than X, performing frequency sweep test on the kth group of chips by adopting the i +1 test frequency in the X test frequencies;

judging that the number of the random numbers of each chip in the kth group of chips is within a first threshold range, and when i +1 is greater than X, determining that the working frequency of the kth group of chips is the Xth test frequency in the X test frequencies;

and when the number of the random numbers of at least one chip in the kth group of chips is judged to be out of a first threshold range, determining the working frequency of the kth group of chips to be the i-1 test frequency in the X test frequencies.

23. A frequency sweeping method according to claim 21 or 22, wherein the sequentially performing frequency sweeping tests on N groups of chips further comprises: and setting the test frequency of the chips of the other groups except the kth group of chips in the N groups of chips as the first test frequency in the X test frequencies.

24. A frequency sweeping method according to any one of claims 15 to 20, wherein the sequentially performing frequency sweeping tests on N groups of chips comprises:

for a kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as a jth test frequency in Y test frequencies, and sending test data to the kth group of chips, wherein the Y test frequencies are sequentially increased in an increasing manner, Y is a positive integer more than 1, j is more than or equal to 2 and less than or equal to Y, and j is a positive integer;

and acquiring and judging whether the number of random numbers of each chip in the kth group of chips is within a threshold range so as to determine the working frequency of the kth group of chips, wherein the random numbers are data generated after each chip in the kth group of chips receives test data.

25. A sweeping method according to claim 24, wherein the obtaining and judging whether the number of random numbers of the kth group of chips is within a threshold range to determine the operating frequency of the kth group of chips comprises:

judging that the number of random numbers of at least one chip in the kth group of chips is out of a first threshold range, and when j +1 is smaller than Y, performing frequency sweep test on the kth group of chips by adopting the j +1 test frequency in the Y test frequencies;

when the number of the random numbers of at least one chip in the kth group of chips is judged to be out of a first threshold range and j +1 is equal to Y, determining that the working frequency of the kth group of chips is the Yth test frequency in the Y test frequencies;

and when the number of the random numbers of each chip in the kth group of chips is judged to be within a first threshold range, determining the working frequency of the kth group of chips to be the jth test frequency in the Y test frequencies.

26. A frequency sweeping method according to claim 24 or 25, wherein the sequentially performing frequency sweeping tests on N groups of chips further comprises: and setting the test frequency of the chips of the other groups except the kth group of chips in the N groups of chips as the Yth test frequency in the Y test frequencies.

27. A frequency sweeping method according to any one of claims 15 to 20, wherein the sequentially performing frequency sweeping tests on N groups of chips comprises:

for a kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as a w-th test frequency in Z test frequencies, and sending test data to the kth group of chips, wherein the Z test frequencies are sequentially increased or sequentially decreased, Z is a positive integer greater than 1, w is more than or equal to 2 and less than or equal to Z, and w is a positive integer;

and acquiring and judging whether the sum of the number of random numbers of all chips in the kth group of chips is within a second threshold range so as to determine the working frequency of the kth group of chips, wherein the random numbers are data generated after each chip in the kth group of chips receives test data.

28. A frequency sweeping method according to any one of claims 15 to 27, further comprising:

and storing the working frequency of each group of chips in the N groups of chips.

29. An electronic device, comprising:

a frequency sweeping apparatus for a chip as claimed in any one of claims 1 to 14.

30. A frequency sweeping apparatus for a chip, comprising a processor and a memory, the memory being configured to store program code, the processor being configured to invoke the program code to perform the frequency sweeping method of any one of claims 15 to 28.

31. A computer readable storage medium for storing program code for executing the frequency sweeping method according to any one of claims 15 to 28.

32. A processing apparatus, comprising:

the chip module comprises N groups of chips, a circuit board and a chip module, wherein the N groups of chips are arranged on the circuit board, each group of chips in the N groups of chips comprises at least one chip, and N is a positive integer greater than 1;

the working frequency of each chip in each group of chips in the N groups of chips is the same, and the working frequencies of at least two groups of chips in the N groups of chips are different.

33. The processing apparatus as in claim 32, wherein the N groups of chips are processor chips for performing data calculations;

the N groups of chips are arranged on a plurality of voltage domains of the circuit board.

34. The processing apparatus according to claim 33, wherein the data lines of the N groups of chips are connected in series and the plurality of voltage domains are connected in parallel.

35. The processing apparatus according to any one of claims 32 to 34, wherein the circuit board comprises M voltage domains, M being a positive integer greater than 1;

a plurality of chips in a group of chips in the N groups of chips are located in the M voltage domains.

36. The processing apparatus as in claim 35 wherein each of the N sets of chips comprises M chips, the M chips being respectively located in the M voltage domains.

37. The processing apparatus according to claim 35 or 36, wherein the sum of the operating frequencies of the chips on at least two of the M voltage domains is equal.

38. The processing apparatus according to any one of claims 35 to 37, wherein the N groups of chips are arranged in N columns on the circuit board, and the chips on the M voltage domains are arranged in M rows on the circuit board.

39. The processing apparatus according to any one of claims 32-38, further comprising:

and the controller is connected with the N groups of chips and used for controlling each chip in the N groups of chips to work under the working frequency.

40. The processing apparatus of claim 39, wherein the controller is further configured to: and determining the working frequency of each group of chips in the N groups of chips.

41. The processing apparatus of claim 40, wherein the controller is configured to: and sequentially carrying out frequency sweep test on the N groups of chips, and determining the working frequency of each group of chips in the N groups of chips.

42. The processing apparatus according to any one of claims 32 to 41, further comprising:

and the memory is used for storing the working frequency of each group of chips in the N groups of chips.

43. An electronic device, comprising:

the processing apparatus of any one of claims 32 to 42.

Technical Field

The present application relates to the field of chip technologies, and more particularly, to a frequency sweeping apparatus and method for a chip, and an electronic device.

Background

With the development of information technology, the computational power requirement of a chip for performing data operation processing is continuously and rapidly increased in the fields of Artificial Intelligence (AI), digital certificate processing and the like.

Currently, in some devices dedicated to data processing, a processor uses a plurality of chips to perform calculations, so as to increase the speed of data processing. Generally, a plurality of chips are swept to determine the uniform working frequency. If one of the chips has poor performance, the resulting barrel effect will cause the lower working frequency of other chips, which will affect the computational power of other chips, and thus the system performance of the device.

Therefore, how to solve the problem of the barrel effect caused by the chips with poor performance in the frequency sweeping process and improve the working frequency and the calculation power of a plurality of chips is a problem to be solved urgently.

Disclosure of Invention

The embodiment of the application provides a frequency sweeping device and method of a chip and electronic equipment, and the working frequency and the computing power of the chip can be improved.

In a first aspect, a frequency sweep apparatus for a chip is provided, including: the chip module comprises N groups of chips arranged on a circuit board, wherein each group of chips in the N groups of chips comprises at least one chip, and N is a positive integer greater than 1;

and the controller is connected with the N groups of chips and is used for sequentially carrying out frequency sweep test on the N groups of chips and determining the working frequency of each group of chips in the N groups of chips.

In the technical scheme of the embodiment of the application, the controller performs frequency sweep test on all the chips in the N groups of chips to obtain the uniform working frequency of all the chips, but performs frequency sweep test on the N groups of chips in sequence to obtain the working frequency of each group of chips, so that the influence of the chips with poor performance in the N groups of chips on other chips is reduced, the chips are prevented from generating a barrel effect, the working frequency of a plurality of chips is improved, and the calculation power and the system performance of the chips are improved.

In one possible implementation, the data lines of the N groups of chips are connected in series, the circuit board includes M voltage domains, M is a positive integer greater than 1, and the at least one chip is located in the M voltage domains.

In one possible implementation, each of the N groups of chips includes M chips, and the M chips are respectively located in the M voltage domains.

In the implementation mode, M chips of each group of chips are respectively located in M voltage domains, wherein when one group of chips is subjected to frequency sweep test, the test of the group of chips does not affect other chips in the same voltage domain, and the frequency sweep test obtains the highest working frequency of N groups of chips.

In one possible implementation, the N groups of chips are arranged in N rows on the circuit board, and the chips in the M voltage domains are arranged in M rows on the circuit board.

In one possible implementation, chips located in the same voltage domain on the circuit board do not perform the frequency sweep test at the same time.

In one possible implementation, the controller is configured to: and sequentially carrying out frequency sweep test on the N groups of chips according to the position sequence from the a group of chips in the N groups of chips, wherein a is more than or equal to 1 and less than or equal to N, and a is a positive integer.

In one possible implementation, the controller is configured to:

for a kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as the ith test frequency in X test frequencies, and sending test data to the kth group of chips, wherein the X test frequencies are sequentially increased in an increasing manner, X is a positive integer greater than 1, i is more than or equal to 2 and less than or equal to X, and i is a positive integer;

and acquiring and judging whether the number of the random numbers of each chip in the kth group of chips is within a first threshold range so as to determine the working frequency of the kth group of chips, wherein the random numbers are data generated after each chip in the kth group of chips receives test data.

In one possible implementation, the controller is configured to: judging whether the number of the random numbers of each chip in the kth group of chips is within a first threshold range and i +1 is less than or equal to X, and performing frequency sweep test on the kth group of chips by adopting the i +1 test frequency in the X test frequencies;

judging whether the number of the random numbers of each chip in the kth group of chips is within a first threshold range and when i +1 is greater than X, determining the working frequency of the kth group of chips as the Xth test frequency in the X test frequencies;

and when the number of the random numbers of at least one chip in the kth group of chips is judged to be out of the first threshold range, determining the working frequency of the kth group of chips as the (i-1) th test frequency in the X test frequencies.

In a possible implementation manner, the test frequency of the other groups of chips except the k-th group of chips in the N groups of chips is set as the first test frequency in the X test frequencies.

In one possible implementation, the controller is configured to:

for the kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as the jth test frequency in Y test frequencies, and sending test data to the kth group of chips, wherein the Y test frequencies are sequentially decreased progressively, Y is a positive integer more than 1, j is more than or equal to 2 and less than or equal to Y, and j is a positive integer;

and acquiring and judging whether the number of the random numbers of each chip in the kth group of chips is within a first threshold range so as to determine the working frequency of the kth group of chips, wherein the random numbers are data generated after each chip in the kth group of chips receives test data.

In one possible implementation, the controller is configured to: judging that the number of random numbers of at least one chip in the kth group of chips is out of a first threshold range, and when j +1 is smaller than Y, performing frequency sweep test on the kth group of chips by adopting the j +1 test frequency in the Y test frequencies;

when the number of the random numbers of at least one chip in the kth group of chips is judged to be out of a first threshold range and j +1 is equal to Y, determining the working frequency of the kth group of chips as the Yth test frequency in the Y test frequencies;

and when the number of the random numbers of each chip in the kth group of chips is judged to be within a first threshold range, determining the working frequency of the kth group of chips to be the jth test frequency in the Y test frequencies.

In one possible implementation, the controller is further configured to: and setting the test frequency of the chips of the other groups except the kth group of chips in the N groups of chips as the Yth test frequency in the Y test frequencies.

In one possible implementation, the controller is configured to:

for the kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as the w-th test frequency in the Z test frequencies, and sending test data to the kth group of chips, wherein the Z test frequencies are sequentially increased or sequentially decreased, Z is a positive integer greater than 1, w is more than or equal to 2 and less than or equal to Z, and w is a positive integer;

and acquiring and judging whether the sum of the number of the random numbers of all the chips in the kth group of chips is within a second threshold range so as to determine the working frequency of the kth group of chips, wherein the random numbers are data generated after each chip in the kth group of chips receives test data.

In one possible implementation, Z may be equal to X as the Z test frequencies sequentially increase and Z may be equal to Y as the Z test frequencies sequentially decrease.

In a possible implementation manner, the frequency sweeping apparatus further includes: and the memory is used for storing the working frequency of each group of chips in the N groups of chips.

In a second aspect, a frequency sweeping method for a chip is provided, which includes: sequentially carrying out frequency sweep test on N groups of chips on the circuit board, wherein each group of chips in the N groups of chips comprises at least one chip, and N is a positive integer greater than 1; and determining the working frequency of each group of chips in the N groups of chips.

In one possible implementation, the data lines of the N groups of chips are connected in series, the circuit board includes M voltage domains, M is a positive integer greater than 1, and the at least one chip is located in the M voltage domains.

In a possible implementation manner, each of the N groups of chips has the same number and includes M chips, and the M chips are respectively located in the M voltage domains.

In one possible implementation, the N groups of chips are arranged in N rows on the circuit board, and the chips in the M voltage domains are arranged in M rows on the circuit board.

In one possible implementation, chips located in the same voltage domain on the circuit board do not perform the frequency sweep test at the same time.

In a possible implementation manner, the sequentially performing the frequency sweep test on the N groups of chips includes:

and sequentially carrying out frequency sweep test on the N groups of chips according to the position sequence from the ith group of chips in the N groups of chips, wherein i is more than or equal to 1 and less than or equal to N, and i is a positive integer.

In a possible implementation manner, the sequentially performing the frequency sweep test on the N groups of chips includes:

for the kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as the ith test frequency in the X test frequencies, and sending test data to the kth group of chips, wherein the X test frequencies are sequentially increased, X is a positive integer more than 1, i is more than or equal to 2 and less than or equal to X, and i is a positive integer;

and acquiring and judging whether the number of the random numbers of each chip in the kth group of chips is within a threshold range so as to determine the working frequency of the kth group of chips, wherein the random numbers are data generated after each chip in the kth group of chips receives test data.

In a possible implementation manner, the obtaining and determining whether the number of random numbers of each chip in the kth group of chips is within a threshold range to determine the operating frequency of the kth group of chips includes:

judging whether the number of the random numbers of each chip in the kth group of chips is within a first threshold range and i +1 is less than or equal to X, and performing frequency sweep test on the kth group of chips by adopting the i +1 test frequency in the X test frequencies;

judging whether the number of the random numbers of each chip in the kth group of chips is within a first threshold range and when i +1 is greater than X, determining the working frequency of the kth group of chips as the Xth test frequency in the X test frequencies;

and when the number of the random numbers of at least one chip in the kth group of chips is judged to be out of the first threshold range, determining the working frequency of the kth group of chips as the (i-1) th test frequency in the X test frequencies.

In a possible implementation manner, the sequentially performing the frequency sweep test on the N groups of chips further includes: and setting the test frequency of the chips of the other groups except the kth group of chips in the N groups of chips as the first test frequency in the X test frequencies.

In a possible implementation manner, the sequentially performing the frequency sweep test on the N groups of chips includes:

for the kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as the jth test frequency in Y test frequencies, and sending test data to the kth group of chips, wherein the Y test frequencies are sequentially decreased progressively, Y is a positive integer more than 1, j is more than or equal to 2 and less than or equal to Y, and j is a positive integer;

and acquiring and judging whether the number of the random numbers of each chip in the kth group of chips is within a first threshold range so as to determine the working frequency of the kth group of chips, wherein the random numbers are data generated after each chip in the kth group of chips receives test data.

In a possible implementation manner, the obtaining and determining whether the number of the random numbers of the kth group of chips is within a threshold range to determine the operating frequency of the kth group of chips includes:

judging that the number of random numbers of at least one chip in the kth group of chips is out of a first threshold range, and when j +1 is smaller than Y, performing frequency sweep test on the kth group of chips by adopting the j +1 test frequency in the Y test frequencies;

when the number of the random numbers of at least one chip in the kth group of chips is judged to be out of a first threshold range and j +1 is equal to Y, determining the working frequency of the kth group of chips as the Yth test frequency in the Y test frequencies;

and when the number of the random numbers of each chip in the kth group of chips is judged to be within a first threshold range, determining the working frequency of the kth group of chips to be the jth test frequency in the Y test frequencies.

In a possible implementation manner, the sequentially performing the frequency sweep test on the N groups of chips further includes: and setting the test frequency of the chips of the other groups except the kth group of chips in the N groups of chips as the Yth test frequency in the Y test frequencies.

In a possible implementation manner, the sequentially performing the frequency sweep test on the N groups of chips includes:

for the kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as the w-th test frequency in Z test frequencies, and sending test data to the kth group of chips, wherein the Z test frequencies are sequentially increased or sequentially decreased, Z is a positive integer greater than 1, w is more than or equal to 2 and less than or equal to Z, and w is a positive integer;

and acquiring and judging whether the sum of the number of the random numbers of all the chips in the kth group of chips is within a second threshold range so as to determine the working frequency of the kth group of chips, wherein the random numbers are data generated after each chip in the kth group of chips receives test data.

In one possible implementation, Z may be equal to X as the Z test frequencies sequentially increase and Z may be equal to Y as the Z test frequencies sequentially decrease.

In one possible implementation, the frequency sweeping method further includes: and storing the working frequency of each group of chips in the N groups of chips.

In a third aspect, an electronic device is provided, including: such as the first aspect or the chip in any possible implementation manner of the first aspect.

In a fourth aspect, a frequency sweeping device for a chip is provided, which includes a processor and a memory, where the memory is used to store a program code, and the processor is used to call the program code to execute the frequency sweeping method in the second aspect or any possible implementation manner of the second aspect.

In a fifth aspect, a computer storage medium is provided for storing program code for performing the frequency sweep method of the second aspect or any possible implementation manner of the second aspect.

In a sixth aspect, there is provided a processing apparatus comprising: the chip module comprises N groups of chips, a circuit board and a chip module, wherein the N groups of chips are arranged on the circuit board, each group of chips in the N groups of chips comprises at least one chip, and N is a positive integer greater than 1;

the working frequency of each chip in each group of chips in the N groups of chips is the same, and the working frequencies of at least two groups of chips in the N groups of chips are different.

In one possible implementation, the N groups of chips are processor chips for performing data calculation; the N groups of chips are arranged on a plurality of voltage domains of the circuit board.

In one possible implementation, the data lines of the N groups of chips are connected in series, and the plurality of voltage domains are connected in parallel.

In one possible implementation, the circuit board includes M voltage domains, M being a positive integer greater than 1; a plurality of chips in one of the N sets of chips are located in the M voltage domains.

In a possible implementation manner, each of the N groups of chips includes M chips, and the M chips are respectively located in the M voltage domains.

In one possible implementation, the sum of the operating frequencies of the chips on at least two of the M voltage domains is equal.

In one possible implementation, the N groups of chips are arranged in N rows on the circuit board, and the chips in the M voltage domains are arranged in M rows on the circuit board.

In one possible implementation, the processing apparatus further includes: and the controller is connected with the N groups of chips and used for controlling each chip in the N groups of chips to work under the working frequency.

In one possible implementation, the controller is further configured to: and determining the working frequency of each group of chips in the N groups of chips.

In one possible implementation, the controller is configured to: and sequentially carrying out frequency sweep test on the N groups of chips, and determining the working frequency of each group of chips in the N groups of chips.

In one possible implementation, the processing apparatus further includes: and the memory is used for storing the working frequency of each group of chips in the N groups of chips.

In a seventh aspect, an electronic device is provided, including: such as the frequency sweeping device of the chip in the sixth aspect or any possible implementation manner of the sixth aspect.

Drawings

FIG. 1 is a schematic block diagram of an electronic device to which the present application may be applied;

fig. 2 is a schematic block diagram of a chip frequency sweeping apparatus according to an embodiment of the present application;

FIG. 3 is a schematic flow chart diagram of a chip frequency sweeping method according to an embodiment of the present application;

FIG. 4 is a schematic diagram of operating frequencies of multiple chips on a force computing board according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a chip frequency sweeping apparatus according to an embodiment of the present application;

FIG. 6 is a schematic diagram of operating frequencies of N groups of chips according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a chip frequency sweeping apparatus according to another embodiment of the present application;

FIG. 8 is a schematic flow chart diagram of a method for frequency sweeping a chip according to another embodiment of the present application;

FIG. 9 is a schematic flow chart diagram of a method for sweeping a chip according to another embodiment of the present application;

FIG. 10 is a schematic flow chart diagram of a method for frequency sweeping a chip according to another embodiment of the present application;

FIG. 11 is a schematic flow chart diagram of a method for sweeping a chip according to another embodiment of the present application;

FIG. 12 is a schematic flow chart diagram of a method for frequency sweeping a chip according to another embodiment of the present application;

FIG. 13 is a schematic flow chart diagram of a method for frequency sweeping a chip according to another embodiment of the present application;

fig. 14 is a schematic structural diagram of a chip frequency sweeping apparatus according to another embodiment of the present application;

fig. 15 is a schematic structural diagram of a chip frequency sweeping apparatus according to another embodiment of the present application;

fig. 16 is a schematic structural diagram of a chip frequency sweeping apparatus according to another embodiment of the present application;

FIG. 17 is a schematic block diagram of a processing apparatus according to an embodiment of the present application;

fig. 18 is a schematic configuration diagram of a processing apparatus according to another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

It should be understood that the specific examples are provided herein only to assist those skilled in the art in better understanding the embodiments of the present application and are not intended to limit the scope of the embodiments of the present application.

It should also be understood that, in the various embodiments of the present application, the sequence numbers of the processes do not mean the execution sequence, and the execution sequence of the processes should be determined by the functions and the inherent logic of the processes, and should not constitute any limitation to the implementation process of the embodiments of the present application.

It should also be understood that the various embodiments described in this specification can be implemented individually or in combination, and the examples in this application are not limited thereto.

Unless otherwise defined, all technical and scientific terms used in the examples of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

First, a logical structure diagram of an electronic device capable of executing the embodiment of the present application is described. The electronic device may be a processing device of a digital certificate, or may be other electronic devices for performing operation processing on a dedicated service, for example, a computing server, a communication device, a high-performance personal computer, and the like, which is not limited in this embodiment of the present application.

As shown in fig. 1, the electronic device 10 may include a power module 110, a processing module 120, a control module 130, a storage module 140, an interface module 150, and a heat dissipation module 160. It should be understood that the components of electronic device 10 may have fewer or more components than shown, or a different configuration of components. The various components shown in fig. 1 may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and/or application specific integrated circuits.

The power module 110 is used for providing power to other modules in the electronic device 10, and may include an AC-to-DC converter (AC-to-DC converter), a DC-to-DC converter (DC-to-DC converter), and a Low Dropout Regulator (LDO) for outputting different DC voltages to meet voltage requirements of different chips and circuits.

The processing module 120 is a calculation processing module for dedicated calculation, which may include a plurality of chips for calculation. When the electronic module 10 is a processing device of a digital certificate, the processing module 120 may include one or more computation boards (also referred to as computation boards), and a plurality of chips (chips), also referred to as Integrated Circuits (ICs), arranged in an array on the one or more computation boards for performing hash operation to solve the hash value, thereby obtaining the digital certificate.

In the processing module 120, data lines of a plurality of chips are connected in series, data obtained by operations of the plurality of chips are transmitted to the control module 130 through the data lines, in other words, data obtained by operations of the plurality of chips are transmitted to the control module 130 through one data transmission interface, and the operation data of the plurality of chips are sequentially transmitted to the control module 130 through the one data transmission interface, instead of the data lines of each chip being connected to the control module 130 and synchronously transmitted to the control module 130.

In addition, in the processing module 120, the plurality of chips are distributed over a plurality of voltage domains, which are connected in parallel, instead of being distributed over the same voltage domain. By adopting the design mode of the multiple voltage domains, chips on different voltage domains are not influenced mutually, and the working stability and reliability of the multiple chips are improved.

Optionally, the chip on the computing board may be any one of an Application Specific Integrated Circuit (ASIC) chip, a Graphics Processing Unit (GPU) chip, a Central Processing Unit (CPU) chip, and a Field Programmable Gate Array (FPGA) chip, which is not limited in this embodiment.

The control module 130 may be a System on a Chip (SOC) for connecting other modules in the electronic device 10 to ensure the orderly communication and data communication among the modules. The control module 130 may include a Microcontroller (MCU), a Microprocessor (Microprocessor), a Digital Signal Processor (DSP), an Analog-to-Digital converter (ADC), a Digital-to-Analog converter (DAC), an Oscillator (Electronic Oscillator) and a Phase Locked Loop (PLL) for providing a time pulse Signal, and the like.

The control module 130 may generate different clock signals through a clock circuit such as a phase-locked loop, so as to control the plurality of chips in the processing module 120 to operate at different operating frequencies. In addition, the control module 130 may also generate test data through circuits such as a microcontroller and a microprocessor, transmit the test data to a plurality of chips in the processing module 120, receive random data generated by the plurality of chips, and process the random data. In other words, the control module 130 may be used to control the operation of the plurality of chips in the processing module 120 and receive and process data of the plurality of chips.

In addition, the control module 130 may be connected to an external network through a network port, and the control module 130 may be configured through the network port, so as to control the operation of the electronic device 10.

The memory module 140 may include one or more Double Data Rate synchronous dynamic random access memory (DDR SDRAM), flash memory (flash), etc. memory units for storing Data and software programs in operation. Wherein the software program is used to control the operation of the hardware modules in the electronic device 10.

In particular, the software programs in the storage module 140 include an Operating System (OS) for controlling and managing conventional System tasks such as memory management, storage control, and power management, among others, as well as various software components and/or drivers that facilitate communication between various software and hardware, as well as a set of communication instructions, among others. The operating system includes but is not limited to: and embedded operating systems such as Linux, Unix, Windows or Vxworks and the like. The communication instruction set includes software components for processing data received via the interface module 150 to facilitate communication with other devices via the interface module.

The Interface module 150 may include various connection interfaces, such as Universal Serial Bus (USB), Ethernet (ETH), Universal Asynchronous Receiver/Transmitter (uart), Serial Peripheral Interface (SPI), and the like, for connecting various external devices directly or via a network.

In addition, the electronic device 10 further includes a heat dissipation module 160, and the heat dissipation module 160 may be a Fan (Fan), a water cooling system or other devices for dissipating heat from the electronic device 10. The power module 110 is used for supplying power to the heat dissipation module 160, and the control module 130 is used for controlling the heat dissipation module 160 to operate.

In the electronic device 10, the processing speed and the processing capability of the computing task depend on the processing module 120. In particular, in a digital certificate processing device, the system performance of the device depends for the most part on the computing power of the computing board, i.e., the speed at which the computing board computes the hash function output. The computing power of the computing power board is determined by the computing power of a plurality of chips on the computing power board, and the computing power of each chip on the computing power board influences the overall system performance of the equipment. In addition, the calculation power of the chip is closely related to the working frequency of the chip, and the higher the working frequency is, the more times are calculated per second, and the stronger the calculation power of the chip is.

In general, the frequency of operation of a plurality of chips on an algorithm board can be obtained through frequency sweep test. Due to different factors such as manufacturers and manufacturing processes of a plurality of chips, the performance of different chips may be different, that is, the highest operating frequency of different chips is different, and when a chip operates at a frequency exceeding the highest operating frequency, the chip may be abnormal. In the prior art, all chips on a force calculation plate are subjected to unified frequency sweep test, and all chips work under the same working frequency.

Fig. 2 shows a conventional chip sweep apparatus, and as shown in fig. 2, the chip sweep apparatus 200 includes a controller 210, a force computation board 220, and a power supply 230. The computation board 220 is provided with a plurality of chips IC, and the computation board 220 may be one example of the processing module 120, or may be another electrical component that carries a plurality of chips and provides electrical connection for the plurality of chips. The controller 210, which may be one example of the control module 130, is a system chip of the frequency sweeping device 200, or other electrical components with control functions, and may control operations of a plurality of chips on the force computing board 220. The power supply 230 is used to supply power to the electrical devices on the chip sweep apparatus 200, and may be one of the power supply modules described above.

As shown in fig. 2, a plurality of chips are arranged in an X-row Y-column array on an algorithm board 220. Optionally, in one embodiment, Y chips are located in one voltage domain per row, and X voltage domains are distributed on the computing board 220 in X rows, where X and Y are positive integers greater than 1.

Specifically, Y chips in one voltage domain are connected in parallel to supply power by using one voltage domain, and chips in different voltage domains are supplied by using different voltage domains, in other words, chip voltages in different voltage domains do not affect each other, but chip voltages in the same voltage domain affect each other.

Optionally, the voltages of the X voltage domains may be the same or different, and controlling multiple chips by different voltage domains can improve the stability of the force computing board 220, so that the power supply voltage of the entire force computing board is uniform.

In addition, the data lines of the Y chips on one voltage domain are connected in series for transmitting data signals. And the head chip and the tail chip on one voltage domain are respectively connected with the chips on the adjacent voltage domains to transmit data signals. For example, as shown in FIG. 2, the first chip IC of the second row_2,1With the first chip, i.e. IC, of the next row_3,1Connecting the last chip IC of the second row_2,YWith the last chip, i.e. IC, of the previous row_1,YAnd (4) connecting.

When Y chips in a voltage domain are connected in parallel and powered by the same voltage source, if one of the chips has poor performance, the highest operating frequency of the chip is low, and if the controller 210 operates at a frequency higher than the highest operating frequency, the chip is abnormal, and the power supply voltage of the whole voltage domain may be reduced, so that all other chips in the voltage domain cannot operate normally.

For the chip frequency sweeping device 200, the embodiment of the present application provides a chip frequency sweeping method 20, which sweeps to obtain the operating frequencies of a plurality of chips on the force calculation board 220. Alternatively, the execution subject of the frequency sweeping method 20 may be the controller 210 described above.

Fig. 3 shows a flow chart of the chip sweep method 20.

S210: setting the frequencies of a plurality of chips on the force calculation plate as an ith test frequency F_i。

Specifically, the controller sets the test working frequency of a plurality of chips on the force calculation board to the ith test frequency F_iThe ith test frequency F_iFor W test frequencies F₁～F_wAnd in the ith test, the W test frequencies are sequentially increased from small to large, W is a positive integer larger than 1, i is larger than or equal to 1 and is less than or equal to W, and i is a positive integer.

S220: test data (pattern) is sent to the plurality of chips.

Specifically, the controller sends one or more test data to a plurality of chips, each of the plurality of chips receives the same one or more test data and performs an operation on the one or more test data, and in the process, the plurality of chips send the result of the operation to the controller 210, wherein the operation result may be a random number (nonce) generated by the chip for the one or more test data or operation data such as a hash value, and the random number is a random number of a random number in the hash operation and ranges from 0 to 2³²And other numerical ranges, which are not limited by the embodiments of the present application. And performing multiple Hash operations on the test data to obtain multiple random numbers, wherein the larger the number of the random numbers generated in unit time is, the stronger the computing power of the chip is, namely, the higher the computing power of the computing power board is.

S230: and receiving and judging whether the number of the random numbers generated by the plurality of chips is within a threshold value range.

Specifically, when the chip works normally, the number of random numbers generated in the working process of the chip is relatively large in a unit time, and when the chip works abnormally, the number of random numbers generated in the calculating process of the chip is relatively small in the unit time. Therefore, a threshold range can be set for the whole of the plurality of chips, and when the number of random numbers generated by the plurality of chips is within the threshold range, the calculation power of the plurality of chips at this time can meet the requirement. Alternatively, a threshold range may be set for each of the plurality of chips, and it may be determined whether the number of random numbers generated by each chip is within the threshold range, and if the number of random numbers is within the threshold range, it may indicate that the chip is operating normally, and if the number of random numbers is outside the threshold range, it may indicate that the chip is operating abnormally.

In addition, the random numbers generated by the plurality of chips are transmitted to the controller through the data lines connected in series, the controller receives the number of the random numbers output by each chip in the plurality of chips, and the number of the random numbers output by each chip in the plurality of chips can be judged whether to be within the threshold range or not.

S241: if the number of the random numbers is within the threshold range, adding 1 to i, and adopting the (i + 1) th test frequency F_i+1And carrying out frequency sweep test on a plurality of chips on the force calculation plate.

Specifically, when the number of random numbers output by each of the plurality of chips is within a threshold range, each chip works normally, or when the number of random numbers output by the whole plurality of chips is within the threshold range, the computing power of the computing board meets the requirement, and at this time, the controller sets the test working frequency of the plurality of chips on the computing board to be the (i + 1) th test frequency F_i+1The i +1 th test frequency F_i+1＞F_iUsing the i +1 th test frequency F_i+1The sweep test is performed on a plurality of chips on the force calculation board, and the process may refer to steps S210 to S230. .

S242: if the number of the random numbers is out of the threshold range, determining the working frequency of the chips as the i-1 test frequency F_i-1。

Specifically, when the number of random numbers output by any one of the plurality of chips is out of the threshold range or the number of random numbers output by the whole plurality of chips is out of the threshold range, ending the frequency sweep test, and determining the working frequency of the plurality of chips on the force computing board as the i-1 test frequency F_i-1. That is, after the sweep test is finished, in the normal working process of the chips on the force calculation board, the working frequency of the chips is F_i-1。

It should be understood that, regarding the arrangement of the voltage domains on the force computing board 220 in fig. 2, in another embodiment, each column of X chips may be located on one voltage domain, and Y voltage domains are longitudinally distributed on the force computing board 220. The frequency sweep method 20 described above is also applicable to the force calculation board in this embodiment, and will not be described here.

Because a plurality of chips in the same voltage domain on the computation board use one voltage source in parallel, if only one chip is abnormal in the same voltage domain, all the chips in the voltage domain may work abnormally, which causes a large influence. Therefore, during the frequency sweep, if the frequency F is tested_iIf the frequency of a chip exceeds the highest frequency of the chip, all chips in a voltage domain where the abnormal chip is located may be abnormal, the number of random numbers generated by the chips in the voltage domain is reduced, and at this time, the random numbers of the whole plurality of chips may not reach the threshold range; or, during the frequency sweep, only one chip is at the test frequency F_iThe lower working is abnormal, the random number is not in the threshold range, and the working frequency of all chips on the force calculation board is less than the test frequency F_i。

FIG. 4 shows a schematic diagram of the operating frequency of multiple chips on an exemplary computing force board.

As shown in FIG. 4, the computing board has 6 rows and 10 columns of chips, wherein the chip IC of the 2 nd row and the 3 rd column_2,3When a multi-chip on the force computing board is subjected to frequency sweep test for a chip with poor performance on the force computing board, an IC_2,3Working abnormity at the test frequency of more than 250MHz, and then obtaining the working frequency of 60 chips on the force calculation plate according to the frequency sweep method 20Are all 250 MHz.

In summary, when the controller 210 performs the frequency sweep test on the plurality of chips on the computation force plate 220 by using the frequency sweep method 20, the finally determined unified operating frequency of the plurality of chips is the normal operating frequency of the worst-performance chip among the plurality of chips, and none of the other chips reaches the highest operating frequency of itself, that is, the optimal operating state is not reached. In other words, a chip with poor performance may form a barrel effect, so that the frequency sweeping method 20 cannot be used to determine the highest operating frequency of each chip on the force computing board, so that the force computing board reaches an optimal operating state, thereby affecting the performance of the entire system.

Based on this, the embodiment of the application provides a frequency sweeping method and a frequency sweeping device for chips, by grouping a plurality of chips and respectively performing frequency sweeping tests, the influence of the chips with poor performance on other chips is reduced, the chips are prevented from generating a barrel effect, the working frequency of the chips is improved, and the computing power and the system performance of the chips are improved.

Fig. 5 shows a schematic diagram of a chip frequency sweeping apparatus provided in an embodiment of the present application.

As shown in fig. 5, the chip sweep apparatus 300 includes:

n groups of chips 320 disposed on the circuit board, wherein each group of chips in the N groups of chips 320 includes at least one chip, and N is a positive integer greater than 1;

and a controller 310 connected to the N groups of chips 320, for sequentially performing a frequency sweep test on the N groups of chips 320, and determining an operating frequency of each group of chips in the N groups of chips 320.

Optionally, in this embodiment of the present application, the chips in the N groups of chips 320 may be the same as the chips in the processing module 120 in fig. 1, and may be any one of an ASIC chip, a GPU chip, a CPU chip, or an FPGA chip, and configured to perform data operation to implement various types of task data processing, such as various types of data processing of audio, video, image, signal, and digital.

Optionally, the data lines of a plurality of the N groups of chips 320 are connected in series to transmit data signals.

Alternatively, as shown in fig. 5, the N groups of chips 320 may be arranged longitudinally in N rows on the circuit board, and the N groups of chip ICs₁～IC_NAs indicated by the dashed box in fig. 5. Or may be arranged on the circuit board in N rows and laterally, which is not limited in the embodiments of the present application. Hereinafter, the N groups of chips 320 are illustrated as being arranged in N rows in a longitudinal direction, and the technical solutions related to the transverse arrangement mode may refer to the longitudinal arrangement mode, which is not described herein again.

In the embodiment of the present application, the circuit board is used for carrying the N groups of chips 320 and electrically connecting the N groups of chips 320.

It should be understood that the Circuit Board includes, but is not limited to, a Printed Circuit Board (PCB), a Flexible Printed Circuit Board (PFC), or a software integration Board (Soft and hard combination Board), which is not limited in the embodiments of the present application.

It should also be understood that, in the processing device of the digital certificate, the combination of the circuit board and the N groups of chips may also be referred to as an algorithm board, and the circuit board and the N groups of chips in the embodiment of the present application are not limited to the algorithm board in the processing device of the digital certificate, but may be a circuit board and N groups of chips in any scene, which is not limited in the embodiment of the present application.

Alternatively, the controller 310 may be one example of the control module 130 in fig. 1, a system chip of the frequency sweeping device 300, or other electrical components with control functions, and may control the N groups of chips 320 to operate.

Specifically, in this embodiment of the present application, when each group of chips in the N groups of chips 320 includes one chip, the controller 310 may be configured to perform a frequency sweep test on each chip to obtain an operating frequency of each chip, respectively, when each group of chips in the N groups of chips 320 includes a plurality of chips, the controller 310 may be configured to perform a frequency sweep test on the plurality of chips, and determine an operating frequency for the plurality of chips in the same group, and the plurality of chips in the same group may be located in the same voltage domain, or located in a plurality of different voltage domains, or partially located in the same voltage domain, and partially located in different voltage domains, which is not limited in this embodiment of the present application.

In other words, the controller 310 does not perform frequency sweep test on all the chips in the N groups of chips 320 at the same time to obtain the uniform operating frequency of all the chips, but performs frequency sweep test on the N groups of chips in sequence to obtain the operating frequency of each group of chips, respectively, the operating frequency of each group of chips may be the same or different, and the frequency sweep process of each group of chips is not affected by other groups of chips, so that the frequency sweep test of the chip with poor performance in the N groups of chips does not affect the frequency sweep test of other chips, in other words, when performing frequency sweep test on other chips, the operating frequency obtained by the frequency sweep test of other chips is not lower due to the influence of the chip with poor performance, and the performance of the entire N groups of chips and the chip frequency sweep apparatus is not affected.

Fig. 6 shows a schematic diagram of the operating frequency of an example of N groups of chips.

As shown in fig. 6, the N groups of chips are arranged in 6 rows and 10 columns, each column of chips is a group, and each group of chips comprises 10 groups of chips, wherein the chip IC in the 2 nd row and the 3 rd column_2,3When the N groups of chips are subjected to frequency sweep test in sequence, the IC is used for the chips with poor performance in the N groups of chips_2,3Operating abnormally at test frequencies in excess of 250MHz, at which time the IC is determined_2,3The third group of chips IC₃The working frequency of the multi-chip is 250MHz without influencing the working frequencies of other groups of chips, and the working frequencies determined by other groups are higher than 250MHz, so that compared with the working frequencies of the multi-chip in FIG. 4, the working frequency of the multi-chip determined by the embodiment of the application is higher, and the working performance of the multi-chip can be optimized.

Optionally, in a possible embodiment, there is only one voltage domain on the circuit board, and at least one chip in the N groups of chips is located on the same voltage domain.

Optionally, in another possible embodiment, there are M voltage domains on the circuit board, and N groups of chips are located on the M voltage domains, where M is a positive integer greater than 1.

For the embodiment of M voltage domains on the circuit board, there are various relative position relationships between the N groups of chips and the M voltage domains, which will be described in the following cases.

First case

Fig. 7 shows the arrangement and positional relationship of the N groups of chips and the M voltage domains in the first case, and M, N is a positive integer greater than 1.

As shown in FIG. 7, N sets of chip ICs₁～IC_NArranged in N rows and M voltage domains V₁～V_MAre arranged in M rows transversely. Specifically, each of the N groups of chips includes M chips, and the M chips are respectively located on M voltage domains. And each voltage domain in the M voltage domains is respectively provided with N chips, and the N chips respectively belong to different groups of chips. In other words, in the first case, different chips in each of the N groups of chips are respectively located on different voltage domains.

Similar to fig. 2, N chips located in the same voltage domain are connected in parallel and powered by the same power supply, and data lines of the N chips are connected in series to transmit data signals.

In this case, the controller 310 may perform the frequency sweep test on the N groups of chips in sequence by using the chip frequency sweep method 30, and in this process, the chips in the same voltage domain on the circuit board are not subjected to the frequency sweep test at the same time, so that the influence of the chips with poor performance in the same voltage domain on other chips in the voltage domain may be avoided.

Optionally, fig. 8 shows a schematic flow chart diagram of a chip frequency sweeping method 30.

S310: and sequentially carrying out frequency sweep test on the N groups of chips, wherein N is a positive integer greater than 1.

Optionally, in the frequency sweeping apparatus 300 shown in fig. 7, each group of chips includes M chips, where the M chips are respectively located in the M voltage domains, and M is a positive integer greater than 1.

S320: and determining the working frequency of each group of chips in the N groups of chips.

Optionally, in the process of sequentially performing the frequency sweep test on each group of chips in the N groups of chips, the frequency sweep test may be performed on the N groups of chips in any order, for example, the frequency sweep test is performed on the even groups of chips sequentially, and then the frequency sweep test is performed on the odd groups of chips sequentially. Or any other sequence, the frequency sweep test of each group of chips in the N groups of chips is completed in sequence, and the specific frequency sweep test sequence is not specifically limited in the embodiment of the application.

Optionally, in the process of sequentially performing the frequency sweep test on each group of chips in the N groups of chips according to the position order, the a-th group of chip ICs in the N groups of chips_aAfter the sweep frequency test is finished, determining the working frequency of the a group of chips, and then carrying out IC test on the a +1 group of chips_a+1Or a-1 th group chip IC_a-1And performing frequency sweep test to determine the working frequency of the a +1 th group of chips or the a-1 th group of chips. Wherein a is more than or equal to 1 and less than or equal to N, and a is a positive integer.

Optionally, the frequency sweep test may be performed from a first group of chips in the N groups of chips until the frequency sweep test on the nth group of chips is completed, or the frequency sweep test may be performed from the nth group of chips in the N groups of chips until the frequency sweep test on the first group of chips is completed; the frequency sweep test may also be performed from any one of the N groups of chips, for example, the frequency sweep test is performed from the a-th group of chips, and after the frequency sweep test is completed on the N-th group of chips, the frequency sweep test is performed on the first group of chips until the frequency sweep test on the a-1-th group of chips is completed.

Optionally, in one possible implementation, X test frequencies F are used for each of the N groups of chips₁，F₂，……，F_XAnd performing frequency sweep test, wherein the X test frequencies are sequentially increased, and X is a positive integer greater than 1.

It should be noted here that the first test frequency F of the X test frequencies₁Lower, each chip in the N groups of chips is at the first test frequency F₁All work normally under the condition.

In the embodiment of the present application, a process of performing a frequency sweep test on any one of the N groups of chips, for example, the kth group of chips, is described in detail with reference to fig. 9 to 11, where k is greater than or equal to 1 and less than or equal to N, and k is a positive integer.

Fig. 9 shows a schematic flow diagram of a chip sweep method 30.

S311: setting the test frequency of the kth group of chips to be XThe ith of the test frequencies F_iWherein i is more than or equal to 2 and less than or equal to X, and i is a positive integer.

Specifically, the controller 310 controls the operation frequency of the kth chip group to be the ith test frequency F_i. Optionally, a controller 310 is connected to the clock line of each chip in the kth group of chips, the controller 310 generating the test frequency F with the ith frequency_iClock signal CLK_iAnd the clock signal CLK is transmitted via a clock line_iThe clock signals of each chip in the kth group of chips are CLK_i。

S312: and sending test data to the kth group of chips.

All chips in the k group work at a clock signal CLK_iThe controller 310 then sends the same test data to each chip in the kth group of chips. Specifically, after the controller 310 generates the test data, the test data is transmitted to each chip of the kth group of chips through the input signal line. After each chip receives the test data, it will generate several random numbers and other operation data.

Optionally, the test data and the random number in this step are the same as the test data and the random number described in step S220 in fig. 3, and related features may refer to the above description, which is not repeated herein.

S321: acquiring and judging whether the number of the random numbers of the kth group of chips is within a threshold range; the random number is generated after the kth group of chips receive the test data.

Specifically, the random number or other operation data generated by each chip may be transmitted to the controller 310 through an output signal line, and the controller 310 receives the random number or other operation data and determines whether the random number or other operation data is within a threshold range.

Alternatively, it may be determined whether the sum of the random number numbers of all chips in the kth group of chips is within a threshold range.

Optionally, it may also be determined whether the number of random numbers of each chip in the kth group of chips is within a threshold range.

S322: and determining the working frequency of the kth group of chips according to the judgment result.

Specifically, the operating frequency of the kth group of chips is determined based on the above-described result of determining whether the number of random numbers or other operation data is within the threshold range.

Optionally, the sweep test is performed on the kth group of chips according to the arrangement sequence of the X test frequencies. After the frequency sweep test is performed on the kth group of chips by using the ith test frequency, the frequency sweep test is performed on the kth group of chips by using the test frequency greater than the ith test frequency, for example, the (i + 1) th test frequency.

Fig. 10 shows a schematic flow diagram of a specific chip sweep method 30.

As shown in fig. 10, in the chip sweep method 30, the steps S321 and S322 may specifically include the following steps.

S3210: and acquiring the number of random numbers of the kth group of chips.

Optionally, the number of random numbers of each chip of the kth group of chips is obtained.

Specifically, the controller 310 receives each chip of the kth group of chips at the ith test frequency F_iAnd (4) generating random numbers, and acquiring the number of the random numbers of each chip in the kth group of chips.

S3211: judging whether the number of the random numbers of each chip in the kth group of chips is within a first threshold range and i +1 is less than or equal to X;

s3221: and performing frequency sweep test on the kth group of chips by using the (i + 1) th test frequency in the X test frequencies.

S3212: judging whether the number of the random numbers of each chip in the kth group of chips is within a first threshold range and when i +1 is larger than X;

s3222: and determining the working frequency of the kth group of chips as the Xth test frequency in the X test frequencies.

S3213: judging whether the number of the random numbers of at least one chip in the kth group of chips is out of a first threshold range;

s3223: and determining the working frequency of the kth group of chips as the (i-1) th test frequency in the X test frequencies.

Specifically, the ith test frequency F of each chip in the kth group of chips is obtained_iAnd judging the number of the random numbers of each chip after the number of the random numbers. For example, in the chip sweep apparatus 300 shown in fig. 5, each group of chips includes M chips, that is, in the embodiment of the present application, the kth group of chips includes M chips, and the number of random numbers of each chip in the M chips is determined.

When the number of the random numbers of each chip in the kth group of chips is within a first threshold range, it is indicated that each chip in the kth group of chips works normally under the ith test frequency, and each chip works normally under the ith test frequency F_iThe calculated force reaches the preset calculated force requirement, in other words, the ith test frequency F_iThe working frequency required by the k group of chips is preset.

In this case, when i +1 ≦ X, i.e., the i +1 th test frequency is the last test frequency F_XOr has not yet reached F_XAnd in the process, the frequency sweep test can be carried out on the kth group of chips by adopting the (i + 1) th test frequency, and whether the (i + 1) th test frequency is the working frequency meeting the preset requirement is tested.

Similarly, when the (i + 1) th test frequency meets the preset requirement, the frequency sweep test is continuously carried out on the kth group of chips by adopting the (i + 2) th test frequency, and the frequency sweep test is sequentially carried out until the Xth test frequency F of the last test frequency is adopted_XAnd carrying out frequency sweep test on the kth group of chips. The subsequent method for performing frequency sweep test on the kth group of chips by using the (i + 1) th test frequency or even the xth test frequency is the same as the frequency sweep method 30, and is not described herein again.

Particularly, when the ith test frequency is the xth test frequency of the last test frequency, i.e. i +1 > X, the frequency sweep test is ended, and the working frequency of the kth group of chips is determined as the xth test frequency.

The above describes the case where the number of random numbers of each chip in the kth group of chips is within the first threshold range, as opposed to the case where the number of random numbers of at least one chip in the kth group of chips is outside the first threshold range, the kth group of chips is described as being up to the first threshold rangeAt least one chip works abnormally at the ith test frequency, and the ith test frequency can not enable each chip in the kth group of chips to work normally, in other words, the ith test frequency F_iThe operating frequency is not preset to meet the k-th set of chips.

In the embodiment of the application, the i-1 st test frequency F is determined_i-1On the basis of meeting the preset working frequency required by the kth group of chips, adopting the ith test frequency F_iPerforming frequency sweep test, when the ith test frequency F_iAnd when the preset requirement of the kth group of chips is not met and the i-1 st test frequency meets the preset requirement of the kth group of chips, determining the working frequency of the kth group of chips as the i-1 st test frequency.

Fig. 11 shows a schematic flow diagram of another specific chip sweep method 30.

As shown in fig. 11, in the chip sweep method 30, the steps S321 and S322 may specifically include the following steps.

S3210: and acquiring the number of random numbers of the kth group of chips.

Optionally, the sum of the numbers of random numbers of all chips of the kth group of chips is obtained.

S3214: judging whether the sum of the number of the random numbers of all the chips in the kth group of chips is within a second threshold range and when i +1 is less than or equal to X;

s3221: and performing frequency sweep test on the kth group of chips by using the (i + 1) th test frequency in the X test frequencies.

S3215: judging whether the sum of the number of the random numbers of all chips in the kth group of chips is within a second threshold value range, and if i +1 is larger than X;

s3222: and determining the working frequency of the kth group of chips as the Xth test frequency in the X test frequencies.

S3216: judging whether the sum of the number of the random numbers of all the chips in the kth group of chips is out of the range of a second threshold value;

s3223: and determining the working frequency of the kth group of chips as the (i-1) th test frequency in the X test frequencies.

Specifically, in the embodiment of the present application, each chip in the kth group of chips is obtained at the kthi test frequencies F_iAnd after the number of the random numbers, summing the number of the random numbers of all the chips in the kth group of chips, and judging the sum of the number of the random numbers. For example, in the chip sweep apparatus 300 shown in fig. 5, each group of chips includes M chips, that is, in the embodiment of the present application, the kth group of chips includes M chips, and the sum of the numbers of the random numbers of the M chips is determined.

When the sum of the numbers of the random numbers of all the chips in the kth group of chips is within a second threshold value range, the kth group of chips is indicated to be at the ith test frequency F_iThe calculated force reaches the preset calculated force requirement, in other words, the ith test frequency F_iThe working frequency required by the k group of chips is preset.

In this case, when i +1 ≦ X, i.e., the i +1 th test frequency is the last test frequency F_XOr has not yet reached F_XAnd in the process, the frequency sweep test can be carried out on the kth group of chips by adopting the (i + 1) th test frequency, and whether the (i + 1) th test frequency is the working frequency meeting the preset requirement is tested.

Particularly, when the ith test frequency is the xth test frequency of the last test frequency, i.e. i +1 > X, the frequency sweep test is ended, and the working frequency of the kth group of chips is determined as the xth test frequency.

In contrast, when the sum of the random numbers of all chips in the kth group of chips is out of the second threshold range, the kth group of chips is indicated to be at the ith test frequency F_iThe lower calculation power does not reach the preset calculation power requirement, in other words, the ith test frequency F_iThe operating frequency is not preset to meet the k-th set of chips. When the ith test frequency F_iAnd when the working frequency is not the working frequency meeting the preset requirement, determining the working frequency of the kth group of chips as the (i-1) th test frequency.

It should be appreciated that in the sweep method 30 of the present application, the sweep test may be performed from a second test frequency F during the sweep test of the k-sets of chips₂The frequency sweep test may be started, or the test may be started from any test frequency after the second test frequency, which is not limited in this application embodiment。

Optionally, in the frequency sweep method 30, when performing the frequency sweep test on the kth group of chips in the N groups of chips, the test frequencies of the other groups of chips except the kth group of chips in the N groups of chips are set to be the same frequency.

Optionally, the test frequency of the other group of chips is set to the first test frequency F in the X test frequencies₁Since each chip in the N groups of chips is at the test frequency F₁Therefore, under the condition of ensuring the normal work of the N groups of chips, the frequency sweep test is carried out on the kth group of chips in the Nth group of chips, and the test result is more accurate.

Optionally, in another possible implementation, Y test frequencies F are used for each of the N groups of chips₁，F₂，……，F_YAnd carrying out frequency sweep test, wherein the Y test frequencies are sequentially decreased, and Y is a positive integer greater than 1.

It should be noted here that the Y-th test frequency F of the Y test frequencies_YLower, each chip in the N groups of chips is at the Yth test frequency F_YAll work normally under the condition.

In the embodiment of the present application, a process of performing a frequency sweep test on any one of N groups of chips, for example, a kth group of chips, is described in detail with reference to fig. 12 and 13, where k is greater than or equal to 1 and less than or equal to N, and k is a positive integer, and N is a positive integer greater than 1.

Fig. 12 shows a schematic flow diagram of a chip frequency sweeping method 40.

S411: setting the test frequency of the kth group of chips as the jth test frequency F in the Y test frequencies_jWherein j is more than or equal to 2 and less than or equal to Y, and j is a positive integer.

S412: and sending test data to the kth group of chips.

S421: acquiring and judging whether the number of the random numbers of the kth group of chips is within a threshold range; the random number is generated after the kth group of chips receive the test data.

Alternatively, it may be determined whether the sum of the random number numbers of all chips in the kth group of chips is within a threshold range. Optionally, it may also be determined whether the number of random numbers of each chip in the kth group of chips is within a threshold range.

S422: and determining the working frequency of the kth group of chips according to the judgment result.

Specifically, the operating frequency of the kth group of chips is determined based on the above-described result of determining whether the number of random numbers or other operation data is within the threshold range.

Optionally, steps S411 to S422 are similar to steps S311 to S322 in fig. 9, and the related schemes may refer to the above description, which is not repeated herein.

Optionally, the sweep test is performed on the kth group of chips according to the arrangement sequence of the Y test frequencies. After the jth test frequency is adopted to perform frequency sweep test on the kth group of chips, the test frequency lower than the jth test frequency, for example, the j +1 th test frequency, is adopted to perform frequency sweep test on the kth group of chips.

Fig. 13 shows a schematic flow diagram of a specific chip sweep method 40.

As shown in fig. 13, in the chip sweep method 40, the steps S421 and S422 may specifically include the following steps. :

s4210: and acquiring the number of random numbers of the kth group of chips.

Optionally, the number of random numbers of each chip of the kth group of chips is obtained.

Specifically, the controller 310 receives each chip of the kth group of chips at the jth test frequency F_jAnd (4) generating random numbers, and acquiring the number of the random numbers of each chip in the kth group of chips.

S4211: judging that the number of the random numbers of each chip in the kth group of chips is within a first threshold range;

s4221: and determining the working frequency of the kth group of chips as the jth test frequency in the Y test frequencies.

S4212: judging whether the number of the random numbers of at least one chip in the kth group of chips is out of a first threshold range and j +1 is equal to Y;

s4222: and determining the working frequency of the kth group of chips as the Yth test frequency in the Y test frequencies.

S4213: judging whether the number of the random numbers of at least one chip in the kth group of chips is out of a first threshold range and j +1 is less than Y;

s4223: and performing frequency sweep test on the kth group of chips by adopting the j +1 th test frequency in the Y test frequencies.

Specifically, each chip in the kth group of chips is obtained at the jth test frequency F_jAnd judging the number of the random numbers of each chip after the number of the random numbers.

When the number of the random numbers of each chip in the kth group of chips is within a first threshold range, it is indicated that each chip in the kth group of chips works normally under the jth test frequency, and each chip works normally under the jth test frequency F_jThe lower calculation power reaches the preset calculation power requirement, in other words, the jth test frequency F_jThe working frequency required by the k group of chips is preset.

In contrast, when the number of the random numbers of at least one chip in the kth group of chips is out of the first threshold range, it indicates that the at least one chip is abnormally operated at the jth test frequency, which cannot enable each chip in the kth group of chips to normally operate, in other words, the jth test frequency F_jThe operating frequency is not preset to meet the k-th set of chips.

In this case, when j +1 < Y, i.e., the jth test frequency is greater than the Y-1 test frequency F_Y-1When testing the frequency, the frequency sweep test needs to be carried out on the kth group of chips by adopting the j +1 th test frequency, and whether the j +1 th test frequency is the working frequency meeting the preset requirement is tested.

Similarly, when the j +1 th test frequency can not meet the preset requirement, the frequency sweep test is continuously carried out on the kth group of chips by adopting the j +2 th test frequency, and the frequency sweep test is sequentially carried out until the Y-1 st test frequency F is adopted_Y-1And carrying out frequency sweep test on the kth group of chips. The subsequent frequency sweep test method for the kth chip set by using the (j + 1) th test frequency or even the (Y-1) th test frequency is the same as the frequency sweep method 40, and is not described herein again.

In particular, when the jth test frequency is the Y-1 test frequency F_Y-1When, i.e. when j +1 is Y, if F_Y-1The preset requirement can not be met, the sweep test is ended, and the working frequency of the kth group of chips is determined as the Yth test frequency F_Y。

In the embodiment of the application, the j-1 st test frequency F is determined_j-1On the basis of not meeting the preset requirement of the kth group of chips, adopting the jth test frequency F_jAnd carrying out frequency sweep test. When the j-1 th test frequency F_j-1Not meeting the preset requirements of the kth group of chips and the jth test frequency F_jWhen the preset requirement of the kth group of chips is met, determining the working frequency of the kth group of chips as the jth test frequency F_j。

It should be understood that, in the embodiment of the present application, in addition to determining the operating frequency of the kth group of chips by determining whether the random number of each chip in the kth group of chips is within the first threshold range, the operating frequency of the kth group of chips may also be determined by determining whether the sum of the numbers of random numbers of all chips in the kth group of chips is within the second threshold range.

Optionally, in the frequency sweep method 40, when performing the frequency sweep test on the kth group of chips in the N groups of chips, the test frequencies of the other groups of chips except the kth group of chips in the N groups of chips are set to be the same frequency.

Optionally, the test frequency of the other groups of chips is set to the Yth test frequency F in the Y test frequencies_YSince each chip in the N groups of chips is at the test frequency F_YTherefore, under the condition of ensuring the normal work of the N groups of chips, the frequency sweep test is carried out on the kth group of chips in the Nth group of chips, and the test result is more accurate.

It should be appreciated that in the sweep method 40 of the present application, the sweep test may be performed from a first test frequency F during the sweep test of the k-sets of chips₁The frequency sweep test is started, and the test may also be started from any one test frequency after the first test frequency, which is not limited in the embodiment of the present application.

It should also be understood that in the sweep frequency method 30 and the sweep frequency method 40 of the present application, the sweep frequency test of the kth group of chips in the N groups of chips is taken as an example for illustration. The frequency sweep test method for other groups of chips in the N groups of chips may be the same as or different from the frequency sweep test method for the kth group of chips, for example, the kth group of chips in the N groups of chips is frequency swept by using the frequency sweep method 30, and the (k + 1) th group of chips is frequency swept by using the frequency sweep method 40, which is not limited in the embodiment of the present application.

Second case

Fig. 14 and 15 show the arrangement and positional relationship of N groups of chips and M voltage domains in the second case, where M and N are positive integers greater than 1.

As shown in FIG. 14, N sets of chip ICs₁～IC_a×NArranged in a longitudinal direction of a x N rows, each of the N groups of chips comprises a rows of chips, a is an integer greater than 1, and M voltage domains V₁～V_MAre arranged in M rows transversely. Specifically, each of the N groups of chips includes a × M chips respectively located on M voltage domains, and a × N chips are disposed on each of the M voltage domains.

Optionally, each group of chips in the N groups of chips may be adjacent a-column chips, or may also be non-adjacent a-column chips, which is not limited in this embodiment of the application.

As shown in FIG. 15, N sets of chip ICs₁～IC_NArranged in N rows and M voltage domains V₁～V_b×MThe chips are transversely arranged in b multiplied by M rows, each voltage domain in the M voltage domains is provided with b rows of chips, and b is an integer larger than 1. Specifically, each of the N groups of chips includes b × M chips respectively located on M voltage domains, and b × N chips are disposed on each of the M voltage domains.

In other words, in the second case, some of the chips in each of the N groups of chips are located on the same voltage domain.

In this case, the controller 310 may still perform the frequency sweep test on the N groups of chips in sequence by using the above-mentioned chip frequency sweep method 30 or the chip frequency sweep method 40, during which, some chips on the same voltage domain on the circuit board are not scannedPerforming the sweep test simultaneously, for example, as shown in FIG. 14, when the sweep test is performed on the kth chip of N groups of chips, where k is greater than or equal to 1 and less than or equal to N, and k is a positive integer, the first chip IC in the kth chip_1,1And a second chip IC_1,2In a first voltage domain V₁Above, but in a first voltage domain V₁The other chips work normally and can not work for the first chip IC_1,1And a second chip IC_1,2The influence is caused, and similarly, chips other than the kth group of chips in other voltage domains do not influence the kth group of chips, so that the influence of the chips with poor performance in the same voltage domain on other chips in the voltage domain can be avoided to a certain extent by using the chip frequency sweeping method 30 or the chip frequency sweeping method 40.

In the embodiment of the present application, the chip frequency sweeping method 30 may refer to fig. 8 to 11 and the related steps described above, and the chip frequency sweeping method 40 may refer to fig. 12 and 13 and the related steps described above, which are not described again here.

It should be understood that, in the second case, the number of chips in each of the N groups of chips may be the same or different, and the embodiments of the present application are not particularly limited. For example, in FIG. 14, a first set of chip ICs₁Comprising 2 columns of chips, a second group of chip ICs₂May comprise 2 columns or more than 2 columns of chips, while in fig. 15 the first voltage domain V₁May comprise 2 rows of chips, and a second voltage domain V₂May include 2 rows or more than 2 rows of chips.

Alternatively, fig. 16 shows a schematic block diagram of another chip sweep apparatus 300.

As shown in fig. 16, the chip sweep apparatus 300 further includes:

and a memory 330, wherein the memory 330 is used for storing the operating frequency of each of the N groups of chips 320, and N is a positive integer greater than 1.

Specifically, the memory 330 may be an example of the storage module 140 in fig. 1.

Optionally, the memory 330 may be used to store computer-executable instructions. The controller 310 is used to access the memory 330 and execute the computer-executable instructions to perform the operations of the chip sweep method according to the embodiment of the present application.

Specifically, the controller 310 sequentially performs a frequency sweep test on the N groups of chips 320, determines the operating frequency of each group of chips, and then sends the operating frequency of each group of chips to the memory 330, and the memory 330 stores the operating frequency. After the sweep test is completed, the controller 310 may read the operating frequency of each of the N sets of chips 320 from the memory 330 and control the N sets of chips 320 to operate according to the operating frequency.

Alternatively, the memory 330 may be two devices independent from the controller 310, or may also be a storage unit in the controller 310, or may also be a storage unit disposed on a circuit board on which the N groups of chips 320 are disposed, which is not limited in this embodiment of the application.

As shown in fig. 16, the chip sweep apparatus 300 may further include:

and the power supply 340, wherein the power supply 340 is used for supplying power to the chip frequency sweeping device 300.

Specifically, the power supply 340 may power the controller 310, the N sets of chips 320, and the memory 330 for different devices and voltage requirements, N being a positive integer greater than 1. In other words, the power source 340 may include various voltage conversion circuits, such as AC/DC conversion circuits or DC/DC conversion circuits, etc., to generate multiple different voltages and connect to different devices and circuits on the chip sweep apparatus 300.

Alternatively, the power source 340 is a constant power module, which may be a constant dc or ac source module, and the controller 310, the circuit board where the N groups of chips 320 are located, and the memory 330 all include a voltage conversion circuit, which can convert the voltage of the power source 340 into a suitable device voltage to meet the operating requirement of the frequency sweeping apparatus 300.

It should be understood that the power source 340 may be a power source in the chip frequency sweeping device 300, or an external power source of the chip frequency sweeping device 300, which is not limited in this embodiment.

The embodiment of the application also provides electronic equipment, and the electronic equipment can comprise the device for sweeping the frequency of the chip in the various embodiments of the application.

The embodiment of the invention also provides a frequency sweeping device of the chip, which comprises a processor and a memory, wherein the memory is used for storing the program code, and the processor is used for calling the program code to execute the frequency sweeping method of the method embodiment.

Embodiments of the present invention also provide a computer storage medium having a computer program stored thereon, where the computer program, when executed by a computer, causes the computer to execute the method of the above method embodiments.

Embodiments of the present invention also provide a computer program product comprising instructions, which when executed by a computer, cause the computer to perform the method of the above method embodiments.

In addition to the above frequency sweeping device, frequency sweeping method and electronic device for chips, the present application also provides a processing device 400.

As shown in fig. 17, the processing apparatus 400 includes:

n groups of chips 420 disposed on the circuit board, wherein each of the N groups of chips 420 includes at least one chip, and N is a positive integer greater than 1;

the working frequency of each chip in each group of chips in the N groups of chips 420 is the same, and the working frequencies of at least two groups of chips in the N groups of chips 420 are different.

Optionally, in this embodiment of the application, the chips in the N groups of chips 420 may be the same as the N groups of chips 320 in fig. 5, 7, 14 to 16.

In one possible embodiment, the N groups of chips may be processor chips, such as any one of ASIC chips, GPU chips, CPU chips or FPGA chips, for performing data operations to implement various types of task data processing, such as audio, video, image, signal, digital and other different types of data processing. For example, when the processing device is a processing device of a digital certificate, the N groups of chips are processing chips of the digital certificate, and are used for performing hash operation to solve a hash value.

Through the scheme of the embodiment of the application, when the N groups of chips operate, the operating frequencies of the chips in different groups may be different, and therefore, all the chips in the N groups of chips are not limited to one operating frequency, so that the operating efficiency of the chips in different groups can be improved, and the processing performance of the processing device 400 can be improved.

Alternatively, in the embodiment of the present application, the arrangement of the N groups of chips 420 on the circuit board may be the same as the arrangement of the N groups of chips 320 on the circuit board, for example, as shown in fig. 17, the N groups of chips 420 may be arranged longitudinally in N rows on the circuit board, and the N groups of chip ICs₁～IC_NAs shown by the dashed box in fig. 17. Or arranged on the circuit board in N rows transversely.

Alternatively, the N groups of chips 420 may be two columns of chips as shown in fig. 15, or may be three columns or any other column. In addition, the N groups of chips 420 may be arranged on the circuit board in rows, with two rows of chips being a group.

It should be understood that, in addition, each of the N groups of chips 420 may not be arranged on the circuit board in rows and columns, for example, the first chip in the first row of chips, the second chip in the second row of chips, and so on, and the X-th chip in the X-th row of chips is the same group of chips. In the real-time application, the arrangement mode of the N groups of chips is not limited, and the number of the chips included in each group of chips is not limited.

In the embodiment of the present application, the circuit board is used for carrying the N sets of chips 420 and electrically connecting the N sets of chips 420.

It should be understood that, in the processing device of the digital certificate, the combination of the circuit board and the N groups of chips may also be referred to as an algorithm board, and the circuit board and the N groups of chips in the embodiment of the present application are not limited to the algorithm board in the processing device of the digital certificate, but may be a circuit board and N groups of chips in any scene, which is not limited in the embodiment of the present application.

Optionally, in this embodiment of the application, the N groups of chips 420 are located on a plurality of voltage domains, the plurality of voltage domains may be connected in parallel with each other, and the data lines of the N groups of chips 420 are connected in series.

For example, as shown in FIG. 17, IC_1,1And IC_1,2Are connected in series with the data lines of IC_1,2And IC_1,3The data lines are connected in series, and by analogy, each chip in the N groups of chips is connected in series in sequence according to the mode, and finally, data obtained by calculation of the N groups of chips is output through one data interface.

Optionally, as shown in fig. 17, the circuit board includes M voltage domains, and N groups of chips 420 are distributed on the M voltage domains, where M is a positive integer greater than 1. Optionally, the M voltage domains are connected in parallel to each other.

Optionally, a plurality of chips in one of the N sets of chips 420 are respectively located on the M voltage domains.

For example, as shown in FIG. 17, the first group of chips in the N groups of chips is an IC₁The chip comprises M chips, and the M chip bits are respectively positioned on M voltage domains.

Optionally, the first set of chip ICs₁It is also possible to include only M-1 chips, the M-1 chips being located on M-1 voltage domains, respectively. Optionally, the first set of chip ICs₁The M chips can also be distributed on M-1 voltage domains, wherein a first group of chip ICs are distributed on one voltage domain₁Two chips in (1).

Optionally, each of the N groups of chips 420 has the same number, and includes M chips, and the M chips are located in M voltage domains respectively. For example, N sets of chip ICs in FIG. 17₁To IC_NIn (1), the number of chips in each group of chips is equal.

Optionally, the sum of the operating frequencies of the chips on at least two of the M voltage domains is equal.

In one possible implementation, N chips are distributed on the first voltage domain and the second voltage domain of the M voltage domains, and the sum of the operating frequencies of the N chips on the first voltage domain is equal to the sum of the operating frequencies of the N chips on the second voltage domain.

Further, as shown in fig. 17, N groups of chips are arranged in N columns on the circuit board, and the chips in M voltage domains are arranged in M rows on the circuit board. N chips are distributed in each voltage domain of the M voltage domains, and the N chips in each voltage domain belong to N groups of chips respectively. Because the working frequency of each chip in each group of chips is the same, the sum of the working frequencies of the N chips in each voltage domain in the M voltage domains is equal.

Optionally, as shown in fig. 18, the processing device 400 may further include a controller 410. The controller 410 is used for controlling the N groups of chips 420 to operate at an operating frequency.

Alternatively, the controller 410 may be used to generate different frequencies and provide them to each of the N sets of chips 420.

Alternatively, the controller 410 may be an example of the control module 130 in fig. 1, and is a system chip of the processing device 400, or other electrical components with control functions, and controls the N groups of chips 420 to operate.

Optionally, in this embodiment of the present application, the controller 410 may also be configured to determine an operating frequency of each of the N groups of chips 420.

For example, the controller 410 is the same as the controller 310 in the foregoing embodiment, the controller 410 may be configured to perform a frequency sweep test on each chip to obtain an operating frequency of each chip, respectively, when each group of chips in the N groups of chips 420 includes a plurality of chips, the controller 410 may be configured to perform a frequency sweep test on the plurality of chips to determine an operating frequency for the plurality of chips in the same group, and the plurality of chips in the same group may be located in the same voltage domain, or located in a plurality of different voltage domains, or located in the same voltage domain partially and located in different voltage domains partially, which is not limited in this embodiment.

Specifically, for the process of the controller 410 performing frequency sweeping on the N sets of chips 420, reference may be made to the method of the controller 310 performing frequency sweeping on the N sets of chips 320 in the foregoing embodiment, which is not described herein again.

Optionally, as shown in fig. 18, the processing apparatus 400 may further include:

and the memory 430 is used for storing the operating frequency of each of the N groups of chips 420, wherein N is a positive integer greater than 1.

Specifically, the memory 430 may be an example of the storage module 140 in fig. 1.

Alternatively, the memory 430 may be two devices independent from the controller 410, or may also be a storage unit in the controller 410, or may also be a storage unit disposed on a circuit board on which the N groups of chips 420 are disposed, which is not limited in this embodiment of the application.

In a possible implementation manner, the controller 410 sequentially performs a frequency sweep test on the N groups of chips 420, determines an operating frequency of each group of chips, and then sends the operating frequency of each group of chips to the memory 430, where the memory 430 stores the operating frequency. After the sweep test is completed, the controller 410 may read the operating frequency of each of the N sets of chips 420 from the memory 430 and control the N sets of chips 420 to operate according to the operating frequency.

As shown in fig. 18, the processing apparatus 400 may further include:

a power supply 440, the power supply 440 configured to power the processing device 400.

The power supply 440 may be the same as the power supply 430 in fig. 16. The power supply may be a power supply in the processing device 400, or may be an external power supply of the processing device 400, which is not limited in the embodiment of the present application.

The embodiment of the present application further provides an electronic device, which may include the processing apparatus according to the various embodiments of the present application.

In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware or any other combination. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a Digital Video Disk (DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), among others.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.