阅读说明：本技术 一种高带宽低功耗的缓冲电路 (Buffer circuit with high bandwidth and low power consumption ) 是由 李荣宽 李思颖 于 2020-12-08 设计创作，主要内容包括：本发明公开了一种高带宽低功耗的缓冲电路,涉及集成电路领域。该缓冲电路采用左半平面零点与非主极点相抵消的方式降低功耗,使电路能在驱动非常大的电容负载时,允许一个常规放大器被一个小的反馈补偿电容C-C稳定。而小的反馈补偿电容能使GBW在不增加功耗的情况下变大,达到高带宽却低功耗的性能。(The invention discloses a buffer circuit with high bandwidth and low power consumption, and relates to the field of integrated circuits. The buffer circuit reduces power consumption by offsetting a left half-plane zero and a non-dominant pole, so that the circuit can allow a conventional amplifier to be compensated by a small feedback compensation capacitor C when a very large capacitive load is driven C And (4) stabilizing. And the small feedback compensation capacitor can make GBW bigger without increasing power consumption, and achieve the performance of high bandwidth but low power consumption.)

1. The buffer circuit with high bandwidth and low power consumption is characterized in that the buffer circuit structure with high bandwidth and low power consumption comprises voltage transconductance amplifiers G1, G2, G4,G5, G6 and G7, current transconductance G3, and input resistor R_cOutput resistor R₁、R₂、R₃Equivalent output capacitor C₁、C₂An output capacitor C_LAnd an internal compensation pole capacitor C_C(ii) a The first stage forward amplifier is composed of equivalent input resistors R of G1, G2, G3 and G3_cThe second stage forward amplifier is G4, and the third stage forward amplifier is G5; a first feed forward transconductance G6, a second feed forward transconductance G7; equivalent output resistance R of first-stage forward amplifier₁And an equivalent output capacitor C₁(ii) a Equivalent output resistance R of second stage forward amplifier₂And an equivalent output capacitor C₂(ii) a Equivalent output resistance R of third-stage forward amplifier₃And an output capacitor C_L(ii) a Internal compensation pole capacitor C_C；

The input V of the buffer circuit with high bandwidth and low power consumption_INConnected to the input terminals of the voltage transconductance amplifiers G1 and G2, the output terminal of the voltage transconductance amplifier G1 is connected to the input terminal of the current transconductance G3, the input terminals of the voltage transconductance amplifiers G6 and G7, and the capacitor C_cAnd a resistor R_cOne end of (a); resistance R_cThe other end of the first and second electrodes is grounded; the output of the current transconductance G3 is connected with the output of the voltage transconductance amplifier G2, the input of the voltage transconductance amplifier G4, and the resistor R₁One terminal of and a capacitor C₁One end of (a); resistance R₁Another terminal of (1) and a capacitor C₁The other end of the first and second electrodes is grounded; the output of the transconductance amplifier G4 is connected to the output of the transconductance amplifier G6, the input of the transconductance amplifier G5, and the resistor R₂One terminal of and a capacitor C₂One end of (a); resistance R₂Another terminal of (1) and a capacitor C₂The other end of the first and second electrodes is grounded; the output of the voltage transconductance amplifier G5 is connected with the output of the voltage transconductance amplifier G7 and the resistor R₃One terminal of (1), a capacitor C_LOne terminal of and a capacitor C_cThe other end of (a); resistance R₃Another terminal of (1) and a capacitor C_LThe other end of the first and second electrodes is grounded; the output of the voltage transconductance amplifier G5 is the output VOUT of the high-bandwidth low-power buffer circuit.

2. The high-bandwidth low-power buffer circuit according to claim 1, wherein the transfer function of the high-bandwidth low-power buffer circuit is:

the high-bandwidth low-power-consumption buffer circuit has three zero points z in total₁、z₂And z₃Four poles p₁、p₂、p₃And p₄(ii) a Wherein p is₂And p₃Is a conjugate complex pole, consisting of 1+ a₁s+a₂s²Obtaining a polynomial;

wherein:

A_DC＝g_m1g_m2g_m3R₁R₂R₃ (2)

wherein A is_DCDenotes the DC gain, g_m1Transconductance parameters, G, for transconductance amplifiers G1 and G2_m2G is a transconductance parameter corresponding to the transconductance amplifier G4_m3G is a transconductance parameter corresponding to the transconductance amplifier G5_mc1G is a transconductance parameter corresponding to the transconductance amplifier G3_mf1G is a transconductance parameter corresponding to the transconductance amplifier G6_mf2Is the transconductance parameter of the corresponding transconductance amplifier G7;

by applying a quadratic polynomial 1+ a₁s+a₂s²Analysis of natural frequency ω of_nAnd the quality factor Q is:

using first and second left half-plane zero points z₁And z₂To compensate for conjugate complex pole p₂And p₃Influence on closed loop stability; and, using the third left half-plane zero point z₃To further improve the phase margin and more specifically to theoretically obtain accurate phase compensation, by applying z₁And z₂Are respectively arranged at 2 omega_GBWAnd 3 omega_GBWFinish, form ω of the polynomial_nIs placed atTo ensure that the quadratic polynomial has no significant effect on the stability of the circuit, its Q value is set toFinally, C can be obtained_CAnd C_LThe relationship between them is:

as seen from the formula (13), C_CAnd C_LIs proportional to the square root of_m3>g_mc1，g_m2R₂Is a second stage gain>>1，C₁Parasitic capacitance is very small, so C_CMuch less than C_LThe high bandwidth low power consumption buffer circuit can use small current to achieve large bandwidth under super large capacitance load.

Technical Field

The invention relates to the field of integrated circuits, in particular to a buffer circuit with high bandwidth and low power consumption.

Background

In an integrated circuit, a bandgap reference voltage source can achieve extremely high temperature coefficient and power supply rejection ratio, and therefore, the bandgap reference voltage source is widely applied to various chips, such as LDO, DCDC, ADC, DAC and the like. The external large capacitor at the output end of the reference voltage source can stabilize the reference voltage, but in the application of the medium-high speed ADC, the external large capacitor and the parasitic inductance of the packaging line can generate resonance, and the capacity of the capacitor for stabilizing the reference voltage is seriously limited. In this case, it is necessary to generate a reference voltage on chip and add a buffer circuit (as shown in fig. 2) to provide a stable reference voltage, which requires a very high bandwidth and driving capability for the designed buffer circuit.

The prior art structure mainly utilizes the increase of the current of the buffer circuit (as shown in fig. 3) to realize the performance of high bandwidth, which inevitably results in the increase of power consumption. By the formula GBW ═ g_m1/C_m1It can be seen that in C_LWhen the ratio is determined to be larger, C is generally adopted to ensure the circuit to be stable_m1＝4g_m1·C_L/g_m3I.e. C_m1The ratio is large, and the bandwidth can be increased only by increasing g_m1(g_m1＝I_D1/(V_GS-V_T) That is to increase the current I flowing through G1_D1. Therefore, to achieve high bandwidth requires increased circuit power consumption.

Disclosure of Invention

In order to solve the above problems, the present invention provides a buffer circuit with high bandwidth and low power consumption. The buffer circuit structure with high bandwidth and low power consumption comprises voltage transconductance amplifiers G1, G2, G4, G5, G6 and G7, current transconductance G3 and an input resistor R_cOutput resistor R₁、R₂、R₃Equivalent output capacitor C₁、C₂An output capacitor C_LAnd an internal compensation pole capacitor C_C(ii) a The first stage forward amplifier is composed of equivalent input resistors R of G1, G2, G3 and G3_cThe second stage forward amplifier is G4, and the third stage forward amplifier is G5; a first feed forward transconductance G6, and a second feed forward transconductance G7. Equivalent output resistance R of first-stage forward amplifier₁And an equivalent output capacitor C₁(ii) a Equivalent output resistance R of second stage forward amplifier₂And an equivalent output capacitor C₂(ii) a Equivalent output resistance R of third-stage forward amplifier₃And an output capacitor C_L(ii) a Internal compensation pole capacitor C_C。

The input V of the buffer circuit with high bandwidth and low power consumption_INConnected to the input terminals of the voltage transconductance amplifiers G1 and G2, the output terminal of the voltage transconductance amplifier G1 is connected to the input terminal of the current transconductance G3, the input terminals of the voltage transconductance amplifiers G6 and G7, and the capacitor C_cAnd a resistor R_cOne end of (a); resistance R_cThe other end of the first and second electrodes is grounded; the output of the current transconductance G3 is connected with the output of the voltage transconductance amplifier G2, the input of the voltage transconductance amplifier G4, and the resistor R₁One terminal of and a capacitor C₁One end of (a); resistance R₁Another terminal of (1) and a capacitor C₁The other end of the first and second electrodes is grounded; the output of the transconductance amplifier G4 is connected to the output of the transconductance amplifier G6, the input of the transconductance amplifier G5, and the resistor R₂One terminal of and a capacitor C₂One end of (a); resistance R₂Another terminal of (1) and a capacitor C₂The other end of the first and second electrodes is grounded; the output of the voltage transconductance amplifier G5 is connected with the output of the voltage transconductance amplifier G7 and the resistor R₃One terminal of (1), a capacitor C_LOne terminal of and a capacitor C_cThe other end of (a); resistance R₃Another terminal of (1) and a capacitor C_LThe other end of the first and second electrodes is grounded; the output of the voltage transconductance amplifier G5 is the output VOUT of the high-bandwidth low-power buffer circuit.

The invention provides a buffer circuit with high bandwidth and low power consumption, which is characterized in that the power consumption is reduced by adopting a mode of offsetting a left half-plane zero and a non-dominant pole, so that when the circuit drives a very large capacitive load, a conventional amplifier is allowed to be driven by a small feedback compensation capacitor C_CAnd (4) stabilizing. And the small feedback compensation capacitor can make GBW bigger without increasing power consumption, and achieve the performance of high bandwidth but low power consumption.

Drawings

FIG. 1 is a schematic diagram of a high bandwidth low power consumption buffer circuit according to the present invention;

FIG. 2 is a block diagram of a bandgap reference source with a buffer circuit;

fig. 3 is a schematic diagram of a conventional buffer circuit.

Detailed Description

The invention is explained in more detail below with reference to specific embodiments and the drawing.

As shown in fig. 1, fig. 1 is a schematic diagram of a buffer circuit structure with high bandwidth and low power consumption of the present invention, and the buffer circuit structure with high bandwidth and low power consumption of the present invention includes voltage transconductance amplifiers G1, G2, G4, G5, G6 and G7, current transconductance G3, and an input resistor R_cOutput resistor R₁、R₂、R₃Equivalent output capacitor C₁、C₂An output capacitor C_LAnd an internal compensation pole capacitor C_C(ii) a The first stage forward amplifier is composed of equivalent input resistors R of G1, G2, G3 and G3_cThe second stage forward amplifier is G4, and the third stage forward amplifier is G5; a first feed forward transconductance G6, and a second feed forward transconductance G7. Equivalent output resistance R of first-stage forward amplifier₁And an equivalent output capacitor C₁(ii) a Equivalent output resistance R of second stage forward amplifier₂And an equivalent output capacitor C₂(ii) a Equivalent output resistance R of third-stage forward amplifier₃And an output capacitor C_L(ii) a Internal compensation pole capacitor C_C。

The input V of the buffer circuit with high bandwidth and low power consumption_INConnected to the input terminals of the voltage transconductance amplifiers G1 and G2, the output terminal of the voltage transconductance amplifier G1 is connected to the input terminal of the current transconductance G3, the input terminals of the voltage transconductance amplifiers G6 and G7, and the capacitor C_cAnd a resistor R_cOne end of (a); resistance R_cThe other end of the first and second electrodes is grounded; the output of the current transconductance G3 is connected with the output of the voltage transconductance amplifier G2, the input of the voltage transconductance amplifier G4, and the resistor R₁One terminal of and a capacitor C₁One end of (a); resistance R₁Another terminal of (1) and a capacitor C₁The other end of the first and second electrodes is grounded; the output of the transconductance amplifier G4 is connected to the output of the transconductance amplifier G6, the input of the transconductance amplifier G5, and the resistor R₂One terminal of and a capacitor C₂One end of (a); resistance R₂Another terminal of (1) and a capacitor C₂The other end of the first and second electrodes is grounded; the output of the voltage transconductance amplifier G5 is connected with the output of the voltage transconductance amplifier G7 and the resistor R₃One terminal of (1), a capacitor C_LOne terminal of and a capacitor C_cThe other end of (a); resistance R₃Another terminal of (1) and a capacitor C_LThe other end of the first and second electrodes is grounded; the output of the voltage transconductance amplifier G5 is the output VOUT of the high-bandwidth low-power buffer circuit.

The transfer function of the whole buffer circuit with high bandwidth and low power consumption can be obtained by the graph 1:

the high-bandwidth low-power-consumption buffer circuit has three zero points z in total₁、z₂And z₃Four poles p₁、p₂、p₃And p₄。p₂And p₃Is a conjugate complex pole, consisting of 1+ a₁s+a₂s²A polynomial is obtained.

Wherein:

A_DC＝g_m1g_m2g_m3R₁R₂R₃ (2)

wherein A is_DCDenotes the DC gain, g_m1Transconductance parameters, G, for transconductance amplifiers G1 and G2_m2G is a transconductance parameter corresponding to the transconductance amplifier G4_m3G is a transconductance parameter corresponding to the transconductance amplifier G5_mc1G is a transconductance parameter corresponding to the transconductance amplifier G3_mf1G is a transconductance parameter corresponding to the transconductance amplifier G6_mf2Corresponding to the transconductance parameter of the transconductance amplifier G7.

By applying a quadratic polynomial 1+ a₁s+a₂s²Analysis of natural frequency ω of_nAnd the quality factor Q is:

the invention utilizes first and second left half-plane zeros z₁And z₂To compensate for conjugate complex pole p₂And p₃Affecting the stability of the closed loop. And, using the third left half-plane zero point z₃The phase margin is further improved. More specifically, to theoretically obtain accurate phase compensation by combining z₁And z₂Are respectively arranged at 2 omega_GBWAnd 3 omega_GBWFinish, form ω of the polynomial_nIs placed atTo ensure that the quadratic polynomial has no significant effect on the stability of the circuit, its Q value is set toFinally, C can be obtained_CAnd C_LThe relationship between them is:

as seen from the formula (13), C_CAnd C_LIs proportional to the square root of_m3>g_mc1，g_m2R₂Is a second stage gain>>1，C₁The parasitic capacitance is very small, and it can be concluded that C_CMuch less than C_LThus the present invention is able to achieve large bandwidths with very large capacitive loads using small currents.

Circuit structure (as shown in FIG. 3) in order to realize stability of buffer circuit (formula C)_m1＝4g_m1·C_L/g_m3) And high bandwidth (formula GBW ═ g)_m1/C_m1) In the load capacitance C_LWhen increased, the required stable capacitance C_m1Very large, g needs to be increased to maintain the bandwidth constant_m1The additional effect is the current (formula g)_m1＝I_D1/(V_GS-V_T) A sharp increase; the circuit structure (as shown in fig. 1) of the present invention can reduce the required stable capacitance C when the same bandwidth as that of the prior art structure is realized_C(formula)Under the same load C as the normal structure_LAnd in the case of bandwidth, generally orderEqual to 1 if let C of the existing structure_m1In the formula (4 g)_m1/g_m3) Fraction also equal to 1, comparison C_m1＝C_LAndthe values of the two stable capacitors show that the structure of the invention can achieve the purpose of greatly reducing power consumption by reducing the stable capacitors).

The above description is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.