阅读说明：本技术 Verilog文件转换方法、装置、存储介质及设备 (Verilog file conversion method, device, storage medium and equipment ) 是由 田红圣 吴蕾 于 2020-12-22 设计创作，主要内容包括：本发明一个或多个实施例公开一种Verilog文件转换方法、装置、存储介质及设备,该方法包括：获取原始Verilog文件以及配置文件,其中,所述配置文件中包括与目标电子设计自动化EDA工具对应的目标表述方式的信息；从所述原始Verilog文件中获取描述逻辑功能的目标代码；将所述目标代码转换为以所述目标表述方式进行表示,得到转换后的文件；根据所述目标代码生成第一测试激励文件；根据所述第一测试激励文件分别以所述原始Verilog文件以及所述转换后的文件进行仿真测试,得到第一测试结果；根据所述第一测试结果,判断所述转换后文件与所述原始Verilog文件的功能是否一致,该方法可提高Verilog文件的通用性。(One or more embodiments of the invention disclose a Verilog file conversion method, device, storage medium and equipment, the method comprising: acquiring an original Verilog file and a configuration file, wherein the configuration file comprises information of a target expression mode corresponding to a target Electronic Design Automation (EDA) tool; acquiring an object code describing a logic function from the original Verilog file; converting the target code into a file expressed in the target expression mode to obtain a converted file; generating a first test excitation file according to the target code; according to the first test excitation file, respectively carrying out simulation test on the original Verilog file and the converted file to obtain a first test result; and judging whether the functions of the converted file are consistent with those of the original Verilog file or not according to the first test result, wherein the method can improve the universality of the Verilog file.)

1. A Verilog file conversion method is characterized by comprising the following steps:

acquiring an original Verilog file and a configuration file, wherein the configuration file comprises information of a target expression mode corresponding to a target Electronic Design Automation (EDA) tool;

acquiring an object code describing a logic function from the original Verilog file;

converting the target code into a file expressed in the target expression mode to obtain a converted file;

generating a first test excitation file according to the target code;

according to the first test excitation file, respectively carrying out simulation test on the original Verilog file and the converted file to obtain a first test result;

and judging whether the functions of the converted file are consistent with those of the original Verilog file or not according to the first test result.

2. The method of claim 1, wherein the first test result includes a first signal output by a simulation tool when the original Verilog file is used for simulation test, and a second signal output by the simulation tool when the converted file is used for simulation test, and the determining whether the functions of the converted file and the original Verilog file are consistent according to the first test result includes:

comparing the first signal to the second signal;

in response to the first signal being consistent with the second signal, determining that the converted file is functionally consistent with the original Verilog file;

and in response to the first signal not being consistent with the second signal, determining that the converted file is not consistent with the original Verilog file in function.

3. The method of claim 1, further comprising:

modifying the configuration file in response to judging that the functions of the converted file are inconsistent with those of the original Verilog file according to the first test result;

and acquiring an object code describing a logic function from the original Verilog file again according to the modified configuration file, and converting the acquired object code into a target expression mode for representing to obtain a converted file.

4. The method of claim 1, wherein obtaining object code describing a logical function from the original Verilog file comprises:

identifying code describing a logic function from the original Verilog file;

extracting the object code describing the target logic function from the identified code.

5. The method of claim 4, wherein the configuration file further comprises:

the logical function's correspondence to Verilog code used to represent the logical function.

6. The method of claim 5, wherein identifying code describing logical functions from the original Verilog file comprises:

and identifying codes describing the logic functions from the original Verilog file according to the corresponding relation between the logic functions and the Verilog codes for representing the logic functions.

7. The method according to any one of claims 1 to 6, further comprising:

after acquiring the target code describing the logic function from the original Verilog file, testing the original Verilog file by using a second test excitation file to obtain a second test result;

determining a target logic function included in the original Verilog file according to the second test result;

and determining whether the target code is correct according to the target logic function.

8. A Verilog file conversion apparatus, comprising:

the electronic design automation EDA tool comprises a first acquisition module, a second acquisition module and a third acquisition module, wherein the first acquisition module is configured to acquire an original Verilog file and a configuration file, and the configuration file comprises information of a target expression mode corresponding to a target electronic design automation EDA tool;

the second acquisition module is configured to acquire object codes describing logic functions from the original Verilog file;

the first conversion module is configured to convert the target code into a file expressed in the target expression mode to obtain a converted file;

a generating module configured to generate a first test stimulus file from the target code;

the first test module is configured to perform simulation test on the original Verilog file and the converted file respectively according to the first test excitation file to obtain a first test result;

and the verification module is configured to judge whether the functions of the converted file and the original Verilog file are consistent or not according to the first test result.

9. The apparatus of claim 8, wherein the first test result comprises a first signal output by a simulation tool when performing simulation test on the original Verilog file and a second signal output by the simulation tool when performing simulation test on the converted file, and wherein the verification module is specifically configured to:

comparing the first signal to the second signal;

in response to the first signal being consistent with the second signal, determining that the converted file is functionally consistent with the original Verilog file;

and in response to the first signal not being consistent with the second signal, determining that the converted file is not consistent with the original Verilog file in function.

10. The apparatus of claim 8, further comprising:

the modification module is configured to modify the configuration file in response to judging that the converted file is inconsistent with the original Verilog file in function according to the first test result;

and the second conversion module is configured to obtain the object code describing the logic function from the original Verilog file again according to the modified configuration file, and convert the obtained object code into the object expression mode for representation to obtain the converted file again.

11. The apparatus of claim 8, wherein the second obtaining module is specifically configured to:

identifying code describing a logic function from the original Verilog file;

extracting the object code describing the target logic function from the identified code.

12. The apparatus of claim 11, wherein the configuration file further comprises:

the logical function's correspondence to Verilog code used to represent the logical function.

13. The apparatus of claim 12, wherein the second obtaining module is specifically configured to:

and identifying codes describing the logic functions from the Verilog file according to the corresponding relation between the logic functions and Verilog codes for representing the logic functions.

14. The apparatus of any one of claims 8 to 13, further comprising:

the second testing module is configured to test the original Verilog file by using a second testing excitation file after acquiring the target code describing the logic function from the original Verilog file to obtain a second testing result;

the first determining module is configured to determine a target logic function included in the original Verilog file according to the second test result;

a second determination module configured to determine whether the target code is correct according to the target logic function.

15. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the Verilog file conversion method of any one of claims 1 to 7 when executing the program.

16. A non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the Verilog file conversion method of any one of claims 1 to 7.

Technical Field

The invention relates to the technical field of computers, in particular to a Verilog file conversion method, a device, a storage medium and equipment.

Background

Currently, in the integrated circuit design, the design process can be mainly divided into a semi-customized circuit design process and a fully customized circuit design process. The semi-custom Circuit design refers to performing behavioral level Description of a chip by using a Hardware Description Language (Very-High-Speed-Integrated Circuit Hardware Description Language) according to a chip design specification, wherein the Verilog is a Hardware Description Language, and the Verilog is a Language for describing the structure and behavior of digital system Hardware in a text form. Then, a synthesis tool is used for converting the hardware description language into a gate-level netlist, and finally, a process of automatic physical design is carried out through an automatic layout and routing tool. In the process, most steps can be automatically designed by an EDA (Electronic design automation) tool, so that large-scale chip circuit design can be conveniently realized. In the design of a full-custom circuit, a circuit meeting the function is designed according to the function and performance requirements of a user, and then layout design and optimization are manually carried out. In the semi-custom circuit design flow, a Verilog or VHDL design file is converted into a gate-level netlist through a synthesis tool, and then a final layout design is obtained through an automatic layout and routing tool. In such a flow, the Verilog design file is compatible with, and can be correctly identified by, the EDA tool. However, in the full-custom design flow, the circuit design is directly carried out, and Verilog is not required to be converted into a gate-level netlist through a synthesis tool. In this case, the Verilog file is generally only used for previous functional verification, and it is likely that the Verilog file is not compatible with other EDA tools. At present, in large chip Design, a semi-custom circuit Design and a full-custom circuit Design are often used comprehensively, a part of special IPs (Intellectual Property modules) can adopt a custom circuit Design flow to complete circuit and layout Design inside the IPs, then the layout files and other Design files of the IPs can be called to perform top-level Design when the top-level Design of the chip is performed, and meanwhile, the Verilog files of the IPs can also be called when the top-level Design is performed to perform top-level Verilog simulation verification and DFT (Design For Testability). Verilog of such a fully customized circuit design block often presents a situation where subsequent process EDA tools are incompatible. Even the Verilog file in the semi-custom design flow may be compatible with some EDA tools in the subsequent flow, but not with other EDA tools, which results in poor portability of the Verilog file.

Disclosure of Invention

In view of the above, one or more embodiments of the present invention provide a method, an apparatus, a storage medium, and a device for converting a Verilog file, which can improve the compatibility of the Verilog file with an EDA tool.

One or more embodiments of the present invention provide a Verilog file conversion method, including: acquiring an original Verilog file and a configuration file, wherein the configuration file comprises information of a target expression mode corresponding to a target Electronic Design Automation (EDA) tool; acquiring an object code describing a logic function from the original Verilog file; converting the target code into a file expressed in the target expression mode to obtain a converted file;

generating a first test excitation file according to the target code; according to the first test excitation file, respectively carrying out simulation test on the original Verilog file and the converted file to obtain a first test result; and judging whether the functions of the converted file are consistent with those of the original Verilog file or not according to the first test result.

Optionally, the determining, according to the first test result, whether the functions of the converted file and the original Verilog file are consistent includes: comparing the first signal to the second signal; in response to the first signal being consistent with the second signal, determining that the converted file is functionally consistent with the original Verilog file; and in response to the first signal not being consistent with the second signal, determining that the converted file is not consistent with the original Verilog file in function.

Optionally, the method further includes: modifying the configuration file in response to judging that the functions of the converted file are inconsistent with those of the original Verilog file according to the first test result; and acquiring an object code describing a logic function from the original Verilog file again according to the modified configuration file, and converting the acquired object code into a target expression mode for representing to obtain a converted file.

Optionally, obtaining object code describing a logic function from the original Verilog file includes: identifying code describing a logic function from the original Verilog file; extracting the object code describing the target logic function from the identified code.

Optionally, the configuration file further includes: the logical function's correspondence to Verilog code used to represent the logical function.

Optionally, identifying code describing a logic function from the original Verilog file includes: and identifying codes describing the logic functions from the Verilog file according to the corresponding relation between the logic functions and Verilog codes for representing the logic functions.

Optionally, the method further includes: after acquiring the target code describing the logic function from the original Verilog file, testing the original Verilog file by using a second test excitation file to obtain a second test result; determining a target logic function included in the original Verilog file according to the second test result; and determining whether the target code is correct according to the target logic function.

One or more embodiments of the present invention further provide a Verilog file conversion apparatus, including: the electronic design automation EDA tool comprises a first acquisition module, a second acquisition module and a third acquisition module, wherein the first acquisition module is configured to acquire an original Verilog file and a configuration file, and the configuration file comprises information of a target expression mode corresponding to a target electronic design automation EDA tool; the second acquisition module is configured to acquire object codes describing logic functions from the original Verilog file; the first conversion module is configured to convert the target code into a file expressed in the target expression mode to obtain a converted file; a generating module configured to generate a first test stimulus file from the target code; the first test module is configured to perform simulation test on the original Verilog file and the converted file respectively according to the first test excitation file to obtain a first test result; and the verification module is configured to judge whether the functions of the converted file and the original Verilog file are consistent or not according to the first test result.

Optionally, the first test result includes a first signal output by a simulation tool when the original Verilog file is used for simulation test, and a second signal output by the simulation tool when the converted file is used for simulation test, and the verification module is specifically configured to: comparing the first signal to the second signal; in response to the first signal being consistent with the second signal, determining that the converted file is functionally consistent with the original Verilog file; and in response to the first signal not being consistent with the second signal, determining that the converted file is not consistent with the original Verilog file in function.

Optionally, the apparatus further comprises: the modification module is configured to modify the configuration file in response to judging that the converted file is inconsistent with the original Verilog file in function according to the first test result; and the second conversion module is configured to obtain the object code describing the logic function from the original Verilog file again according to the modified configuration file, and convert the obtained object code into the object expression mode for representation to obtain the converted file again.

Optionally, the second obtaining module is specifically configured to: identifying code describing a logic function from the original Verilog file; extracting the object code describing the target logic function from the identified code.

Optionally, the configuration file further includes: the logical function's correspondence to Verilog code used to represent the logical function.

Optionally, the second obtaining module is specifically configured to: and identifying codes describing the logic functions from the Verilog file according to the corresponding relation between the logic functions and Verilog codes for representing the logic functions.

Optionally, the apparatus further comprises: the second testing module is configured to test the original Verilog file by using a second testing excitation file after acquiring the target code describing the logic function from the original Verilog file to obtain a second testing result; the first determining module is configured to determine a target logic function included in the original Verilog file according to the second test result; a second determination module configured to determine whether the target code is correct according to the target logic function.

One or more embodiments of the present invention also provide an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the processor implements any Verilog file conversion method as described above.

One or more embodiments of the present invention also provide a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform any of the Verilog file conversion methods described above.

In the Verilog file conversion method provided by one or more embodiments of the present invention, an object code describing a logic function is obtained from a Verilog file, the object code is expressed in an object expression manner corresponding to an object EDA tool in a configuration file, and then it is verified whether the converted file is equivalent to an original Verilog file by a test stimulus file, so that the purpose of equivalently converting the Verilog file into a file compatible with the object EDA tool is achieved, the Verilog file can be applied to various EDA tools, and the universality of the Verilog file is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flow diagram illustrating a Verilog file transformation method in accordance with one or more embodiments of the invention;

FIG. 2 is a flow diagram illustrating a Verilog file transformation method in accordance with one or more embodiments of the invention;

FIG. 3 is a flow diagram illustrating a Verilog file transformation method in accordance with one or more embodiments of the invention;

FIG. 4 is a schematic structural diagram of a Verilog file conversion device according to one or more embodiments of the present invention;

fig. 5 is a schematic structural diagram of an electronic device according to one or more embodiments of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a flowchart illustrating a Verilog file conversion method according to one or more embodiments of the present invention, where the method includes:

step 101: acquiring an original Verilog file and a configuration file, wherein the configuration file comprises information of a target expression mode corresponding to an EDA tool;

the configuration file defines, for example, a target EDA tool that the Verilog file needs to be compatible with and a Verilog expression mode corresponding to the target EDA tool. For example, if the logical and function is implemented, there may be several expressions as follows:

and (3) behavior level: OUT is A & B;

and (4) gate level: and I1(OUT, A, B);

or the function of the logical and may be expressed using the form of a primitive.

For example, only a general Verilog expression form may be defined in the configuration file, and in addition, in step 101, the Verilog file may be converted into a general Verilog expression form according to the configuration file.

Step 102: acquiring an object code describing a logic function from the original Verilog file;

the logic function in one or more embodiments of the present invention may be, for example, a logic function that can be realized by a single logic device, or a logic function that can be realized by a functional unit/module that is formed by connecting at least two logic devices through a certain connection relationship. On the basis, an algorithm for identifying codes describing logic functions in the Verilog file can be constructed in advance, Verilog codes corresponding to various logic devices can be defined in the algorithm in advance, or Verilog code segments corresponding to function modules formed by at least two logic devices can be defined, the Verilog file is used as the input of the algorithm, the algorithm is operated, the codes describing the logic functions in the Verilog file and the logic functions described by the codes can be output, and then the target codes are extracted from the output codes according to the application of the codes. For example, for a more complex IP module, such as a memory, when the original Verilog file is only used for the top level DFT design (e.g., scan chain design), if the top level DFT design is performed by using the completed original Verilog file, the design cycle will be longer, so that the Verilog logic related to the test can be extracted according to the purpose of the identified code describing the logic function to remove the redundant logic (i.e., the logic unrelated to the test, such as memory array logic, etc.), so as to obtain the target code, which can speed up the subsequent design process and simplify the design process.

Step 103: converting the target code into a file expressed in the target expression mode to obtain a converted file;

for example, for each EDA tool, a Verilog expression method compatible with each EDA tool may be preset, and the Verilog expression method compatible with each EDA tool may be set as a target expression method corresponding to the EDA tool. Assuming that the target expression compatible with a certain EDA tool a includes expression 1, expression 2, and expression 3, taking the case assumed here as an example, in step 103, the target code may be converted into any expression of expression 1, expression 2, and expression 3.

Step 104: generating a first test excitation file according to the target code;

for example, a set of simulation stimulus files can be generated according to the logic functions described by the object code, and the simulation stimulus files are used for performing simulation tests on the logic functions.

Step 105: according to the first test excitation file, respectively carrying out simulation test on the original Verilog file and the converted file to obtain a first test result;

in one example, a simulation test is performed by the simulation tool according to the first test stimulus file by using the original Verilog file to obtain a first signal output by the simulation tool, and a simulation test is performed by the simulation tool according to the first test stimulus file by using the converted file to obtain a second signal output by the simulation tool. Because the test stimulus files used for carrying out the simulation test based on the original Verilog file and the converted file are the same, whether the converted file is equivalent to the original Verilog file or not can be determined by judging the consistency of the first signal and the second signal.

Step 106: and judging whether the functions of the converted file are consistent with those of the original Verilog file or not according to the first test result.

Following the above example, if the first signal is consistent with the second signal, the converted file can be determined to be equivalent to the original Verilog file, otherwise, the converted file can be determined not to be equivalent to the original Verilog file, and then the Verilog file can be converted again.

In the Verilog file conversion method provided by one or more embodiments of the present invention, an object code describing a logic function is obtained from a Verilog file, the object code is expressed in an object expression manner corresponding to a target EDA tool in a configuration file, and then it is verified whether the converted file is equivalent to an original Verilog file by a test stimulus file, so that the purpose of equivalently converting the Verilog file into a file compatible with the target EDA tool is achieved, the Verilog file can be applied to various EDA tools, and the universality of the Verilog file is improved. In addition, based on the method, because the Verilog which is not compatible with the EDA tool can be converted into the Verilog which is compatible with the mainstream EDA tool in a simpler mode, the Verilog file does not need to be redesigned, and the design time is saved.

In one or more embodiments of the present invention, the designer of the Verilog file may also define some functional modules, in which case, the configuration file may further include: the logical function's correspondence to Verilog code used to represent the logical function. Therefore, when the object code describing the logic function is obtained from the Verilog file, some self-defined function modules in the Verilog file can be effectively identified based on the corresponding relation, and the code describing the logic function is obtained. The logic function may be implemented by one logic device or by at least two connected logic devices, for example.

In one or more embodiments of the present invention, the Verilog file conversion method may further include: modifying the configuration file in response to judging that the functions of the converted file are inconsistent with those of the original Verilog file according to the first test result; and acquiring an object code describing a logic function from the original Verilog file again according to the modified configuration file, and converting the acquired object code into a target expression mode for representing to obtain a converted file. Following the above example, if the first signal and the second signal are not consistent, it may be determined that the converted file is not consistent with the functions of the original Verilog file, and this may be the case that some special function modules in the original Verilog file are not effectively recognized when the original Verilog file is converted, for example, when the original Verilog file includes some user-defined function modules, when the code describing the logic functions is recognized from the original Verilog file, these function modules may not be correctly recognized. Therefore, after the functions of the converted file and the original Verilog file are determined to be inconsistent according to the first test result, the expressions of the custom function modules can be added/modified in the configuration file, so that the logic functions in the Verilog file can be correctly identified when the original Verilog file is identified again after the configuration file is modified.

In one or more embodiments of the present invention, the determining, according to the first test result, whether the functions of the converted file and the original Verilog file are consistent may include: comparing the first signal to the second signal; in response to the first signal being consistent with the second signal, determining that the converted file is functionally consistent with the original Verilog file; and in response to the first signal not being consistent with the second signal, determining that the converted file is not consistent with the original Verilog file in function.

Fig. 2 is a flowchart illustrating a Verilog file conversion method according to one or more embodiments of the present invention, taking the example shown in fig. 2 as an example, when performing equivalence verification on an original Verilog file and a converted file, the test stimulus file is used to add a test stimulus signal to input signals of the original Verilog file and the converted Verilog file, respectively, as shown in steps 203, 204, and 205 in fig. 2, and then a Verilog simulation tool is used to perform simulation based on two Verilog files, respectively, and then changes of output signals of the two Verilog files are compared. If the changes of the two Verilog output signals are completely consistent, the converted Verilog file and the original Verilog file can be judged to be equivalent, namely the Verilog file and the original Verilog file are consistent in function.

In one or more embodiments of the present invention, a complex Verilog may be simplified according to requirements, for example, when a step of "obtaining an object code describing a logic function from the Verilog file" is performed, a part of important logic functions in the Verilog file may be extracted according to requirements, and redundant logic is removed, so as to simplify a design flow and shorten a design cycle. Based on this, obtaining the object code describing the logic function from the original Verilog file may include: identifying code describing a logic function from the original Verilog file; extracting the object code describing the target logic function from the identified code.

In one or more embodiments of the invention, identifying code describing a logical function from the original Verilog file may include: and identifying codes describing the logic functions from the original Verilog file according to the corresponding relation between the logic functions and the Verilog codes for representing the logic functions. For example, when some user-defined function modules are included in the original Verilog file, the code describing these user-defined function modules can be correctly identified from the original Verilog file according to Verilog code corresponding to the logic functions defined in the configuration file.

In one or more embodiments of the present invention, the Verilog file conversion method may further include: after acquiring the target code describing the logic function from the original Verilog file, testing the original Verilog file by using a second test excitation file to obtain a second test result; determining a target logic function included in the original Verilog file according to the second test result; and determining whether the target code is correct according to the target logic function. The original Verilog file may be added with the corresponding test stimulus signal, and then the logic function included in the Verilog file may be determined by the output signal. For example, information about a scan chain in a Verilog file can be determined by pouring a particular stimulus into the input signal of the scan chain and then observing the output signal of the scan chain.

Fig. 3 is a flowchart illustrating a Verilog file conversion method according to one or more embodiments of the present invention, which may include the following processes, as shown in fig. 3:

step 301: preparing an original Verilog file;

step 302: identifying logic function description in an original Verilog file, converting the logic function description into a Verilog description mode (an example of the target EDA tool) which can be identified by a mainstream EDA tool, namely a universal Verilog file, and generating a set of test excitation according to an identified logic structure;

step 303: respectively carrying out simulation test on the original Verilog and the general Verilog by using the test excitation file generated in the step 302, comparing whether the outputs of the two Verilog files are consistent, if the output signals of the two Verilog files in the simulation test result are completely consistent, determining that the generated general Verilog file is equivalent to the original Verilog file, otherwise, determining that the two Verilog files are not equivalent, and returning to execute the step 302 to convert the original Verilog file again when the two Verilog files are not equivalent;

step 304: after the equivalent verification of the generated generic Verilog file in step 303 is passed, the generated generic Verilog file can be applied to a design link of a subsequent mainstream EDA tool.

Fig. 4 is a schematic structural diagram illustrating a Verilog file conversion apparatus according to one or more embodiments of the present invention, and as shown in fig. 4, the apparatus 40 may include:

a first obtaining module 41, configured to obtain an original Verilog file and a configuration file, where the configuration file includes information of a target expression mode corresponding to a target EDA tool;

a second obtaining module 42 configured to obtain object code describing a logic function from the original Verilog file;

a first conversion module 43, configured to convert the object code into a representation in the object expression manner, resulting in a converted file;

a generating module 44 configured to generate a first test stimulus file from the object code;

a first testing module 45, configured to perform simulation testing on the Verilog file and the converted file respectively according to the first test stimulus file to obtain a first testing result;

and the verification module 46 is configured to determine whether the functions of the converted file and the original Verilog file are consistent according to the first test result.

In one or more embodiments of the present invention, the first test result includes a first signal output by a simulation tool when the original Verilog file is used for simulation test, and a second signal output by the simulation tool when the converted file is used for simulation test, and the verification module may be specifically configured to: comparing the first signal to the second signal; in response to the first signal being consistent with the second signal, determining that the converted file is functionally consistent with the original Verilog file; and in response to the first signal not being consistent with the second signal, determining that the converted file is not consistent with the original Verilog file in function.

In one or more embodiments of the present invention, the Verilog file conversion apparatus may further include: the modification module is configured to modify the configuration file in response to judging that the converted file is inconsistent with the original Verilog file in function according to the first test result; and the second conversion module is configured to obtain the object code describing the logic function from the original Verilog file again according to the modified configuration file, and convert the obtained object code into the object expression mode for representation to obtain the converted file again.

In one or more embodiments of the present invention, the second obtaining module is specifically configured to: identifying code describing a logic function from the original Verilog file; extracting the object code describing the target logic function from the identified code.

In one or more embodiments of the present invention, the configuration file may further include: the logical function's correspondence to Verilog code used to represent the logical function.

In one or more embodiments of the present invention, the second obtaining module may be specifically configured to: and identifying codes describing the logic functions from the Verilog file according to the corresponding relation between the logic functions and Verilog codes for representing the logic functions.

In one or more embodiments of the present invention, the Verilog file conversion apparatus may further include: the second testing module is configured to test the original Verilog file by using a second testing excitation file after acquiring the target code describing the logic function from the original Verilog file to obtain a second testing result; the first determining module is configured to determine a target logic function included in the original Verilog file according to the second test result; a second determination module configured to determine whether the target code is correct according to the target logic function.

One or more embodiments of the present invention also provide an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the processor implements any Verilog file conversion method as described above.

One or more embodiments of the present invention provide a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform any of the Verilog file conversion methods described above.

Fig. 5 is a schematic diagram illustrating a more specific hardware structure of an electronic device according to one or more embodiments of the present invention, where the electronic device may include: a processor 510, a memory 520, an input/output interface 530, a communication interface 540, and a bus 550. Wherein processor 510, memory 520, input/output interface 530, and communication interface 540 are communicatively coupled to each other within the device via bus 550.

The processor 510 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits, and is configured to execute related programs to implement the technical solutions provided in the embodiments of the present specification.

The Memory 520 may be implemented in the form of a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, or the like. The memory 520 may store an operating system and other application programs, and when the technical solution provided by the embodiments of the present specification is implemented by software or firmware, the relevant program codes are stored in the memory 520 and called by the processor 510 for execution.

The input/output interface 530 is used for connecting an input/output module to realize information input and output. The i/o module may be configured as a component in a device (not shown) or may be external to the device to provide a corresponding function. The input devices may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output devices may include a display, a speaker, a vibrator, an indicator light, etc.

The communication interface 540 is used for connecting a communication module (not shown in the figure) to realize communication interaction between the device and other devices. The communication module can realize communication in a wired mode (such as USB, network cable and the like) and also can realize communication in a wireless mode (such as mobile network, WIFI, Bluetooth and the like).

Bus 550 includes a pathway to transfer information between various components of the device, such as processor 510, memory 520, input/output interface 530, and communication interface 440.

It should be noted that although the above-mentioned device only shows the processor 510, the memory 520, the input/output interface 530, the communication interface 540 and the bus 550, in a specific implementation, the device may also include other components necessary for normal operation. In addition, those skilled in the art will appreciate that the above-described apparatus may also include only those components necessary to implement the embodiments of the present description, and not necessarily all of the components shown in the figures.

Computer-readable media of the present embodiments, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "comprising", without further limitation, means that the element so defined is not excluded from the group consisting of additional identical elements in the process, method, article, or apparatus that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.

In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations of the invention.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.