阅读说明：本技术 减少装置覆盖误差 (Reducing device overlay error ) 是由 L·叶鲁舍米 R·弗克维奇 于 2018-07-30 设计创作，主要内容包括：本发明提供过程控制方法、计量目标及生产系统以减少或消除过程覆盖误差。计量目标具有一(多)对具有不同分段的周期结构,例如,在所述对的一个周期结构中无分段,而在所述对的另一周期结构中具有类似装置的分段。过程控制方法直接在先前层处的所述周期结构的生产之后及在当前层处的所述周期结构的生产之前从所述先前层处的所述周期结构导出计量测量,并使用所述导出的测量来调整作为所述当前层的生产的一部分的光刻阶段。生产系统将光刻工具及计量工具集成到生产反馈回路中,所述生产反馈回路实现了逐层过程调整。(The present invention provides process control methods, metrology targets, and production systems to reduce or eliminate process overlay errors. The metrology target has a (plurality of) pairs of periodic structures with different segmentation, e.g. no segmentation in one periodic structure of the pair, and similarly arranged segmentation in the other periodic structure of the pair. A process control method derives a metrology measurement from the periodic structure at a previous layer directly after production of the periodic structure at the previous layer and before production of the periodic structure at a current layer, and uses the derived measurement to adjust a lithography phase that is part of the production of the current layer. The production system integrates the lithography tool and the metrology tool into a production feedback loop that enables layer-by-layer process tuning.)

1. A process control method of utilizing metrology targets having a periodic structure at least at a previous layer and a current layer of a wafer in lithographic production, the process control method comprising:

deriving a metrology measurement from the periodic structure at the previous layer directly after production of the periodic structure at the previous layer and before production of the periodic structure at the current layer, and

adjusting at least a lithography stage as part of production of the current layer using the derived measurements.

2. The process control method of claim 1, wherein the derived metrology measurements include at least coverage measurements for two different periodic structures in the previous layer.

3. The process control method of claim 1, further comprising deriving a metrology measurement from the periodic structure at the previous layer after applying an etch phase to the periodic structure at the previous layer and before the production of the periodic structure at the current layer.

4. The process control method according to claim 3, wherein the derived metrology measurements comprise at least overlay measurements on the periodic structures in the previous layer before and after the etch phase.

5. The process control method according to any one of claims 1 to 4, wherein the metrology target is an imaging target.

6. The process control method of claim 5, wherein the imaging target comprises at least three layers of the wafer, and the process control method is performed after production of a first layer of the three layers and production of a second layer of the three layers.

7. The process control method according to any one of claims 1-4, wherein the metrology target is a scatterometry target.

8. The process control method of claim 7, wherein the scatterometry target comprises at least two grating-over-grating targets having their previous layers produced side-by-side on the wafer for the metrology measurement derivation.

9. The process control method according to one of claims 1-8, wherein the metrology target comprises at least two pairs of the periodic structures, at least one pair at the previous layer and at least another pair in the current layer, and wherein in each pair one periodic structure is segmented with segmentation of similar devices while the other periodic structure is not segmented.

10. A metrology target, comprising:

at least two pairs of periodic structures, at least one pair at a previous layer and at least one other pair in a current layer, and

wherein in each pair one periodic structure is segmented with device-like segmentation, while the other periodic structure is not segmented.

11. The metrology target of claim 10, configured as an imaging target with two or three pairs of periodic structures in each of two measurement directions.

12. The metrology target of claim 10, configured as a scatterometry target having two side-by-side grating-over-grating periodic structures along at least one measurement direction.

13. A target design file for the metrology target of any one of claims 10 to 12.

14. A metrology measurement of the metrology target of any one of claims 10-12.

15. A production system, comprising:

at least one lithography tool configured to prepare a wafer by producing layers of the wafer,

a metrology tool configured to derive a metrology measurement from a periodic structure at a previous layer of a metrology target directly after production of a previous layer periodic structure and before production of a periodic structure at a current layer of the metrology target, and

a control unit configured to use the derived measurements to adjust the at least one lithography tool at least with respect to a lithography stage that is part of production of the current layer that is the metrology target.

16. The production system of claim 15, wherein the control unit is independent, part of the at least one lithography tool and/or part of the metrology tool.

17. The production system of claim 15, wherein the metrology target comprises at least two pairs of the periodic structures, at least one pair at the previous layer and at least another pair in the current layer, and wherein in each pair, one periodic structure is segmented with device-like segmentation while another periodic structure is not segmented.

1. Field of the invention

The present invention relates to the field of semiconductor metrology, and more particularly, to eliminating or reducing process overlay errors.

2. Discussion of related Art

As node sizes in semiconductor manufacturing decrease, the impact of process overlay errors becomes more and more significant.

Background

Disclosure of Invention

The following is a simplified summary that provides a preliminary understanding of the invention. This summary does not necessarily identify key elements nor limit the scope of the invention, but is merely used as an introduction to the following description.

One aspect of the invention provides a process control method that utilizes metrology targets having a periodic structure at least at a previous layer and a current layer of a wafer in lithographic production, the process control method comprising: deriving metrology measurements from the periodic structure at the previous layer directly after production of the periodic structure at the previous layer and before production of the periodic structure at the current layer, and using the derived measurements to adjust at least a lithography phase that is part of the production of the current layer.

These, additional and/or other aspects and/or advantages of the present invention are set forth in the detailed description that follows; possibly inferred from the detailed description; and/or may be learned by practice of the invention.

Drawings

For a better understanding of embodiments of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings in which like numerals refer to corresponding elements or parts throughout.

In the drawings:

fig. 1A and 1B are high-level schematic block diagrams of process control methods according to some embodiments of the invention.

Fig. 2A through 2C are high-level schematic diagrams of design principles applicable to metrology targets, according to some embodiments of the invention.

Fig. 3 and 4 are high-level schematic diagrams of post-production metrology targets relating to the disclosed measurement methods, in accordance with some embodiments of the invention.

FIG. 5 is a high-level schematic diagram of a metrology scatterometry target designed to be printed side-by-side to employ process control methods, according to some embodiments of the present invention.

Fig. 6A, 6B, 7A and 7B are high-level schematic diagrams of production systems according to some embodiments of the invention.

Detailed Description

In the following description, various aspects of the present invention are described. For purposes of explanation, specific configurations and details are set forth in order to provide a thorough understanding of the present invention. However, it will also be apparent to one skilled in the art that the present invention may be practiced without the specific details presented herein. In addition, well-known features may be omitted or simplified in order not to obscure the present invention. With specific reference to the drawings, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the present invention only, and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention, the description taken with the drawings making apparent to those skilled in the art how the several forms of the invention may be embodied in practice.

Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not limited in its application to the details of construction and the arrangement of the components set forth in the following description or illustrated in the drawings. The invention is applicable to other embodiments and combinations of the disclosed embodiments, which can be practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting.

Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the specification discussions utilizing terms such as "processing," "computing," "calculating," "determining," "enhancing," "deriving," or the like, refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities within the computing system's registers and/or memories into other data similarly represented as physical quantities within the computing system's memories, registers or other such information storage, transmission or display devices. In certain embodiments, the illumination technique may include electromagnetic radiation in the visible range, ultraviolet or even shorter wave radiation (e.g., x-rays), and even possible particle beams.

Embodiments of the present invention provide efficient and economical methods and mechanisms for improving (reducing) device coverage by eliminating or reducing process coverage errors, and thereby provide improvements in the field of semiconductor manufacturing technology and metrology.

As semiconductor node sizes continue to shrink, the disclosed embodiments reduce variations in overlay and improve control over process variations that affect on-product overlay (OPO). In particular, the disclosed embodiments reduce or eliminate overlay variations associated with incoming processes that may result in overlay offset and feature size dependencies. To improve control, the disclosed embodiments establish measurements prior to a particular lithography process stage and feed forward the measurements for each wafer to improve wafer-specific overlay control in a lithography tool, such as a scanner. We disclose below the concept of achieving such a target design, measurement and control.

Process control methods, metrology targets, and production systems are provided to reduce or eliminate process overlay errors. The metrology target has a (plurality of) pairs of periodic structures with different segmentation, e.g. no segmentation in one periodic structure of the pair, and similarly arranged segmentation in the other periodic structure of the pair. The process control method derives metrology measurements from the periodic structure at the previous layer directly after production of the periodic structure at the previous layer and before production of the periodic structure at the current layer, and uses the derived measurements to adjust a lithography phase that is part of the production of the current layer. The production system integrates the lithography tool and the metrology tool into a production feedback loop that enables layer-by-layer process tuning.

Fig. 1A and 1B are high-level schematic block diagrams of a process control method 100 according to some embodiments of the invention. The process control method utilizes a metrology target 210 (see targets illustrated in figures 2A-2C and 3-5) having periodic structures 214 at least at a previous layer 210A and a current layer 210B of the wafer 90 in lithographic production. The method stages may be performed with respect to the system 200 described below (e.g., see fig. 6A, 6B, 7A, and 7B), which may optionally be configured to implement the method 100. The method 100 may be implemented at least in part by at least one computer processor, for example, in the control unit 240, the metrology module 230, or the lithography module 220 (see fig. 6A, 6B, 7A, and 7B). Certain embodiments include a computer program product comprising a computer readable storage medium having a computer readable program embodied therewith and configured to perform the relevant stages of the method 100. Certain embodiments include a target design file for a respective metrology target 210 as disclosed herein. The method 100 may include the following stages regardless of the order thereof.

The method 100 may include: in the design phase, the metrology imaging and/or scatterometry target is designed to have a one-to-one segmented and one unsegmented periodic structure at least at its previous layers (stage 105). It should be noted that in certain embodiments, segmented periodic structures may be segmented at device spacing, while unsegmented periodic structures may be partially or fully segmented, but not at device spacing, e.g., at a larger amplitude scale that does not experience similar process errors as devices. In some embodiments, the different periodic structures 214A, 214B may differ in their layout style, for example, in one or more parameters of the segmentation characteristics (e.g., pitch, CD-CD, possibly pattern) and/or in one or more parameters of the periodic structure characteristics (e.g., pitch, CD-CD, possibly pattern).

FIG. 1B schematically illustrates a process control method 100 that includes measuring process overlay by adding a pre-lithographic overlay measurement (e.g., any one of 110-114) during process execution, such as after a previous post-processing step 80, and feeding forward the measurement 120 into a successive lithographic step 85, such as correcting the NZO (non-zero offset) based on, for example, quality advantages or error bars. Periodic metrology measurements 87, such as post-development inspection (ADI), may be performed continuously. The intermediate measurements may be based on overlay differences between the target layout before and after the previous post-processing step 80, as shown by way of example below, to indicate and at least partially quantify process effects on overlay.

The process control method 100 includes deriving metrology measurements from the periodic structure at the previous layer directly after production of the periodic structure at the previous layer and before production of the periodic structure at the current layer (stage 110), and using the derived measurements to adjust at least a lithography stage that is part of the production of the current layer (stage 120).

For example, the derived metrology measurements may include at least overlay measurements with respect to two different periodic structures in previous layers (see examples below). In particular, two different periodic structures may be segmented differently, e.g., one periodic structure may be segmented at device intervals (see below, periodic structure 214A), while the other periodic structure may be unsegmented (see below, periodic structure 214B). Since process overlay error is dominated by structure size and fine segmentation, overlay offset between two aligned structures can be characterized, and process overlay error can be computed and possibly corrected or reduced even before the metrology target 210 is fully produced (see FIG. 1B).

The process control method 100 may further include deriving metrology measurements from the periodic structure at the previous layer after applying the etch phase to the periodic structure at the previous layer and before production of the periodic structure at the current layer (stage 112). The derived metrology measurements may include at least overlay measurements on periodic structures in previous layers before and after the etch phase.

In certain embodiments, the metrology target 210 may comprise an imaging target comprising two layers, three layers, or more. For example, the imaging target 210 may include at least three layers (210A, 210B, 210C, see, e.g., fig. 3 and 4) of the wafer 90, and the process control method 100 may be performed after production of a first of the three layers and after production of a second of the three layers (stage 114).

In certain embodiments, metrology target 210 may comprise a scattering target comprising at least two grating-over-grating targets (210D, 210E, see fig. 2C, 5, 7A, and 7B) having their previous layers 210A produced side-by-side on wafer 90 for metrology measurement derivation.

It should be noted that the elements of the following figures may be combined in any operable combination and that the description of certain elements in certain figures, but not in others, is for illustrative purposes only and is not limiting.

Fig. 2A through 2C are high-level schematic diagrams of design principles suitable for metrology targets 210, according to some embodiments of the invention. The metrology target 210 includes at least two pairs 212 of periodic structures 214, at least one pair at a previous layer 210A and at least another pair in a current layer 210C. In each pair 212, one periodic structure 214A is segmented with device-like segmentation, while the other periodic structure 214B is not segmented. The metrology target 210 may include an imaging target having two or three pairs of periodic structures in each of two measurement directions (see, e.g., fig. 3 and 4). Metrology target 210 may comprise a scatterometry target having two side-by-side grating-over-grating periodic structures along at least one measurement direction (see, e.g., fig. 2C, 5, 7A, and 7B).

Fig. 2A schematically illustrates a pair 212 of a segmented periodic structure 214A and an unsegmented periodic structure 214B, respectively, wherein the segmentation of the periodic structure 214A may have similarly-arranged segments. The pairs 212 may be used as independent metrology targets 210 and/or as elements in more complex metrology targets 210. FIG. 2B schematically illustrates a simplified imaging metrology target 210 having pairs 212 in two measurement directions (denoted X and Y) in a previous layer 210A, and a similar regular periodic structure (e.g., segmented or unsegmented) within each pair in a current layer 210B. The imaging metrology target 210 may include more than two pairs 212 of periodic structures 214 in each of the two measurement directions (X, Y), e.g., the imaging metrology target 210 may further include two pairs 212 of previous layers 210A in each measurement direction configured to enable measurement of the produced structures before and after the etch stage (see, e.g., fig. 3 and 4). FIG. 2C schematically illustrates a simplified scatterometry target 210 having two side-by-side grating-over-grating periodic structures 210D, 210E along at least one measurement direction. The gratings (periodic structures) of the targets 210D, 210E at the previous layer 210B may be segmented differently (e.g., segmented periodic structures 214A with a device pitch and unsegmented periodic structures 214B with an unsegmented or segmented pitch greater than the device pitch).

The disclosed target design files and metrology measurements of metrology target 210 are also part of this disclosure. It should be noted that the disclosed metrology targets 210 are depicted in fig. 2A-C in a non-limiting manner as mask patterns, and that actual printed targets may differ from mask designs due to OPC (optical proximity correction) modifications and process characteristics, including process errors measured by the disclosed method 200.

Fig. 3 and 4 are high-level schematic diagrams of a post-production metrology target 210 with respect to the disclosed measurement method 100, in accordance with some embodiments of the present invention. In a non-limiting example, the metrology target 210 includes a TAIM (triple AIM-advanced imaging metrology) target with three sets of periodic structures-a previous layer 210A, an etched previous layer 210B, and a current layer (e.g., resist) 210C. In each layer, pairs of periodic structures in each measurement direction (e.g., X and Y, corresponding to the scanner axis) are used to derive corresponding coverage measurements. It should be noted that to improve accuracy and performance, a variety of illumination and collection schemes may be used. In order to obtain sufficient imaging signal analysis information, a relatively large target spacing is required. While coverage can be computed in conventional methods, imaging coverage of previous layer structures can be computed using a modified algorithm designed according to the disclosed target structure (e.g., for different periodic structures in 212).

As schematically illustrated in fig. 3 and 4, components or albeit periodic structures may not be printed or etched away due to process errors. The different production of the corresponding segmented periodic structure 214A and the non-segmented periodic structure 214B, respectively, may be used to indicate the process errors involved and enable at least partial correction of the process errors even before printing the current layer 210B.

FIG. 5 is a high-level schematic diagram of metrology scatterometry targets 210D, 210E designed to be printed side-by-side to employ the process control method 100, according to some embodiments of the invention. The metrology scatterometry targets 210D, 210E may be configured to share periodic structures in at least one layer 210A, such as a previous layer from which process errors may be derived by measuring periodic structures of different segments (see also fig. 2C, 7A and 7B). In certain embodiments, the correlation between the imaging coverage results and the scatterometry coverage results may be used as a quality advantage of the NZO (non-zero offset) and/or error bar estimation.

Fig. 6A, 6B, 7A, and 7B are high-level schematic diagrams of a production system 250 according to some embodiments of the invention. The production system 250 includes: at least one lithography tool 220 configured to prepare the wafer 90 by producing layers of the wafer; a metrology tool 230 configured to derive metrology measurements from the periodic structure 214 at the previous layer 210A of the metrology target 210 directly after production of the previous layer periodic structure and before production of the periodic structure 214 at the current layer 210C of the metrology target 210; and a control unit 240 (which may be independent, as part of the lithography tool 220) and/or as part of the metrology tool 230) configured to use the derived measurements to adjust the lithography tool 220 at least with respect to a lithography stage as part of the production of the current layer 210C of the metrology target 210.

The metrology target 210 may include at least two pairs 212 of periodic structures 214, at least one pair 212 at a previous layer 210A and at least another pair 212 in a current layer 210B, where in each pair 212, one periodic structure is segmented with device-like segmentation while the other periodic structure is not segmented.

For example, fig. 6A and 6B respectively illustrate an imaged object 210 produced layer by a lithography tool 220, wherein a metrology tool 230 provides measurements after production of a previous (first) layer 210A, as schematically illustrated in fig. 6A, which may be used to adjust production parameters of a continuous current (second) layer 210B by the lithography tool, as schematically illustrated in fig. 6B. It should be noted that the imaging target 210 may include more than two layers with corresponding adjustments of the measurement and production adjustment processes.

In another example, fig. 7A and 7B respectively illustrate scatterometry targets 210 produced layer-by-layer by a lithography tool 220, wherein a metrology tool 230 provides measurements after production of a previous (first) layer 210A, as schematically illustrated in fig. 7A, which may be used to adjust production parameters of a continuous current (second) layer 210B by the lithography tool, as schematically illustrated in fig. 7B. It should be noted that the scatterometry target 210 may include more than two layers with corresponding adjustments of the measurement and production adjustment processes. Two scatterometry targets 210 may be produced side-by-side to provide sufficient periodic structures in at least the previous layer 210A to implement the disclosed process.

Advantageously, the disclosed process overcomes the disadvantages of conventional metrology methods based on post-lithographic measurements of structure coverage. While prior art approaches only provide feedback overlay control due to wafer-to-wafer variations, which results in poor ability to control the process window, the disclosed embodiments enable different populations of device structures within a device to be represented, accurately reflect the state of actual device features in the die, and thus enable operation under tighter overlay budgets and on-product overlays (OPOs). While prior art approaches are limited in their ability to accurately reflect the actual device feature state in the die (due to differences in process loads, pattern densities, or distortion fields, as no metrology measurements are made on similar structures and similar locations), the disclosed embodiments may be used in a structure-specific manner to provide spatially differentiated coverage measurements. The disclosed ability to adjust the lithography process during production also reduces overall errors and enhances the accuracy and precision of the production and metrology processes.

Various aspects of the present invention are described above with reference to flowchart illustrations and/or partial diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each part of the flowchart illustrations and/or part of the figures, and combinations of parts in the flowchart illustrations and/or part of the figures, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or partial diagram or portions thereof.

These computer program instructions may also be stored in a computer-readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or partial diagram or portion thereof.

The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or partial diagram or portion thereof.

The above-mentioned flow charts and diagrams illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each portion of the flowchart or partial diagram may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the section may occur out of the order noted in the figures. For example, two components shown in succession may, in fact, be executed substantially concurrently, or the components may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each portion of the partial figures and/or flowchart illustration, and combinations of portions in the partial figures and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In the foregoing description, embodiments are examples or implementations of the invention. The various appearances of "one embodiment," "certain embodiments," or "some embodiments" are not necessarily all referring to the same embodiments. While various features of the invention may be described in the context of a single embodiment, these features may also be provided separately or in any suitable combination. Conversely, although the invention may be described in the context of separate embodiments for clarity, the invention may also be implemented in a single embodiment. Certain embodiments of the invention may include features from different embodiments described above, and certain embodiments may include elements from other embodiments described above. Disclosure of elements of the invention in the context of particular embodiments should not be construed as limiting its use in particular embodiments only. Further, it is to be understood that the invention may be practiced or practiced in various ways and that the invention may be practiced in certain embodiments other than those outlined in the description above.

The invention is not limited to these figures or the corresponding description. For example, the flows need not move in each illustrated box or state, or in exactly the same order as illustrated and described. Unless defined otherwise, the meanings of technical and scientific terms used herein are generally understood by those of ordinary skill in the art to which the invention belongs. While the invention has been described with respect to a limited number of embodiments, these should not be construed as limitations on the scope of the invention, but rather as exemplifications of some of the preferred embodiments. Other possible variations, modifications, and applications are also within the scope of the invention. Accordingly, the scope of the present invention should not be limited by what has been described so far, but should be limited only by the appended claims and their legal equivalents.