阅读说明：本技术 用于毫米波5g通信的具有可重配置带宽的宽带低噪声放大器(lna) (Wideband Low Noise Amplifier (LNA) with reconfigurable bandwidth for millimeter wave 5G communications ) 是由 黄敏祐 王�华 托马斯·陈 迟太运 于 2019-05-21 设计创作，主要内容包括：根据一个实施例,低噪声放大器(LNA)电路包括第一放大器级,该第一放大器级包括：第一晶体管；第二晶体管,其耦接至第一晶体管；第一电感器,其耦接在输入端口与第一晶体管的栅极之间；以及第二电感器,其耦接至第一晶体管的源极,其中,第一电感器和第二电感器分别与第一晶体管的栅极电容谐振以用于双谐振。LNA电路包括第二放大器级,该第二放大器级包括：第三晶体管；第四晶体管,其耦接在第三晶体管与输出端口之间；以及无源网络,其耦接至第三晶体管的栅极。LNA电路包括电容器,其耦接在第一放大器级与第二放大器级之间,其中,电容器将无源网络的阻抗变换至第一放大器级的最佳负载。(According to one embodiment, a Low Noise Amplifier (LNA) circuit includes a first amplifier stage comprising: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled between the input port and the gate of the first transistor; and a second inductor coupled to a source of the first transistor, wherein the first inductor and the second inductor respectively resonate with a gate capacitance of the first transistor for dual resonance. The LNA circuit comprises a second amplifier stage comprising: a third transistor; a fourth transistor coupled between the third transistor and the output port; and a passive network coupled to the gate of the third transistor. The LNA circuit comprises a capacitor coupled between the first amplifier stage and the second amplifier stage, wherein the capacitor transforms the impedance of the passive network to an optimal load for the first amplifier stage.)

1. An LNA circuit (low noise amplifier circuit) comprising:

a first amplifier stage comprising:

a first transistor;

a second transistor coupled to the first transistor;

a first inductor coupled between an input port and a gate of the first transistor; and

a second inductor coupled to a source of the first transistor, wherein the first and second inductors are each resonant with a gate capacitance of the first transistor for dual resonant input matching;

a second amplifier stage comprising:

a third transistor;

a fourth transistor coupled between the third transistor and an output port; and

a passive network coupled to a gate of the third transistor; and

a capacitor coupled between the first amplifier stage and the second amplifier stage, wherein the capacitor transforms an impedance of the passive network to an optimal load for the first amplifier stage.

2. The LNA circuit of claim 1, further comprising a third inductor coupled between the first and second transistors for a C-L-C transmission line of the first amplifier stage to pass signals from the first transistor to the second transistor.

3. The LNA circuit of claim 1, further comprising a variable gain controller coupled to the first amplifier stage to control the gain of the first amplifier stage.

4. The LNA circuit of claim 1, further comprising a fourth inductor coupled to the drain of the second transistor to resonate with the drain capacitance of the second transistor at a first resonance.

5. The LNA circuit of claim 1, wherein the passive network comprises a fifth inductor in parallel with a first resistor.

6. The LNA circuit of claim 1, further comprising a sixth inductor coupled between the third transistor and the fourth transistor for a C-L-C transmission line of the second amplifier stage to pass an amplifier signal from the third transistor to the fourth transistor.

7. The LNA circuit of claim 1, further comprising a transformer-based balun coupled between the output port and the fourth transistor, wherein a primary winding of a transformer of the transformer-based balun is resonant with a drain capacitance of the fourth transistor at a second resonance.

8. The LNA circuit of claim 1, further comprising a first capacitor bank coupled in parallel with the first inductor.

9. The LNA circuit of claim 8, further comprising a second capacitor bank coupled in parallel with a fourth inductor.

10. The LNA circuit of claim 9, further comprising a third capacitor bank coupled in parallel with the capacitor.

11. The LNA circuit of claim 10, further comprising a fourth capacitor bank coupled in parallel with the primary winding of the transformer-based balun.

12. The LNA circuit of claim 11, wherein the first, second, third and fourth capacitor banks are programmable capacitors.

13. The LNA circuit of claim 11, wherein the first, second, third and fourth capacitor banks are digitally tunable capacitors.

14. An RF receiver circuit comprising an LNA circuit for amplifying a received signal, the LNA circuit comprising:

a first amplifier stage comprising:

a first transistor;

a second transistor coupled to the first transistor;

a first inductor coupled between an input port and a gate of the first transistor; and

a second inductor coupled to a source of the first transistor, wherein the first and second inductors are each resonant with a gate capacitance of the first transistor for dual resonant input matching;

a second amplifier stage comprising:

a third transistor;

a fourth transistor coupled between the third transistor and an output port; and

a passive network coupled to a gate of the third transistor; and

a capacitor coupled between the first amplifier stage and the second amplifier stage, wherein the capacitor transforms an impedance of the passive network to an optimal load for the first amplifier stage.

15. The RF receiver circuit of claim 14, further comprising a third inductor coupled between the first transistor and the second transistor for a C-L-C transmission line of the first amplifier stage to pass an amplifier signal from the first transistor to the second transistor.

16. The RF receiver circuit of claim 14, further comprising a variable gain controller coupled to the first amplifier stage to control a gain of the first amplifier stage.

17. The RF receiver circuit of claim 14, further comprising a fourth inductor coupled to the second transistor to resonate with a drain capacitance of the second transistor at a first resonance.

18. The RF receiver circuit of claim 14 wherein the passive network includes a fifth inductor in parallel with a first resistor.

19. The RF receiver circuit of claim 14, further comprising a sixth inductor coupled between the third transistor and the fourth transistor for a C-L-C transmission line of the second amplifier stage to pass an amplifier signal from the third transistor to the fourth transistor.

20. An RF front-end circuit, i.e. a radio frequency front-end circuit, comprising an RF receiver for receiving RF signals, the RF receiver comprising an LNA for amplifying received RF signals, the LNA comprising:

a first amplifier stage comprising:

a first transistor;

a second transistor coupled to the first transistor;

a first inductor coupled between an input port and a gate of the first transistor; and

a second inductor coupled to a source of the first transistor, wherein the first and second inductors are each resonant with a gate capacitance of the first transistor for dual resonant input matching;

a second amplifier stage comprising:

a third transistor;

a fourth transistor coupled between the third transistor and an output port; and

a passive network coupled to a gate of the third transistor; and

a capacitor coupled between the first amplifier stage and the second amplifier stage, wherein the capacitor transforms an impedance of the passive network to an optimal load for the first amplifier stage.

Technical Field

Embodiments of the present invention relate generally to wireless communication devices. More particularly, embodiments of the invention relate to a wideband Low Noise Amplifier (LNA) with reconfigurable bandwidth for a communication device.

Background

For next generation 5G communication devices, many applications such as Augmented Reality (AR)/Virtual Reality (VR) and 5G Multiple Input Multiple Output (MIMO) require higher data rates. The shift in design to millimeter wave (mm-wave) frequencies supports this higher data rate. On the other hand, a wider bandwidth is required to facilitate higher data rates. For example, the wider bandwidth should cover the 5G spectrum including the 24, 28, 37 and 39GHz bands.

Conventional RF front-end LNA circuits have limited performance at high frequency operation due to the high frequency parasitics of the LNA components. This typically results in a lower bandwidth, input impedance mismatch and degraded noise figure of the RF front-end circuit.

Drawings

Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

Fig. 1 is a block diagram illustrating an example of a wireless communication device according to one embodiment.

Fig. 2 is a block diagram illustrating an example of an RF front end integrated circuit in accordance with one embodiment.

Fig. 3 is a block diagram illustrating an RF transceiver integrated circuit in accordance with one embodiment.

Figure 4 is a block diagram illustrating an example of a wideband receiver circuit in accordance with one embodiment.

Fig. 5 is a block diagram illustrating a wideband IQ generation circuit according to one embodiment.

Fig. 6 is a block diagram illustrating a wideband IQ mixer according to one embodiment.

Fig. 7A shows a simulation plot of conversion gain versus Local Oscillator (LO) frequency between 20 to 45GHz for the mm-wave IQ generation circuit of fig. 5 and the wide-band IQ mixer of fig. 6 of a co-design, according to one embodiment.

Fig. 7B shows a simulation plot of conversion gain versus Intermediate Frequency (IF) between 0 and 8GHz for the mm-wave IQ generation circuit of fig. 5 and the wide-band IQ mixer of fig. 6 of a co-design, according to one embodiment.

Fig. 8 illustrates a three-dimensional model of a differential inductor pair according to one embodiment.

Fig. 9 shows a layout model of double balanced mixers each with a differential inductor pair according to one embodiment.

Fig. 10 is a block diagram illustrating a poly-phase filter (PPF) circuit according to one embodiment.

Fig. 11 is a simulation diagram illustrating image rejection ratio versus RF frequency of 22 to 39GHz at a fixed IF frequency of 3.5GHz for the wideband receiver circuit of fig. 4, according to one embodiment.

Fig. 12 is a block diagram illustrating an RF transceiver integrated circuit in accordance with one embodiment.

Fig. 13A-13B are block diagrams illustrating examples of transceiver switches according to some embodiments.

Fig. 14A is a block diagram illustrating an exemplary wideband LNA circuit according to one embodiment.

Fig. 14B is a diagram illustrating the S parameter (S11) for a wideband LNA circuit according to one embodiment.

Fig. 14C is a graph illustrating conversion gain (S parameters S21 and S31) for a wideband LNA circuit according to an embodiment.

Fig. 15A is a block diagram illustrating an exemplary wideband LNA circuit without a co-designed matching network, according to one embodiment.

Fig. 15B is a block diagram illustrating the S-parameters (S11) of a wideband LNA circuit without a co-designed matching network, according to one embodiment.

Fig. 16A is a block diagram illustrating an exemplary wideband LNA circuit with a co-designed matching network according to one embodiment.

Fig. 16B is a block diagram illustrating the S-parameters (S11) of a wideband LNA circuit with a co-designed matching network according to one embodiment.

Fig. 17A is a graph illustrating conversion gain for the first stage LC resonance and the second stage LC resonance of the wideband LNA circuit according to an embodiment.

Fig. 17B is a graph illustrating conversion gain for the combined first stage LC resonance and second stage LC resonance of a wideband LNA circuit according to an embodiment.

Fig. 18A is a block diagram illustrating an example EM model for a wideband LNA circuit, according to one embodiment.

Fig. 18B is a block diagram illustrating an example EM layout for a wideband LNA circuit, according to one embodiment.

Fig. 19A is a block diagram illustrating an example wideband LNA circuit, according to one embodiment.

Fig. 19B is a graph illustrating conversion gains of the first amplifier stage, the second amplifier stage, and the impedance transformation stage of the wideband LNA circuit according to one embodiment.

Detailed Description

Various embodiments and aspects of the inventions will be described with reference to details discussed below, and the accompanying drawings will illustrate the various embodiments. The following description and drawings are illustrative of the invention and are not to be construed as limiting the invention. Numerous specific details are described to provide a thorough understanding of various embodiments of the invention. However, in certain instances, well-known or conventional details are not described in order to provide a concise discussion of embodiments of the present inventions.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

Note that in the respective drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more constituent signal paths and/or have arrows at one or more ends to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, these lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or logic cell. As indicated by design requirements or preferences, any represented signal may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

Throughout the present specification, and in the claims, the term "connect" means a direct electrical connection between what is connected, without any intermediate means. The term "couple" means either a direct electrical connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term "circuitry" means one or more passive and/or active components arranged to cooperate with each other to provide a desired function. The term "signal" means at least one current signal, voltage signal, or data/clock signal. The meaning of "a", "an" and "the" includes plural references. The meaning of "in …" includes "in …" and "on …".

As used herein, unless otherwise specified the use of the ordinal adjectives "first", "second", and "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. The term "substantially" herein means within 10% of the target.

For purposes of the embodiments described herein, unless otherwise specified, these transistors are Metal Oxide Semiconductor (MOS) transistors that include a drain terminal, a source terminal, a gate terminal, and a bulk terminal. The source terminal and the drain terminal may be the same terminal and are used interchangeably herein. Those skilled in the art will recognize that other transistors may be used, such as bipolar junction transistors-BJTs PNP/NPN, BiCMOS, CMOS, etc., without departing from the scope of the present invention.

According to a first aspect, a Low Noise Amplifier (LNA) circuit comprises a first amplifier stage comprising: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled between the input port and the gate of the first transistor; and a second inductor coupled to the source of the first transistor, wherein the first and second inductors are respectively resonant with a gate capacitance (e.g., Cgs or Cgd) and/or a source capacitance (e.g., Cgs or Cds) of the first transistor for dual resonant input matching. The LNA circuit comprises a second amplifier stage comprising: a third transistor; a fourth transistor coupled between the third transistor and the output port; and a passive network coupled to the gate of the third transistor. The LNA circuit comprises a capacitor coupled between the first amplifier stage and the second amplifier stage, wherein the capacitor transforms the gate capacitance of the third transistor and/or the impedance of the passive network to an optimal load of the first amplifier stage.

In one embodiment, the LNA circuit further comprises a third inductor coupled between the first transistor and the second transistor for a C-L-C transmission line of the first amplifier stage to pass the signal from the first transistor to the second transistor. In one embodiment, the LNA circuit further comprises a variable gain controller coupled to the first amplifier stage to control the gain of the first amplifier stage. In one embodiment, the LNA circuit further comprises a fourth inductor coupled to the drain of the second transistor to resonate with the drain capacitance of the second transistor at the first resonance. In one embodiment, among others, the passive network includes a fifth inductor in parallel with the first resistor.

In one embodiment, the LNA circuit further comprises a sixth inductor coupled between the third transistor and the fourth transistor for the C-L-C transmission line of the second amplifier stage to pass the amplifier signal from the third transistor to the fourth transistor. In one embodiment, the LNA circuit further comprises a transformer-based balun (transformer-based balun) coupled between the output port and the fourth transistor, wherein a primary winding of a transformer of the transformer-based balun is resonant with a drain capacitance of the fourth transistor at a second resonance.

In one embodiment, the LNA circuit further comprises a first capacitor bank coupled in parallel with the first inductor. In another embodiment, the LNA circuit further comprises a second capacitor bank coupled in parallel with the fourth inductor. In another embodiment, the LNA circuit further comprises a third capacitor bank coupled in parallel with the capacitor. In another embodiment, the LNA circuit further comprises a fourth capacitor bank coupled in parallel with the primary winding of the transformer-based balun. In another embodiment, the first capacitor bank, the second capacitor bank, the third capacitor bank, and the fourth capacitor bank are programmable capacitors. In another embodiment, the first, second, third and fourth capacitor banks are digital (or analog-based) tunable capacitors.

According to a second aspect, an RF receiver circuit comprises an LNA circuit for amplifying a received signal, the LNA circuit comprising a first amplifier stage comprising: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled between the input port and the gate of the first transistor; and a second inductor coupled to the source of the first transistor, wherein the first and second inductors are respectively resonant with a gate capacitance (e.g., Cgs or Cgd) and/or a source capacitance (e.g., Cgs or Cds) of the first transistor for dual resonant input matching. The LNA circuit includes: a second amplifier stage, the second amplifier stage comprising: a third transistor; a fourth transistor coupled between the third transistor and the output port; and a passive network coupled to the gate of the third transistor. The LNA circuit comprises a capacitor coupled between the first amplifier stage and the second amplifier stage, wherein the capacitor transforms the gate capacitance of the third transistor and/or the impedance of the passive network to an optimal load of the first amplifier stage.

According to a third aspect, the RF front-end circuit comprises an RF receiver for receiving RF signals, the RF receiver comprising an LNA RF receiver circuit comprising an LNA circuit for amplifying the received RF signals, the LNA circuit comprising a first amplifier stage comprising: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled between the input port and the gate of the first transistor; and a second inductor coupled to the source of the first transistor, wherein the first and second inductors are respectively resonant with a gate capacitance (e.g., Cgs or Cgd) and/or a source capacitance (e.g., Cgs or Cds) of the first transistor for dual resonant input matching. The LNA circuit comprises a second amplifier stage comprising: a third transistor; a fourth transistor coupled between the third transistor and the output port; and a passive network coupled to the gate of the third transistor. The LNA circuit comprises a capacitor coupled between the first amplifier stage and the second amplifier stage, wherein the capacitor transforms the gate capacitance of the third transistor and/or the impedance of the passive network to an optimal load of the first amplifier stage.

Fig. 1 is a block diagram illustrating an example of a wireless communication apparatus according to an embodiment of the present invention. Referring to fig. 1, a wireless communication apparatus 100 (also simply referred to as a wireless apparatus) includes an RF front-end module 101, a baseband processor 102, and the like. The wireless device 100 may be any type of wireless communication device, such as a mobile phone, a laptop computer, a tablet computer, a network equipment device (e.g., an internet of things or IOT device), and so forth.

In radio receiver circuits, the RF front end is a generic term for the antenna up to and including all circuits between the mixer stages. The RF front-end consists of all components in the receiver that process the original input radio frequency signal before converting it to a lower frequency (e.g., IF). In microwave and satellite receivers, the RF front-end is commonly referred to as a low-noise block (LNB) or low-noise down converter (LND) and is typically located at the antenna so that the signal from the antenna can be transmitted to the rest of the receiver at an intermediate frequency that is easier to handle. The baseband processor is the device (chip or part of a chip) in the network interface that manages all radio functions (all functions that require the antenna).

In one embodiment, the RF front-end module 101 includes one or more RF transceivers, wherein each RF transceiver transmits and receives RF signals within a particular frequency band (e.g., a particular frequency range such as a non-overlapping frequency range) via one of a plurality of RF antennas. The RF front-end IC chip also includes an IQ generator and/or a frequency synthesizer coupled to the RF transceiver. An IQ generator or generation circuit generates and provides an LO signal to each RF transceiver to enable the RF transceivers to mix, modulate, and/or demodulate RF signals within a corresponding frequency band. The RF transceiver and the IQ generation circuit may be integrated within a single IC chip as a single RF front-end IC chip or package.

Fig. 2 is a block diagram illustrating an example of an RF front end integrated circuit according to one embodiment of the invention. Referring to fig. 2, the RF front end 101 includes an IQ generator and/or a frequency synthesizer 200, etc., coupled to a multiband RF transceiver 211. The transceiver 211 is configured to transmit and receive RF signals within one or more frequency bands or a wide range of RF frequencies via the RF antenna 221. In one embodiment, transceiver 211 is configured to receive one or more LO signals from IQ generator and/or frequency synthesizer 200. LO signals are generated for one or more respective frequency bands. The LO signals are used by the transceiver to mix, modulate, and demodulate to transmit and receive RF signals in the corresponding frequency bands. Although only one transceiver and antenna is shown, multiple pairs of transceivers and antennas may be implemented, with one pair for each frequency band.

Fig. 3 is a block diagram illustrating an RF transceiver Integrated Circuit (IC) according to one embodiment. RF transceiver 300 may represent RF transceiver 211 of fig. 2. Referring to fig. 3, frequency synthesizer 200 may represent frequency synthesizer 200 as described above. In one embodiment, RF transceiver 300 may include a frequency synthesizer 200, a transmitter 301, and a receiver 302. Frequency synthesizer 200 is communicatively coupled to a transmitter 301 and a receiver 302 to provide LO signals. The transmitter 301 may transmit RF signals of multiple frequency bands. Receiver 302 may receive RF signals in multiple frequency bands.

Receiver 302 includes a Low Noise Amplifier (LNA)306, a mixer 307, and a filter 308. LNA306 is used to receive RF signals from a remote transmitter via antenna 221 and amplify the received RF signals. The amplified RF signal is then demodulated by a mixer 307 (also referred to as a down-conversion mixer) based on the LO signal provided by the IQ generator 317. IQ generator 317 may represent an IQ generator of IQ generator/synthesizer 200 as described above. In one embodiment, IQ generator 317 is integrated into wideband receiver 302 as a single integrated circuit. The demodulated signal is then processed by a filter 308, which filter 308 may be a low pass filter. In one embodiment, the transmitter 301 and receiver 302 share an antenna 221 via a transmit and receive (T/R) switch 309. The T/R switch 309 is configured to switch between the transmitter 301 and the receiver 302 to couple the antenna 221 to either the transmitter 301 or the receiver 302 at a particular point in time. Although a pair of transmitter and receiver is shown, multiple pairs of transmitter and receiver and/or independent receivers may be implemented.

Fig. 4 is a block diagram illustrating an example of a wideband LNA306, a wideband IQ mixer 307, and a filter 308. The filter 308 may be a two-stage resistor-capacitor (e.g., RC-CR) polyphase filter. The filter 308 may include one or more variable gain Intermediate Frequency (IF) amplifiers for additional power gain. Note that the wideband IQ mixer 307 may be designed in cooperation with the wideband IQ generation circuit 317 as a single unit. Wideband IQ mixer 307 may also include matching network 318 for impedance matching between LNA306 and mixer 307.

Fig. 5 is a block diagram illustrating a mm-wave broadband IQ generation circuit according to one embodiment. Referring to fig. 5, a wideband IQ generation circuit 317 may generate IQ signals (e.g., LO _ Ip, LO _ Qp, LO _ In, and LO _ Qn) based on differential LO signals (e.g., LO _ Ip and LO _ In) over a wide frequency range. IQ generation circuit 317 introduces a 90 degree phase shift to the LO signal to generate signals in four phase quadrants. The IQ signal may then be used by an IQ mixer to modulate an RF signal with IQ data to a lower frequency signal (e.g., an IF signal).

Fig. 6 is a block diagram illustrating a wideband IQ mixer according to one embodiment. A mixer is a three-port device capable of frequency conversion or modulation of a signal. For the receiver, the mixer down-converts (or demodulates) the RF signal using the LO signal to generate an IF signal. Referring to fig. 6, mixer 307 includes two (or dual) balanced Gilbert (Gilbert) mixers 620 and 621. Double balanced mixer 620-621 down-converts (or demodulates) the differential RF signal using the differential LO signal to generate a differential IF signal. For example, mixer 620 receives RF _ inp, RF _ inn, and differential In-phase signals (e.g., LO _ Ip and LO _ In) generated by a mm-wave wideband IQ generation circuit (such as IQ generator 317 of fig. 5) to generate IF _ Ip and IF _ In. Similarly, mixer 621 receives RF _ inp, RF _ inn, and differential quadrature signals (e.g., LO _ Qp and LO _ Qn) generated by a mm-wave wideband IQ generation circuit (such as IQ generator 317 of fig. 5) to generate IF _ Qp and IF _ Qn. In some embodiments, mixers 620-621 may each include one or more differential amplifier stages.

Referring to fig. 6, for a two-stage differential amplifier, the amplifier may include a common source differential amplifier as a first stage and a gate-coupled differential amplifier as a second stage. The common-source differential amplifier stages of mixers 620 and 621 may each receive a differential signal RF _ inp and RF _ inn. The gates of mixer 620 are coupled to receive differential signals LO _ In and LO _ Ip from the differential amplifier stage. The gate of mixer 621 is coupled to the differential amplifier stage to receive the differential signals LO _ Qn and LO _ Qp. The RF signal is then down-converted by the LO signal to generate an IF signal. The second stage may include a low pass filter, which may be a first order low pass filter to minimize high frequency noise injection into the mixer 620-621. In one embodiment, the low pass filter comprises a passive low pass filter having a load resistor in parallel with a capacitor (e.g., capacitor 630). In one embodiment, the first stage differential amplifier is coupled to the second stage differential amplifier via a differential inductor (e.g., differential inductor 633). In one embodiment, mixer 620-621 is co-designed with a mm-wave IQ generation circuit (such as mm-wave IQ generation circuit 317 of FIG. 5) on a single monolithic integrated circuit.

Fig. 7A shows a simulation plot of conversion gain versus Local Oscillator (LO) frequency between 20 to 45GHz for the co-designed mm-wave IQ generation circuit of fig. 5 and the broadband IQ mixer of fig. 6, according to one embodiment. Referring to fig. 7A, with moderate differential power at the input of the IQ generation circuit (such as an LO signal with a differential power of about-2 dBm, etc.), the IQ mixer 307 may produce a down-conversion gain of approximately >7dB and an amplitude mismatch of approximately < 0.7dB over the LO frequency range of 23 to 43 GHz.

Fig. 7B shows a simulation plot of conversion gain versus Intermediate Frequency (IF) between 0 and 8GHz for the co-designed mm-wave IQ generation circuit of fig. 5 and the wide-band IQ mixer of fig. 6, according to one embodiment. Referring to fig. 6, the output load resistor of mixer 620/621 may be co-designed in parallel with input capacitor 630 to form a first order low pass filter, which input capacitor 630 may be the parasitic capacitance seen at the next IF amplifier stage (e.g., IF variable gain amplifier stage 308 of fig. 4). Referring to fig. 7B, based on the co-designed mm-wave IQ generation circuit and IQ mixer, the conversion gain attenuation can be reduced from a peak gain of about 7.6dB to about 0.5dB for an IF frequency designed at about 3.5 GHz.

Referring to fig. 6, a differential inductor pair 633 is used to obtain current gain between the two differential amplifier stages. Four inductors are included for good performance, e.g., two differential inductor pairs for each IQ mixer in a dual IQ mixer. However, four inductors comprise a large footprint. Fig. 8 illustrates a three-dimensional model of a differential inductor pair according to one embodiment. The differential inductor pair 800 may be the differential inductor pair 633 of fig. 6. In one embodiment, the differential inductor pair may be reduced to the footprint (footprint) of a single inductor, such as the differential inductor pair 800 of fig. 8. Referring to fig. 8, a differential inductor pair 800 includes two spiral inductors that are folded together to the footprint of a single inductor due to the fact that there is a virtual ground between the inductor pair, and thus, a ground plane (e.g., a ground plane surrounding the inductors) may be reused for the inductor pair to reduce the footprint of the inductor pair. In one embodiment, the differential inductor pair 800 may each have an inductance of about 200 pH. In one embodiment, the inductor pair has a footprint of about 165 μm by 85 μm.

Fig. 9 illustrates a layout model of double balanced mixers each having the differential inductor pair of fig. 8 according to one embodiment. Referring to fig. 9, the double balanced mixer 900 may be the IQ mixer 620-621 of fig. 6. As shown in fig. 9, two inductor pairs (e.g., 4 inductors total) are each coupled between the first stage amplifier and the second stage amplifier. The inductor pair applies inductance between the two stages to enhance current gain over the mm-wave frequency range. The inductors of the differential inductor pair share a virtual ground and have the footprint of a single inductor. In one embodiment, the mixer footprint is approximately 185 μm by 252 μm. FIG. 10 is a block diagram illustrating a polyphase filter (PPF) circuit according to one embodiment. PPF 308 may filter out higher frequency noise and may recombine the four In-phase and quadrature signals back into a differential pair of IF signals, e.g., IF _ Ip and IF _ In. In one embodiment, PPF 308 includes one or more amplifier stages to further amplify the IF signal. Referring to FIG. 10, in one embodiment, PPF 308 includes three stages. The first stage includes a differential amplifier 1001 to increase the power of IQ IF signals (e.g., IF _ Ip, IF _ In, IF _ Qp, and IF _ Qn). The second stage includes a resistor-capacitor-resistor (RC _ CR) PPF 1003. PPF 1003 may filter out undesired signal noise (e.g., high frequency noise outside of the IF frequency range) and may combine four In-phase and quadrature signals (e.g., IF _ Ip, IF _ In, IF _ Qp, and IF _ Qn) into a differential pair of IF signals (e.g., IF _ Ip and IF _ In). Finally, the third stage includes an amplifier 1005 to further amplify the differential IF signals IF _ Ip and IF _ In to generate IF _ out + and IF _ out-. The amplifier 1001 and the amplifier 1005 may be variable gain amplifiers to allow for gain adjustment of the PPF circuit 308.

Figure 11 is a simulation diagram illustrating image rejection ratio versus RF frequency from 22 to 39GHz at an IF frequency of about 3.5GHz for the wideband receiver circuit of figure 4 (e.g., receiver 302), according to one embodiment. The simulation setup included as inputs a differential LO with a drive power ranging from-2 to +3 dBm. At an IF frequency of about 3.5GHz, the broadband Image Rejection Ratio (IRR) is approximately >23dB for a frequency range of about 22 to 39 GHz. According to one embodiment, the broadband receiver 302 occupies approximately 1.36mm by 0.65 mm.

Fig. 12 is a block diagram illustrating an RF transceiver integrated circuit in accordance with one embodiment. RF transceiver 1200 may be transceiver 300 of fig. 3. In one embodiment, the RF transceiver 1200 includes a co-designed matching network 304 coupled between a T/R switch 309 and an LNA306 of the receiver 302. Matching network 304, in conjunction with T/R switch 309 and LNA306, may improve the performance of receiver 302.

Fig. 13A-13B are block diagrams illustrating examples of transceiver T/R switches according to some embodiments. Referring to FIG. 13A, LNA306 is coupled directly to T/R switch 309. Here, the input impedance of LNA306 is designed to match the output impedance of switch 309. However, the load capacitance (e.g., Coff) of the off switch of switch 309 and the load capacitance of PA 303 may load the input of the LNA directly, degrading the performance of receiver 302. FIG. 13B shows LNA306 coupled to T/R switch 309 via co-designed matching network 304. Network 304 may include an inductor (e.g., L-line) in series with an inductive transmission line (T-line) coupled between LNA306 and T/R switch 309_matching). The inductor may resonate with load capacitance and/or parasitic capacitance seen by the matching network to resonate at one or more resonant frequencies.

Fig. 14A is a block diagram illustrating an exemplary wideband LNA circuit according to one embodiment. An LNA is an amplifier that can amplify a low power RF signal without significantly reducing its signal-to-noise ratio. Referring to fig. 14A, LNA306 includes a first (amplifier) stage 1401 and a second (amplifier) stage 1402. The first stage 1401 may be implemented in a source-induced negative feedback topology (source-induced negative feedback topology) to achieve broadband input matching with high linearity, e.g., the source terminal of transistor M1 is coupled to inductor L2. The LNA based on the inductance degeneration common source stage can realize low noise coefficient.

IN one embodiment, the inductor L1 is coupled between the gate terminal of the transistor M1 and the input port (IN). Referring to fig. 14A, inductors L1, L2, together with the parasitic gate capacitance (e.g., Cgs and/or Cgd) and/or source capacitance of transistor M1, may be configured to resonate at double resonance for broadband input impedance matching. The inductive degeneration topology may include transistors M1 and M2 and a current gain peaking inductor (e.g., inductor L3) coupled between transistors M1 and M2. The inductor L3 is selected to form a C-L-C like transmission line with the parasitic capacitance (e.g., Cds) of the transistor M1 and the parasitic capacitance (e.g., Cgs) of M2 to transfer the high frequency amplified signal from the transistor M1 to the transistor M2. Without the inductor L3, the parasitic capacitance Cds of M1 and the parasitic capacitance Cgs of M2 would leak the RF current signal along M1-M2, which reduces the gain and reduces the noise figure of the overall LNA.

In one embodiment, the first stage 1401 may include a variable gain control for adjusting the gain of the first stage to adjust the input linearity of the LNA 306. The variable gain control may include a pnp transistor (e.g., PMOS) coupled to the drain terminal of transistor M2. The pnp transistor receives the LNA _ vctrl signal at the gate terminal for adjusting the gain control of the first stage. In one embodiment, inductor L4 is coupled to the drain terminal of transistor M2 (e.g., at the source and drain terminals of a pnp transistor) to resonate at a first resonant frequency or resonance.

For the second stage 1402, the signal 1404 is amplified by the M3 and M4 transistors. Similar to L3 and transistors M1 and M2, current gain peaking inductor L6 is inserted between the M3 and M4 transistors to form a C-L-C like transmission line with the parasitic capacitance (e.g., Cds) of transistor M3 and the parasitic capacitance (e.g., Cgs) of M4 as seen by inductor L6 to transfer the high frequency amplifier signal from M3 to M4. Similar to inductor L3, without inductor L6, parasitic capacitance Cds of M3 and parasitic capacitance Cgs of M4 would leak RF current signals along M3-M4, which reduces gain and lowers the noise figure of the overall LNA.

In one embodiment, the transformer-based balun 1405 is coupled to the drain terminal of M4, so the high frequency signal at the drain terminal of M4 may be converted from single-ended to differential (e.g., balanced) components (e.g., at ports Outp and Outn) by the transformer-based balun 1405. A balun is a type of transformer used to convert an unbalanced signal into a balanced signal or vice versa. A balanced signal comprises two signals carrying signals of equal magnitude but opposite phase. An unbalanced signal comprises a single signal that operates with respect to a ground signal. The balanced signal allows for balanced configuration of the next stage (e.g., mixer 307) to prevent RF-LO, LO-IF, and RF-IF signal leakage. Here, since the transformer-based balun 1405 is coupled to and next to the output ports of the LNA306 (e.g., at the second stage 1402, just before the output ports Outp and Outn), the passive losses of the transformer-based balun 1405 are minimized. Further, the primary winding inductance of the transformer-based balun may resonate with Cgs of the transistor M4 at the second resonant frequency. The second resonant frequency of the second stage in conjunction with the first resonant frequency of the first stage enables wideband frequency spreading for the corresponding conversion gain bandwidth.

In one embodiment, the gate terminal of transistor M3 is coupled to the passive network circuit. The passive network circuit may include an inductor L5 in parallel with a resistor R1. In one embodiment, C_{_conversion}The capacitor is coupled between the first stage (e.g., the drain terminal of transistor M2) and the second stage (e.g., the gate terminal of transistor M3). C_{_conversion}The gate capacitance (e.g., Cgs) of M3 and/or the impedance of the passive network circuit (e.g., L5 in parallel with R1) may be impedance transformed to the optimal load for the first stage. Note that although the LNA is shown as having only two stages, additional stages may be implemented, such as a three-stage LNA, etc.

Fig. 14B is a diagram illustrating the S parameter (S11) of an exemplary wideband LNA circuit according to one embodiment. Graph 1450 may be the S11 plot of LNA306 of fig. 14A. As shown by the S11 plot, LNA306 has dual resonances at 26GHz and 34GHz, which can be achieved by tuning inductors L1 and L2 of LNA306 of fig. 14A. S11 is about < -16dB at these two resonant frequencies and about < -10dB for a frequency range of about 25 to 40 GHz.

Fig. 14C is a graph illustrating conversion gain (or S parameters S21 and S31) of an example wideband LNA circuit, according to an embodiment. Referring to fig. 14C, a graph 1470 may be a conversion gain plot for LNA306 of fig. 14A. As shown, the single-ended to single-ended gain is approximately 14dB (e.g., S21 and S31 from input port 1 to output ports outp2 and outn 3). The differential to single-ended gain is approximately 17dB from the single-ended input port to the differential output port. Referring to FIGS. 14B through 14C, in one embodiment, the S11(> -10dB) bandwidth and the 3-dB S21 gain bandwidth cover a frequency range of about 27GHz to about 40 GHz.

Fig. 15A is a block diagram illustrating an exemplary wideband LNA circuit without a co-designed matching network according to one embodiment. Fig. 15B is a block diagram illustrating the S parameter (S11) of input matching for a wideband LNA circuit (e.g., fig. 15A) without a co-designed matching network according to one embodiment. In this case, once the LNA306 is loaded with the T/R switch 309 and the off-state Power Amplifier (PA)303 as shown in fig. 15A, the load capacitance and/or parasitic capacitance of the off-switch of the T/R switch 309 and the off-state PA 303 degrade the overall receiver performance as shown in fig. 15B. For the T/R switch 309, Ron models the on-resistance of the switch transistor, and Coff models the off-capacitance of the switch transistor. The overall receiver input matches S11> -10dB over a frequency range of about 20 to 49GHz (e.g., the entire frequency band of interest for 5G MIMO communications). In other words, most of the received signal is reflected rather than received by the receiver, resulting in sub-optimal performance (e.g., receiver bandwidth, conversion gain, sensitivity, noise figure, etc.) at mm-wave frequencies.

Fig. 16A is a block diagram illustrating an exemplary wideband LNA circuit with a co-designed matching network according to one embodiment. Fig. 16B is a block diagram illustrating the S-parameter (S11) of input matching for a wideband LNA circuit (e.g., fig. 16A) with a co-designed matching network according to one embodiment. Referring to fig. 16A, matching network 304 includes a transmission line (T-line) that bridges a T/R switch 309 to LNA 306.

In one embodiment, matching network 304 includes L_matchingWith capacitance (e.g., Coff) of T/R switch 309 and OFF state PA 303The capacitance resonates. Referring to fig. 15A, a capacitance C1 (about 1pF) is typically coupled to the input of the LNA to block DC signals received by the receiver, however, C1 may cause signal loss due to capacitive division between C1 and the parasitic capacitor seen at the gate node of transistor M1. Referring to fig. 16A, in one embodiment, matching network 304 includes a capacitor C2 coupled to the T-line. Here, in contrast, the capacitance C2 (about 270fF) can (1) create high order resonance with the T-line and the series gate inductor L1, and (2) block the DC signal at the front end of the receiver without signal loss due to capacitive voltage division.

In one embodiment, matching network 304 includes multiple resonant LC pairs, including (1) load capacitors from Coff and PA of the T/R switch and L_matchingA first LC pair that resonates, (2) a second LC pair from C2 and T-line and L1, and (3) a third LC pair from the gate-to-source parasitic capacitor of M1 and inductor L2. With multiple resonant LC pairs, the matching network 304 is similar to a high order chebyshev filter that can achieve broadband input matching of mm-waves. For example, referring to FIG. 16B, in one embodiment, the input match (S11) for the front-end switch viewing FIG. 16A may be about < -10dB for a frequency range of about 22.5GHz to 42 GHz. Here, S11 of fig. 16B includes a plurality of resonance frequencies, compared to fig. 15B, thereby expanding the useful bandwidth of the receiver using the T/R switch.

Fig. 17A is a graph illustrating conversion gain for the first stage LC resonance and the second stage LC resonance of the wideband LNA circuit according to an embodiment. Fig. 17B is a graph illustrating conversion gain for the combined first stage LC resonance and second stage LC resonance of a wideband LNA circuit according to an embodiment. For example, fig. 17A-17B may be conversion gain diagrams for the wideband LNA circuit 306 of fig. 14A.

Referring to fig. 17A, a graph 1700 shows gain bandwidth extension using a two-stage resonance point including a first resonance frequency f1 and a second resonance frequency f 2. Here, f1 may correspond to the frequency of the first stage LC resonance (e.g., 26GHz), and f2 may correspond to the frequency of the second stage LC resonance (e.g., 34 GHz). The frequency f1 may be roughly adjusted by selecting inductor L4, and the frequency f2 may be roughly adjusted by selecting the size of the transformer-based balun (e.g., adjusting the primary winding inductance of the transformer coupled to transistor M4). Referring to fig. 17B, a graph 1710 shows the overall conversion gain bandwidth of the LNA of fig. 17A for two-stage resonant frequencies f1 and f 2. Referring to fig. 17B, the conversion gain bandwidth covers a frequency range of approximately f1 to f 2. Here, by shifting and separating the two resonant frequencies f1 and f2, the LNA can be reconfigured for wideband operation to cover a wider bandwidth.

Fig. 18A is a block diagram illustrating an example EM model of a wideband LNA circuit in accordance with one embodiment. FIG. 18B is a block diagram illustrating an example EM layout of a wideband LNA circuit in accordance with one embodiment. Referring to fig. 18A-18B, an overall LNA model/layout including bypass capacitors may have a size of approximately 650 μm by 700 μm.

In one embodiment, a capacitor bank may be inserted near the resonant source, e.g., near the resonant inductor, to improve the operational frequency range of the LNA. Fig. 19A is a block diagram illustrating an example wideband LNA circuit, according to one embodiment. Referring to FIG. 19A, the LNA 1900 may be the LNA306 of FIG. 14A. In one embodiment, the LNA 1900 further includes a first capacitor bank coupled in parallel with the inductor L1. In another embodiment, the LNA 1900 includes a second capacitor bank coupled in parallel with the inductor L4. In another embodiment, LNA 1900 includes AND_{_conversion}A third capacitor bank coupled in parallel. In another embodiment, the LNA 1900 includes a fourth capacitor bank coupled across the primary winding of the transformer-based balun. In one embodiment, the first, second, third and fourth capacitor banks may be programmable capacitors or digital (or analog) tunable capacitors. By tuning the capacitors, the input matching dual resonance and/or the first and second resonant frequencies may be shifted to reconfigure the operating frequency range of the LNA 1900.

Fig. 19B is a graph illustrating conversion gains of the first amplifier stage, the second amplifier stage, and the impedance transformation stage of the wideband LNA circuit according to one embodiment. Graph 1950 may be a conversion gain graph of LNA 1900 of fig. 19A. Referring to fig. 19B, in one embodiment, tuning the first, second, third, and fourth capacitor banks may reconfigure the operating frequency of LNA 1900 to a frequency range of approximately 21GHz to 46GHz, which may be a 38% to 75% improvement over the frequency band of operation of LNA306 of fig. 14A as previously shown in fig. 14C. Thus, the additional capacitor bank may reconfigure the frequency response of the LNA to operate the LNA in a different frequency band or range.

In the foregoing specification, embodiments of the invention have been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of the invention as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.