阅读说明：本技术 一种无电容型ldo的瞬态响应增强电路 (Transient response enhancement circuit of no-capacitor LDO ) 是由 姚和平 汪西虎 唐威 苏海伟 于 2020-12-02 设计创作，主要内容包括：本发明涉及集成电路技术领域,尤其涉及一种无电容型LDO的瞬态响应增强电路,其中,包括：一输出控制支路,连接于一电压输入端和一电压输出端之间,以控制电压输入端的电压输入至电压输出端；一泄放支路,连接于电压输出端和地之间；一检测支路,连接于电压输出端和泄放支路之间,以检测电压输出端的输出电压；泄放支路用于提供一条输出到地的低阻通路,当输出电压出现尖峰脉冲时泄放支路打开,将输出电流中的瞬态尖峰电流泄放至地。有益效果：通过泄放支路将电压输出端的瞬态尖峰电流泄放至地,从而抑制电压输出端的电压上跳,达到增强LDO瞬态响应的目的,且通过设置输出控制支路,将输出极点移至高频处,提升LDO的频率稳定性,且结构简单、响应速度快,无需外接特定的电容及额外的外接电容引脚,可缩小芯片面积。(The invention relates to the technical field of integrated circuits, in particular to a transient response enhancement circuit of a capacitor-free LDO (low dropout regulator), which comprises: the output control branch circuit is connected between a voltage input end and a voltage output end so as to control the voltage of the voltage input end to be input to the voltage output end; the bleeder branch is connected between the voltage output end and the ground; the detection branch is connected between the voltage output end and the discharge branch so as to detect the output voltage of the voltage output end; the bleeder branch is used for providing a low-resistance path which is output to the ground, and is opened when the spike pulse occurs in the output voltage, so that the transient spike current in the output current is discharged to the ground. Has the advantages that: transient spike current of the voltage output end is discharged to the ground through the discharging branch circuit, so that voltage jump of the voltage output end is restrained, the purpose of enhancing the transient response of the LDO is achieved, the output pole is moved to a high-frequency position through the output control branch circuit, the frequency stability of the LDO is improved, the structure is simple, the response speed is high, external specific capacitors and additional external capacitor pins are not needed, and the area of a chip can be reduced.)

1. A transient response enhancement circuit for a capacitor-less LDO, comprising:

the output control branch circuit is connected between a voltage input end and a voltage output end and is used for controlling the voltage of the voltage input end to be input to the voltage output end;

the bleeder branch is connected between the voltage output end and the ground;

the detection branch is connected between the voltage output end and the discharge branch so as to detect the output voltage of the voltage output end;

when the detection branch circuit detects transient spike voltage in the output voltage, the effect of restraining overshoot of the output voltage is achieved through the discharge branch circuit.

2. The transient response enhancement circuit of claim 1, wherein said detection branch comprises:

and the source electrode of the first PMOS tube is connected to the voltage output end and forms the input end of the detection branch, the drain electrode of the first PMOS tube is connected to the input end of the discharge branch and forms the output end of the detection branch, and the control end of the first PMOS tube is connected with a feedback signal so as to detect the output voltage of the voltage output end.

3. The transient response enhancement circuit of claim 2, wherein the bleed branch comprises:

the first PMOS tube;

and the control end of the NMOS tube is connected to the drain electrode of the first PMOS tube, the drain electrode of the NMOS tube is connected to the voltage output end, and the source electrode of the NMOS tube is grounded and forms the output end of the bleeder branch.

4. The transient response enhancement circuit of claim 2, wherein said output control branch comprises:

the input end of the amplifier is connected to the drain electrode of the first PMOS tube;

and the control end of the second PMOS tube is connected with the output end of the amplifier, the source electrode of the second PMOS tube is connected to the voltage input end, and the drain electrode of the second PMOS tube is connected to the voltage output end and forms the output end of the output control branch.

5. The transient response enhancement circuit of claim 4, wherein said output control branch further comprises a feedback unit having an input connected to said voltage output and an output connected to said detection branch for outputting said feedback signal.

6. The transient response enhancement circuit of claim 5, wherein said feedback unit comprises a comparator having a first input terminal coupled to a reference voltage, a second input terminal coupled to a feedback voltage provided by said voltage output terminal, and an output terminal coupled to the control terminal of said first PMOS transistor.

7. The transient response enhancement circuit of claim 4, wherein said output control branch further comprises a current sink having an input connected to the drain of said first PMOS transistor and an output connected to ground for providing a bias current to said amplifier.

8. The transient response enhancement circuit of claim 7, wherein said sensing branch further comprises a resistor connected in parallel with said current sink and connected between the drain of said first PMOS transistor and ground.

9. The transient response enhancement circuit of claim 6, wherein said comparator is formed by an operational amplifier.

10. The transient response enhancement circuit of claim 8 wherein said resistor is a polycrystalline resistor.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a transient response enhancement circuit of a capacitor-free LDO (low dropout regulator).

Background

LDO (low dropout regulator) is widely used in power management circuits due to its outstanding advantages such as simple structure, low cost, and small size, and is an indispensable part of electronic devices. The biggest challenge of LDO design is the problem of transient response, which is especially prominent under the requirement of low quiescent current. Because the state of the system load changes frequently and the load current changes rapidly, the LDO is required to meet the requirement of sudden change of the load current in a very short time and achieve the purposes of small voltage overshoot and rapid voltage stabilization.

In the prior art, the LDO relies on an external capacitor at the output end and an equivalent series resistor thereof to generate a left half plane zero point to ensure the stability of the system, and the external capacitor is a tantalum capacitor of several microfarads, so that the LDO has good stability and transient response. However, the external capacitor is usually large in size and requires a specific range of resistance values, and at the same time, requires a large area of the printed circuit board, thereby limiting its application. Therefore, the problems in the prior art described above become a problem to be solved by those skilled in the art.

Disclosure of Invention

In view of the above problems in the prior art, a transient response enhancement circuit of a capacitor-less LDO is provided.

The specific technical scheme is as follows:

the invention provides a transient response enhancement circuit of a capacitor-free LDO (low dropout regulator), which comprises:

the output control branch circuit is connected between a voltage input end and a voltage output end and is used for controlling the voltage of the voltage input end to be input to the voltage output end;

the bleeder branch is connected between the voltage output end and the ground;

the detection branch is connected between the voltage output end and the discharge branch so as to detect the output voltage of the voltage output end;

when the detection branch circuit detects transient overshoot voltage in the output voltage, the effect of restraining the overshoot of the output voltage is achieved through the discharge branch circuit.

Preferably, the detection branch comprises:

and the source electrode of the first PMOS tube is connected to the voltage output end and forms the input end of the detection branch, the drain electrode of the first PMOS tube is connected to the input end of the discharge branch and forms the output end of the detection branch, and the control end of the first PMOS tube is connected with a feedback signal so as to detect the output voltage of the voltage output end.

Preferably, the bleed branch comprises:

the first PMOS tube;

and the control end of the NMOS tube is connected to the drain electrode of the first PMOS tube, the drain electrode of the NMOS tube is connected to the voltage output end, and the source electrode of the NMOS tube is grounded and forms the output end of the bleeder branch.

Preferably, the output control branch comprises:

the input end of the amplifier is connected to the drain electrode of the first PMOS tube;

and the control end of the second PMOS tube is connected with the output end of the amplifier, the source electrode of the second PMOS tube is connected to the voltage input end, and the drain electrode of the second PMOS tube is connected to the voltage output end and forms the output end of the output control branch.

Preferably, the output control branch further includes a feedback unit, an input end of the feedback unit is connected to the voltage output end, and an output end of the feedback unit is connected to the detection branch for outputting the feedback signal.

Preferably, the feedback unit includes a comparator, a first input terminal of the comparator is connected to a reference voltage, a second input terminal of the comparator is connected to a feedback voltage provided by the voltage output terminal, and an output terminal of the comparator is connected to the control terminal of the first PMOS transistor.

Preferably, the output control branch further includes a current sink, the input terminal of the current sink is connected to the drain of the first PMOS transistor, and the output terminal of the current sink is grounded, so as to provide a bias current to the amplifier CG.

Preferably, the detection branch further includes a resistor connected in parallel to the current sink and connected between the drain of the first PMOS transistor and ground.

Preferably, the comparator is formed by an operational amplifier.

Preferably, the resistor is a polycrystalline resistor.

The technical scheme has the following advantages or beneficial effects: the detection branch circuit detects transient spike voltage of the voltage output end, a low-resistance path from the output end to the ground is provided by opening the discharge branch circuit, so that voltage jump of the voltage output end is suppressed, the purpose of enhancing transient response of the LDO is achieved, the output pole is moved to a high-frequency position by arranging the output control branch circuit, the frequency stability of the LDO is improved, the structure is simple, the response speed is high, external specific capacitors and additional external capacitor pins are not needed, and the chip area can be reduced.

Drawings

Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.

Fig. 1 is a circuit schematic of an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.

The invention provides a transient response enhancement circuit of a capacitor-free LDO (low dropout regulator), as shown in figure 1, wherein the transient response enhancement circuit comprises:

the output control branch circuit 1 is connected between a voltage input end VIN and a voltage output end VOUT and is used for controlling the voltage of the voltage input end VIN to be input to the voltage output end VOUT;

the bleeder branch 2 is connected between the voltage output end VOUT and the ground GND;

the detection branch circuit 3 is connected between the voltage output end VOUT and the bleeder branch circuit 2 to detect the output voltage of the voltage output end VOUT;

when the detection branch circuit 3 detects transient spike voltage in the output voltage, the effect of suppressing the overshoot of the output voltage is achieved through the discharge branch circuit.

Specifically, in this embodiment, when the detection branch circuit 3 detects a transient spike voltage in the output voltage of the voltage output terminal VOUT, the transient spike current in the output current can be discharged to the ground through the discharging branch circuit 2, so as to suppress the voltage jump of the LDO voltage output terminal VOUT, thereby achieving the purpose of enhancing the transient response of the LDO.

In addition, in this embodiment, an output control branch 1 is further provided, when the LDO operates in a steady state, an output pole is moved to a high frequency, so that the frequency stability of the LDO can be improved, the circuit structure is simple, the response speed is high, and the chip area is reduced.

In a preferred embodiment, the detection branch 3 comprises:

a first PMOS transistor Q1, the source is connected to the voltage output terminal VOUT and forms the input terminal of the detection branch 3, the drain is connected to the input terminal of the bleeding branch 2 and forms the output terminal of the detection branch 3, and the control terminal is connected to a feedback signal to detect the output voltage of the voltage output terminal VOUT.

Specifically, the detection branch 3 in the above-mentioned technical solution includes a first PMOS transistor Q1, and the first PMOS transistor Q1 is used for detecting the magnitude of the output voltage of the voltage output terminal VOUT. In this embodiment, the control end of the first PMOS transistor Q1 is connected to a feedback signal, and when the LDO operates normally, the first PMOS transistor Q1 receives the feedback signal to regulate the output.

In a preferred embodiment, the bleed branch 2 comprises:

a first PMOS transistor Q1;

an NMOS transistor Q2, having a control terminal connected to the drain of the first PMOS transistor Q1, a drain connected to the voltage output terminal VOUT, and a source grounded and forming the output terminal of the bleeding branch 2.

Specifically, in this embodiment, since the LDO itself has a bandwidth limitation, the voltage at the control terminal of the first PMOS transistor Q1 increases with a certain delay time, so that an excessive output current flows to the voltage output terminal VOUT, and thus a transient spike voltage appears at the voltage output terminal VOUT. Further, when the first PMOS transistor Q1 detects that the voltage output terminal VOUT has a transient spike voltage, and the source voltage of the first PMOS transistor Q1 is increased, a large transient current is formed, and the excess current flows to the first resistor R, so that the voltage of the control terminal of the NMOS transistor Q2 is increased, and the NMOS transistor Q2 is turned on, so that the NMOS transistor Q2 discharges the transient spike current to the ground GND.

In addition, it should be noted that the bleeding branch 2 only functions in large signal response, and does not work in steady-state operation of the LDO.

In a preferred embodiment, the output control branch 1 comprises:

the input end of the amplifier CG is connected to the drain electrode of the first PMOS tube Q1;

and a second PMOS transistor Q3, having a control terminal connected to the output terminal of the first amplifier CG, a source connected to the voltage input terminal VIN, and a drain connected to the voltage output terminal VOUT and forming the output terminal of the output control branch 1.

Specifically, in the present embodiment, the voltage output by the first PMOS transistor Q1 is amplified by the first amplifier CG and transmitted to the control terminal of the second PMOS transistor Q3 to turn on the second PMOS transistor Q3, so that the voltage input from the voltage input terminal VIN is transmitted to the voltage output terminal VOUT through the second PMOS transistor Q3.

In a preferred embodiment, the output control branch 1 further includes a feedback unit 10, an input terminal of which is connected to the voltage output terminal VOUT, and an output terminal of which is connected to the detection branch 3 for amplifying the output feedback signal.

Specifically, in this embodiment, the detection branch 3 is connected to the feedback unit 10, and the output pole of the voltage output terminal VOUT is moved to a high frequency place through a negative feedback manner, so that under the condition of no capacitance, the output pole of the voltage output terminal VOUT is at the high frequency place under different loads, and the problem of frequency stability of the LDO output loop is solved.

In a preferred embodiment, the feedback unit 10 includes a comparator EA, a first input terminal of the comparator EA is connected to a reference voltage VREF, a second input terminal of the comparator EA is connected to a feedback voltage VFB provided by the voltage output terminal VOUT, and the output terminal of the comparator EA is connected to the control terminal of the first PMOS transistor Q1.

Specifically, the feedback unit 10 in the above-mentioned technical solution is a comparator EA, and compares the reference voltage VREF with the feedback voltage VFB provided by the voltage output terminal VOUT, so as to regulate and output a corresponding voltage.

In a preferred embodiment, the output control branch 1 further includes a current sink IB having an input terminal connected to the drain of the first PMOS transistor Q1 and an output terminal connected to GND for providing a bias current to the amplifier CG.

Specifically, the output control branch 1 further includes a current sink IB, which provides a bias current to the amplifier CG, that is, the current sink IB is used to provide a low potential to the amplifier CG, so that the amplifier CG amplifies the low potential.

In a preferred embodiment, the sensing branch 3 further includes a resistor R connected in parallel to the current sink IB and connected between the drain of the first PMOS transistor Q1 and the ground GND.

Specifically, the detection branch circuit 3 in the above technical solution further includes a resistor R, and when the first MOS transistor Q1 detects that the voltage output terminal VOUT has a transient spike voltage, the resistor R detects the potential of the second MOS transistor Q2 in a process of discharging the transient spike current in the output current to the ground GND through the second MOS transistor Q2.

In a preferred embodiment, the comparator EA is formed by an operational amplifier.

In a preferred embodiment, the resistor R is a polycrystalline resistor.

While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.