阅读说明：本技术 Cache RAM与Retention RAM数据交换控制器及实现方法 (Data exchange controller of Cache RAM and Retention RAM and implementation method ) 是由 卢鼎 于 2020-11-13 设计创作，主要内容包括：本发明公开了一种Cache RAM与Retention RAM数据交换控制器及实现方法,该数据交换控制器设于Cache RAM与Retention RAM之间,包括主控制状态机、数据搬运过滤判断模块、缓存模块、存储访问端口控制模块、寄存器文件、RAM端口以及接口模块。该数据交换控制器通过数据搬运过滤判断模块对预搬运的数据进行过滤,只搬运有效数据,减少了搬运次数,加速了数据交换过程,节约了系统带宽和功耗,通过RAM端口的设置,可以直接将数据从一个RAM搬运到另一个RAM中,无需特别复杂的数据包转换,高效简洁,该数据交换控制器结构简单,占用资源少,应用于系统睡眠唤醒场景时,节省传输带宽,加速上下电过程,提升了用户体验。(The invention discloses a data exchange controller of a Cache RAM and a Retention RAM and an implementation method thereof. This data exchange controller filters the data of judging module to carrying in advance through the data transport, only carry effective data, the number of times of carrying has been reduced, data exchange process has been accelerated, system bandwidth and consumption have been practiced thrift, setting through the RAM port, can directly carry data from a RAM to another RAM in, need not the data packet conversion of special complicacy, it is high-efficient succinct, this data exchange controller simple structure, it is few to occupy the resource, when being applied to system sleep and awakening up the scene, save transmission bandwidth, the power-on and power-off process accelerates, user experience has been promoted.)

1. A data exchange controller of a Cache RAM and a Retention RAM is arranged between the Cache RAM and the Retention RAM, and is characterized by comprising:

a master control state machine for controlling a data handling process;

the data handling filtering judgment module is connected with the main control state machine and is used for judging whether data need to be handled or not;

the cache module is connected with the data carrying filtering judgment module and is used for caching the TAG content and the carried cache line data;

the storage access port control module is respectively connected with the cache module and the main control state machine and is used for performing read-write control on each port;

the register file is respectively connected with the main control state machine and the data handling filtering judgment module and is used for storing a register configuration command;

one end of the RAM port is connected with the storage access port control module, and the other end of the RAM port is connected with an external Cache RAM or a Retention RAM; and

and one end of the interface module is connected with the register file and the main control state machine, and an AHB Slave interface at the other end of the interface module is connected with the system CPU through an external AHB bus and is used for receiving a system data swap-in/swap-out command.

2. The data exchange controller for the Cache RAM and the Retention RAM according to claim 1, wherein the Cache module comprises a TAG Cache unit and a Cache line Cache unit, and both the TAG Cache unit and the Cache line Cache unit are connected to the data handling filtering judgment module;

the TAG cache unit is used for caching partial TAG contents, and the cache line cache unit is used for caching the carried cache line data.

3. The controller of claim 1, wherein the interface module comprises an AHB slave interface unit and an interrupt interface unit;

one end of the AHB slave interface unit is connected with the register file, and the other end of the AHB slave interface unit is connected with a CPU on an AHB bus and used for receiving a data swap-in/swap-out operation command initiated by a system CPU;

one end of the interrupt interface unit is connected with the main control state machine, and the other end of the interrupt interface unit is connected with the system CPU and used for informing the CPU that the data transportation is finished.

4. The controller of claim 1, wherein the RAM ports comprise a first RAM port and a second RAM port, the first RAM port is connected to an external Cache RAM, and the second RAM port is connected to an external Retention RAM.

5. The controller according to claim 1, wherein the data handling filtering and determining module comprises:

a TAG item INDEX unit for acquiring a TAG item using an INDEX domain INDEX in the logical address;

a flag determination unit for determining whether the valid flag bit V of the current TAG entry is valid: if the effective marker bit V of the current TAG item is invalid, the TAG item is invalid, and the next item is judged by entering a TAG item skipping unit; if the effective flag bit V of the current TAG item is effective, continuing to enter a hit judgment unit to continuously judge whether hit occurs;

a hit judgment unit, configured to further compare the current TAG entry with a TAG field of a logical address TAG in the logical address when the current TAG entry is valid as the valid flag V, and hit if the current TAG entry is consistent with the TAG field of the logical address TAG, otherwise miss; if the effective marker bit V of the current TAG item is invalid, the current TAG item is invalid;

the carrying starting unit is used for carrying cache line data corresponding to the DAT identification when the hit judging unit judges that the cache line data is hit; and

and the TAG item skipping unit is used for skipping the current TAG item and judging the next TAG item when the hit judgment unit judges that the current TAG item is not hit.

6. A Cache RAM data swap-in implementation method is characterized by comprising the following steps:

reading a TAG item from a Retention RAM, and caching the read TAG item;

judging whether data need to be carried according to the current TAG item;

if the transportation is needed, reading cache line data corresponding to the DAT identification from the Retention RAM, and caching the read cache line data;

writing effective data in the cached Cache line data into a corresponding Cache RAM;

after current transport, according to the setting of scope offset, decide whether to end: if not, continuing to read the TAG item in the next Retention RAM and continuing to carry data; when the data is finished, the system returns to the IDLE state and informs the system of the completion of data transportation through the interrupt interface.

7. The method for realizing data swap-in of the Cache RAM according to claim 6, wherein the step of judging whether to start a data handling process according to the current TAG item specifically comprises the steps of:

using an INDEX domain INDEX in the logic address to obtain a TAG item, if the effective marker bit V of the current TAG item is effective, further comparing the current TAG item with the logic address TAG domain in the logic address, if the effective marker bit V is consistent, hitting, otherwise, not hitting; if the effective marker bit V of the current TAG item is invalid, the TAG item enters a TAG item skipping unit, and the judging process is continuously executed;

if the TAG is judged to be hit, carrying cache line data corresponding to the DAT identification;

if the TAG is judged to be not hit, skipping the current TAG item and judging the next TAG item;

and if the TAG is judged to be invalid, skipping the current TAG item and judging the next TAG item.

8. A Cache RAM data swap-out implementation method is characterized by comprising the following steps:

reading a TAG item from the TAG RAM, and caching the read TAG item;

judging whether data need to be carried according to the current TAG item;

if the data needs to be carried, reading Cache line data corresponding to the DAT identification from the Cache RAM, and caching the read Cache line data;

writing effective data in the cached cache line data into a corresponding Retention RAM;

after current transport, according to the setting of scope offset, decide whether to end: if not, continuing to read the TAG item in the next TAG RAM and continuing to carry data; when the data is finished, the system returns to the IDLE state and informs the system of the completion of data transportation through the interrupt interface.

9. The method for realizing data swapping out of the Cache RAM according to claim 8, wherein judging whether to start a data handling process according to the current TAG item specifically comprises:

using an INDEX domain INDEX in the logic address to obtain a TAG item, if the effective marker bit V of the current TAG item is effective, further comparing the current TAG item with the logic address TAG domain in the logic address, if the current TAG item is consistent, hitting, otherwise, not hitting; if the effective marker bit V of the current TAG item is invalid, judging that the current TAG item is invalid;

if the TAG is judged to be hit, carrying cache line data corresponding to the DAT identification;

if the TAG is judged to be not hit, skipping the current TAG item, and judging the next TAG item,

and if the TAG is judged to be invalid, skipping the current TAG item and judging the next TAG item.

Technical Field

The invention relates to the technical field of SOC chip design and data exchange, in particular to a data exchange controller of a Cache RAM and a Retention RAM and a data exchange implementation method.

The invention has requested the priority of patent application with application date 2020.05.11, application number 202010393144.3, name Cache RAM and Retention RAM data exchange controller and implementation method.

Background

At present, with the expansion of the demand of the internet of things and embedded systems for low cost and high capacity external storage, caching low-speed external storage data by adding a special cache controller gradually becomes a mainstream technical scheme. According to the spatial locality and temporal locality principles of data/instruction calling, frequent calling in and calling out of data/instructions can be reduced through the Cache controller, and the access speed is increased. However, in practical applications, when the system is in a sleep state, data in the Cache RAM is directly lost. The existing solution is to swap in and swap out the data in the Cache RAM through the AHB bus and the Retention RAM when the system is sleeping.

However, in the conventional method, when data is transferred, a secondary conversion process from the RAM interface to the AHB interface and then from the AHB interface to the RAM interface needs to be performed. Meanwhile, in the conventional scheme, the whole data is required to be carried item by item when the Cache RAM data is exchanged, and in practical application, a large number of invalid data items exist in the Cache RAM, for example, valid data is not filled in corresponding entries or corresponding data items are invalid. In this case, the data is swapped in and out, which wastes a large amount of bandwidth and power consumption of the system, and the user experience effect is poor.

Therefore, the technical problem to be solved by the present invention is how to provide a solution that can simplify the data exchange process between the Cache RAM and the latency RAM, improve the data transfer efficiency of the CPU and the bus, and shorten the power-on/power-off time.

Disclosure of Invention

In view of this, the present invention provides a data exchange controller for a Cache RAM and a coverage RAM, which has a simple structure and occupies a small amount of resources, and can shorten the power-on and power-off time of a system, thereby solving the problems of complex process, low data transfer efficiency of a CPU and a bus, and poor user experience effect of the existing data exchange scheme for the Cache RAM and the coverage RAM.

In order to achieve the purpose, the invention adopts the following technical scheme:

in a first aspect, the present invention discloses a data exchange controller for a Cache RAM and a Retention RAM, the data exchange controller being disposed between the Cache RAM and the Retention RAM, comprising:

a master control state machine for controlling a data handling process;

the data handling filtering judgment module is connected with the main control state machine and is used for judging whether data need to be handled or not;

the cache module is connected with the data carrying filtering judgment module and is used for caching the TAG content and the carried cache line data;

the storage access port control module is respectively connected with the cache module and the main control state machine and is used for performing read-write control on each port;

the register file is respectively connected with the main control state machine and the data handling filtering judgment module and is used for storing a register configuration command;

one end of the RAM port is connected with the storage access port control module, and the other end of the RAM port is connected with an external Cache RAM or a Retention RAM; and

and one end of the interface module is connected with the register file and the main control state machine, and an AHB Slave interface at the other end of the interface module is connected with the system CPU through an external AHB bus and is used for receiving a system data swap-in/swap-out command.

The invention has the beneficial effects that: the data exchange controller filters the data to be carried in advance through the data carrying and filtering judging module, only carries effective data, reduces the total carrying data amount, avoids unnecessary data carrying, accelerates the data exchange process, saves the system bandwidth and power consumption, can directly carry the data from one RAM to another RAM through the setting of the RAM port, does not need particularly complex data packet conversion, and is efficient and simple. The data exchange controller is simple in structure, small in occupied resource, and capable of saving transmission bandwidth, accelerating the power-on and power-off processes and improving user experience when being applied to a system sleep awakening scene.

On the basis of the above scheme, the scheme provided by the invention is further explained.

Furthermore, the cache module comprises a TAG cache unit and a cache line cache unit, and both the TAG cache unit and the cache line cache unit are connected with the data carrying, filtering and judging module;

the TAG cache unit is used for caching partial TAG contents, and the cache line cache unit is used for caching the carried cache line data.

Further, the interface module includes an AHB slave interface unit and an interrupt interface unit;

one end of the AHB slave interface unit is connected with the register file, and the other end of the AHB slave interface unit is connected with an AHB bus and used for receiving a system data swap-in/swap-out command;

one end of the interrupt interface unit is connected with the main control state machine, and the other end of the interrupt interface unit is connected with the system CPU and used for informing the CPU that the data transportation is finished.

Furthermore, the RAM ports comprise a first RAM port and a second RAM port, the first RAM port is connected with an external Cache RAM, and the second RAM port is connected with an external Retention RAM.

Further, the data handling filtering and judging module comprises:

a TAG item INDEX unit for acquiring a TAG item using an INDEX domain INDEX in the logical address;

a flag determination unit for determining whether the valid flag bit V of the current TAG entry is valid: if the effective marker bit V of the current TAG item is invalid, the TAG item is invalid, and the next item is judged by entering a TAG item skipping unit; if the effective flag bit V of the current TAG item is effective, continuing to enter a hit judgment unit to continuously judge whether hit occurs;

a hit judgment unit, configured to further compare the current TAG entry with a TAG field of a logical address TAG in the logical address when the current TAG entry is valid as the valid flag V, and hit if the current TAG entry is consistent with the TAG field of the logical address TAG, otherwise miss; if the current TAG item is not invalid for the valid marker bit V, the current TAG item is invalid;

the carrying starting unit is used for carrying cache line data corresponding to the DAT identification when the hit judging unit judges that the cache line data is hit; and

and the TAG item skipping unit is used for skipping the current TAG item and judging the next TAG item when the hit judgment unit judges that the current TAG item is not hit.

In a second aspect, the present invention provides a method for implementing data swap-in of a Cache RAM, including:

reading a TAG item from a Retention RAM, and caching the read TAG item;

judging whether data need to be carried according to the current TAG item;

if the transportation is needed, reading cache line data corresponding to the DAT identification from the Retention RAM, and caching the read cache line data;

writing effective data in the cached Cache line data into a corresponding Cache RAM;

after current transport, according to the setting of scope offset, decide whether to end: if not, continuing to read the TAG item in the next Retention RAM and continuing to carry data; when the data is finished, the system returns to the IDLE state and informs the system of the completion of data transportation through the interrupt interface.

Further, the process of judging whether to start to carry data according to the current TAG item specifically includes:

using INDEX of INDEX domain in the logic address to obtain TAG item, if the effective flag bit V of the current TAG item is effective, further comparing the current TAG item with the logic address TAG domain in the logic address, if the effective flag bit V is effective, hitting (hit) if the effective flag bit V is consistent, otherwise not hitting (miss); if the effective marker bit V of the current TAG item is invalid, the TAG item is invalid (invalid), and the TAG item enters a TAG item skipping unit to continue to execute the judgment process;

if the TAG is judged to be hit (hit), carrying cache line data corresponding to the DAT identification;

if the TAG is judged as not hit (miss), skipping the current TAG item and judging the next TAG item;

and if the TAG is judged to be invalid (invalid), skipping the current TAG item and judging the next TAG item.

In a third aspect, the present invention further provides a method for implementing data swap-out of a Cache RAM, where the method includes:

reading a TAG item from the TAG RAM, and caching the read TAG item;

judging whether data need to be carried according to the current TAG item;

if the data needs to be carried, reading Cache line data corresponding to the DAT identification from the Cache RAM, and caching the read Cache line data;

writing effective data in the cached cache line data into a corresponding Retention RAM;

after current transport, according to the setting of scope offset, decide whether to end: if not, continuing to read the TAG item in the next TAG RAM and continuing to carry data; when the data is finished, the system returns to the IDLE state and informs the system of the completion of data transportation through the interrupt interface.

Further, the process of judging whether to start to carry data according to the current TAG item specifically includes:

using an INDEX domain INDEX in the logic address to obtain a TAG item, if the effective marker bit V of the current TAG item is effective, further comparing the current TAG item with the logic address TAG domain in the logic address, if the current TAG item is consistent, hitting, otherwise, not hitting; if the effective marker bit V of the current TAG item is invalid, judging that the current TAG item is invalid;

if the TAG is judged to be hit, carrying cache line data corresponding to the DAT identification;

if the TAG is judged to be not hit, skipping the current TAG item and judging the next TAG item;

and if the TAG is judged to be invalid, skipping the current TAG item and judging the next TAG item.

According to the technical scheme, compared with the prior art, the Cache RAM data swap-in and swap-out implementation method needs to judge whether data transportation needs to be started or not before data transportation, the current data are transported only after the transportation starting condition is met, and swap-in and swap-out during data transportation are only effective data, so that the problem of system bandwidth waste and power consumption caused by transportation of a large number of invalid data items is solved, the data transportation process can be directly transported from one RAM to another RAM, a complex data packet conversion process is not needed, and the method is simple and efficient.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram illustrating a structure of a data exchange controller for a Cache RAM and a Retention RAM according to the present invention;

FIG. 2 is a block diagram of a data handling filter determination module according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating a position relationship of a data exchange controller in a Cache RAM and a Retention RAM data high-speed exchange device according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating a working principle of a Cache controller according to an embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating a TAG RAM instructing a Cache RAM to transport data through a data exchange controller according to an embodiment of the present invention;

FIG. 6 is a schematic flow chart of a Cache RAM data swap-in implementation method according to the present invention;

FIG. 7 is a schematic flow chart of a Cache RAM data swap-out implementation method according to the present invention;

FIG. 8 is a schematic diagram illustrating a principle of data swap-in and swap-out of a Cache RAM according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, an embodiment of the present invention discloses a data exchange controller for a Cache RAM and a latency RAM, where the data exchange controller is disposed between the Cache RAM and the latency RAM, and includes:

the main control state machine 1, the main control state machine 1 is used for controlling data handling;

the data handling filtering judgment module 2 is connected with the main control state machine 1 and is used for judging whether data needs to be handled or not;

the cache module 3 is connected with the data carrying filtering judgment module 2 and is used for caching the TAG content and the carried cache line data;

the storage access port control module 4 is connected with the cache module 3 and the main control state machine 1 respectively, and is used for performing read-write control on each port;

the register file 5, the register file 5 is connected with main control state machine 1 and data handling filter judging module 2 separately, is used for storing the register and disposing the order;

one end of the RAM port is connected with the storage access port control module 4, and the other end of the RAM port is connected with an external Cache RAM or a Retention RAM; and

and one end of the interface module is connected with the register file 5 and the main control state machine 1, and an AHB Slave interface at the other end of the interface module is connected with the system CPU through an external AHB bus and is used for receiving a system data swap-in/swap-out command.

In a specific embodiment, the cache module 3 includes a TAG cache unit 31 and a cache line cache unit 32, and both the TAG cache unit 31 and the cache line cache unit 32 are connected to the data handling filtering judgment module 2;

the TAG cache unit 31 is configured to cache TAG content, and the cache line cache unit 32 is configured to cache the carried cache line data.

In a specific embodiment, the interface module includes an AHB slave interface unit 8 and an interrupt interface unit 9;

one end of an AHB slave interface unit 8 is connected with the register file 5, and the other end of the AHB slave interface unit is connected with an AHB port on an AHB bus and used for receiving a system data exchange in/out command;

one end of the interrupt interface unit 9 is connected to the main control state machine 1, and the other end thereof is connected to the system CPU for notifying the CPU that the data transfer is completed.

In the present embodiment, the register file 5 includes a command register, an address register, a status register, a mode register, and the like.

In a specific embodiment, the RAM ports include a first RAM port 6 and a second RAM port 7, the first RAM port 6 is connected with an external Cache RAM, and the second RAM port 7 is connected with an external latency RAM.

In one specific embodiment, referring to fig. 2, the data handling filter determination module 2 includes:

a TAG entry indexing unit 21 for acquiring a TAG entry using an INDEX of an INDEX field in the logical address;

a flag determination unit 22 for determining whether the valid flag bit V of the current TAG entry is valid;

a hit determining unit 23, configured to further compare the current TAG entry with a TAG field of a logical address TAG in the logical address when the valid flag V of the current TAG entry is valid, and hit if the current TAG entry is consistent with the TAG field of the logical address TAG, otherwise miss; if the effective marker bit V of the current TAG item is invalid, the current TAG item is invalid;

a carrying starting unit 24, configured to carry cache line data corresponding to the DAT identifier when the hit determination unit determines that the cache line data is hit; and

and a TAG item skipping unit 25, configured to skip the current TAG item and perform the next TAG item determination when the hit determination unit determines that the TAG item is not hit.

The position of the data exchange controller in the Cache RAM and the Retention RAM data high-speed exchange device provided in this embodiment is as shown in fig. 3, one end of the data exchange controller is connected to the AHB bus module, and the other end of the data exchange controller is connected to the Cache RAM and the Retention RAM, respectively.

In the Cache RAM and Retention RAM data high-speed exchange device provided in this embodiment, the AHB bus module: the data exchange controller is responsible for the interconnection of each AHB interface peripheral and the CPU/DMA data exchange controller;

cache AHB bus interface module: the access from the AHB bus to the register and the RAM of the Cache is responsible;

retention RAM AHB bus interface module: the access from AHB bus to the Retention RAM is responsible;

register file: defining a programming interface of the controller, and defining a plurality of registers including a command register, a state register, an address register, a mode register and the like;

a Cache controller: the Cache management module is responsible for access control of the Cache RAM and data Cache management of external storage;

a storage controller: the data exchange between the external storage and the RAM is carried out;

cache RAM: the Cache is used as a Cache for reading and writing data by the Cache and the storage controller and is connected with a first port of the data controller;

TAG RAM: the storage unit used as the address remapping of the Cache has small capacity (usually within the range of 256-512 bytes);

and the Retention RAM is used as a storage cache of data during sleep and is connected with the second port of the data exchange controller, so that the data can be maintained without loss under the condition of system power failure.

In this embodiment, the working principle of the Cache controller is as shown in fig. 4, and the logical address of the system access storage is divided into three parts: the logical address TAG field, INDEX field and OFFSET field are respectively introduced as follows:

logical address TAG field: storing high-order address information of the system, and comparing the high-order address information with the Cache remapping identifier;

INDEX domain: storing TAG index information of the TAG RAM for searching a corresponding TAG data item;

OFFSET domain: and storing the offset of the Cache line internal data offset of the Cache RAM, and acquiring the final data.

Storing an effective mark bit V, a comparison mark TAG and physical address DATA DATA in a TAG RAM of a Cache module, wherein:

the valid flag bit V is used for marking whether the current entry is valid;

the comparison TAG is used for comparing with the TAG of the logic address;

the physical address DATA is used to store a physical base address where cache line DATA is actually stored.

Wherein the mapping of addresses from logical addresses to physical addresses comprises the following steps:

1. indexing each TAG entry of the TAG RAM using an INDEX field;

2. if the entry is V, then compare with logical address TAG field, hit if consistent, otherwise miss;

3. if the entry is not V, the entry is invalid (invalid);

4. if the plurality of TAG items indexed by the INDEX are miss or invalid, the logical address access miss (miss) needs to call in data from the outside and supplement the corresponding TAG item;

5. if some item is hit (there is only one item, otherwise, it is wrong), then the INDEX where the reorganization is located, the physical address DATA of the hit item and the OFFSET domain are combined into the remapped address, and the cache RAM is accessed to obtain the access DATA.

Due to the data calling of the Cache RAM and the initialization and updating of the TAG RAM, a large amount of time is occupied. Especially, when the system is in sleep, the data of the Cache RAM and the data of the TAG RAM are lost, so that the performance of the system is lost. Therefore, when designing the data exchange controller, the embodiment of the invention ensures that the data exchange controller can meet the following conditions:

when the system is sleeping, the data of the Cache RAM and the TAG RAM are quickly swapped out to the Retention RAM;

and after the system is awakened, quickly replacing the data in the Retention RAM into the Cache RAM and the TAG RAM.

Referring to fig. 5, the data interchange controller provided in this embodiment determines whether to transport the corresponding Cache RAM content by pre-reading each flag bit of the TAG RAM. If the item is valid (V), carrying the cache line DATA corresponding to the DATA item; if the item is invalid, the corresponding item is skipped over, and the next item is directly judged. The design reduces the carrying times, accelerates the data exchange process and saves the bandwidth and the power consumption.

In this embodiment, before data swap-in and swap-out, the register file 5 is first subjected to operations such as configuration command, setting mode, etc., and the configuration contents include:

a) the direction of the data being transported;

b) a source start address of the transport data;

c) a target start address of the transport data;

d) the range offset of the transport data (the source last address of the transport data — the start address of the transport data, in bytes).

In this embodiment, since the data exchange controller is designed to have a transport filtering function, the amount of data actually transported is equal to or less than the offset.

In a second aspect, an embodiment of the present invention further provides reference to fig. 6, where the embodiment of the present invention discloses a method for implementing data swap-in of a Cache RAM, where the method includes:

s1: reading a TAG item from a Retention RAM, and caching the read TAG item;

s2: judging whether data need to be carried according to the current TAG item;

s3: if the transportation is needed, reading cache line data corresponding to the DAT identification from the Retention RAM, and caching the read cache line data;

s4: writing effective data in the cached Cache line data into a corresponding Cache RAM;

s5: after current transport, according to the setting of scope offset, decide whether to end: if not, continuing to read the TAG item in the next Retention RAM and continuing to carry data; when the data is finished, the system returns to the IDLE state and informs the system of the completion of data transportation through the interrupt interface.

In a specific embodiment, the determining whether to start the process of carrying data according to the current TAG item specifically includes:

using an INDEX domain INDEX in the logic address to obtain a TAG item, if the effective marker bit V of the current TAG item is effective, further comparing the current TAG item with the logic address TAG domain in the logic address, if the effective marker bit V is consistent, hitting, otherwise, not hitting; if the effective marker bit V of the current TAG item is invalid, the current TAG item is invalid;

if the TAG is judged to be hit, carrying cache line data corresponding to the DAT identification;

if the TAG is judged to be not hit, skipping the current TAG item and judging the next TAG item;

and if the TAG is judged to be invalid, skipping the current TAG item and judging the next TAG item.

In a third aspect, referring to fig. 7, the present invention further provides a method for implementing data swap-out of a Cache RAM, where the method includes:

a1: reading a TAG item from the TAG RAM, and caching the read TAG item;

a2: judging whether data need to be carried according to the current TAG item;

a3: if the data needs to be carried, reading Cache line data corresponding to the DAT identification from the Cache RAM, and caching the read Cache line data;

a4: writing effective data in the cached cache line data into a corresponding Retention RAM;

a5: after current transport, according to the setting of scope offset, decide whether to end: if not, continuing to read the TAG item in the next TAG RAM and continuing to carry data; when the data is finished, the system returns to the IDLE state and informs the system of the completion of data transportation through the interrupt interface.

In a specific embodiment, the determining whether to start the process of carrying data according to the current TAG item specifically includes:

using INDEX of INDEX domain in the logic address to obtain TAG item, if the effective flag bit V of the current TAG item is effective, further comparing the current TAG item with the logic address TAG domain in the logic address, if the effective flag bit V is consistent, hitting (hit), otherwise not hitting (miss); if the effective marker bit V of the current TAG item is invalid, the current TAG item is invalid (invalid);

if the TAG is judged to be hit (hit), carrying cache line data corresponding to the DAT identification;

if the TAG is judged as not hit (miss), skipping the current TAG item and judging the next TAG item;

and if the TAG is judged to be invalid (invalid), skipping the current TAG item and judging the next TAG item.

In this embodiment, no matter in the process of swapping in or swapping out the Cache RAM data, the implementation principle of the step of determining whether to start carrying is the same, which can be seen in fig. 8 specifically, it can be seen from fig. 8 that, no matter in the process of swapping in or swapping out the data, the TAG RAM must be swapped in or swapped out first, and then the Cache RAM data is carried under the guidance of the V identifier of the TAG RAM and whether to hit.

In this embodiment, the calling of the Cache RAM data and the initialization and update of the TAG RAM may take a lot of time. Especially when the system is asleep, the loss of Cache RAM data and TAG RAM data can result in a loss of system performance. Therefore, the Cache RAM data swap-in implementation method and the Cache RAM data swap-out implementation method provided by this embodiment can be used in cooperation with the system state in actual application, and are specifically as follows:

when the system is sleeping, the data of the Cache RAM and the TAG RAM are quickly swapped out to the Retention RAM;

and after the system is awakened, quickly exchanging the data in the Retention RAM into the Cache RAM and the Retention RAM.

In summary, the data exchange controller and the data swap-in and swap-out implementation method disclosed in the embodiments of the present invention have the following advantages, compared with the prior art:

cache data handling filtering function:

in a conventional design, the whole data is required to be carried item by item when the Cache RAM data is exchanged in and out. In practical applications, a large number of invalid data items exist in the Cache RAM, for example, valid data is not filled in a corresponding entry or a corresponding data item is invalid. In this case, swapping in and out of these data wastes bandwidth and power consumption.

The scheme provided by this embodiment determines whether to carry the corresponding Cache RAM content by pre-reading each flag bit of the TAG RAM (as shown in fig. 8). If the item is valid (V), carrying the cache line DATA corresponding to the DATA item; if the item is invalid, the corresponding item is skipped over, and the next item is directly judged. The design reduces the carrying times, accelerates the data exchange process and saves the bandwidth and the power consumption.

2. Data handling process direct port access:

in the conventional data transportation, a secondary conversion process from the RAM interface to the AHB interface and then from the AHB interface to the RAM interface is required. Unnecessary packet conversion is performed, resulting in a waste of system bandwidth and time delay.

In the scheme provided by this embodiment, the RAM port is connected to the Cache RAM and the Retention RAM, and only the Cache RAM data packet is converted in the whole data swap-in and swap-out process, and compared with the multiple conversions of the Cache RAM data packet, the Cache RAM data packet is converted for multiple times, so that the efficiency of data swap is significantly improved.

3. The complexity is low: the Cache RAM and the Retention RAM are respectively connected with the first RAM port and the second RAM port of the device, so that the design difficulty of the Cache module is effectively reduced.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art.