阅读说明：本技术 像素电路及其驱动方法、显示装置 (Pixel circuit, driving method thereof and display device ) 是由 胡国锋 谷其兵 林奕呈 时凌云 黄文杰 洪青桦 李秀玲 付宝 于 2021-07-26 设计创作，主要内容包括：本公开实施例提供一种像素电路,包括：电流控制模块,被配置为在第一扫描信号端的控制下,向第一节点提供驱动电信号；依次串联连接的n个待驱动元件,第一个待驱动元件的第一极与第一节点连接,第n个待驱动元件的第二极与第二电源端连接；与n个待驱动元件一一对应且并联连接的n个灰阶控制模块,第i个灰阶控制模块分别与第i子像素数据信号端、第二扫描信号端连接,n个灰阶控制模块被配置为在第二扫描信号端的控制下,基于n个子像素数据信号端,控制各个待驱动元件的导通时间长度；或者,控制流经各个待驱动元件的电流。这样的像素电路,大大降低了一个像素的电流,降低了显示装置的功耗,提升了产品竞争力。(The disclosed embodiment provides a pixel circuit, including: a current control module configured to provide a driving electric signal to the first node under the control of the first scan signal terminal; n to-be-driven elements which are sequentially connected in series, wherein the first pole of the first to-be-driven element is connected with the first node, and the second pole of the nth to-be-driven element is connected with the second power supply end; the n gray scale control modules are in one-to-one correspondence with the n elements to be driven and are connected in parallel, the ith gray scale control module is respectively connected with the ith sub-pixel data signal end and the second scanning signal end, and the n gray scale control modules are configured to control the conduction time length of each element to be driven based on the n sub-pixel data signal ends under the control of the second scanning signal end; alternatively, the current flowing through each element to be driven is controlled. The pixel circuit greatly reduces the current of one pixel, reduces the power consumption of the display device and improves the product competitiveness.)

1. A pixel circuit, comprising:

a current control module, respectively connected to a first power terminal, a first data signal terminal, a first scan signal terminal and a first node, configured to provide a driving electrical signal to the first node based on a signal of the first power terminal and a data signal of the first data signal terminal under the control of the first scan signal terminal;

the driving unit comprises n to-be-driven elements which are sequentially connected in series, a first pole of a first to-be-driven element is connected with a first node, a second pole of an nth to-be-driven element is connected with a second power supply end, and n is a positive integer greater than 1;

the n gray scale control modules are in one-to-one correspondence with the n elements to be driven and are connected in parallel, the ith gray scale control module is respectively connected with the ith sub-pixel data signal end and the second scanning signal end, and the n gray scale control modules are configured to control the conduction time length of each element to be driven in the process that the driving electric signal is transmitted from the first node to the second power supply end based on the n sub-pixel data signal ends under the control of the second scanning signal end; alternatively, the current flowing through each element to be driven is controlled, where i is 1,2, …, n.

2. The pixel circuit according to claim 1, wherein the n gray scale control modules include n time control modules, the n time control modules are in one-to-one correspondence with and connected in parallel with the n to-be-driven elements, the ith time control module is respectively connected with the ith sub-pixel data signal terminal, the second scan signal terminal and the time control signal terminal, and the n time control modules are configured to control the on-time length of each to-be-driven element in the process that the driving electrical signal is transmitted from the first node to the second power terminal based on the data signals of the n sub-pixel data signal terminals and the signals of the time control signal terminal under the control of the second scan signal terminal.

3. The pixel circuit according to claim 2, wherein the time control signal terminal is configured to output a pulse width modulation signal comprising a falling edge with a slope and/or a rising edge with a slope.

4. The pixel circuit of claim 2, wherein the timing control module comprises a first write submodule, a bootstrap submodule, and a switch submodule;

the first write-in submodule is respectively connected with the ith sub-pixel data signal end, the second scanning signal end and the second node and is configured to provide a data signal of the ith sub-pixel data signal end for the second node under the control of the second scanning signal end;

the bootstrap sub-module is respectively connected with the second node and the time control signal end, and the electric potential of the second node is changed based on the signal of the time control signal end under the bootstrap action of the bootstrap sub-module;

the switch submodule is respectively connected with two ends of the ith element to be driven and the second node, and is configured to enable two ends of the corresponding element to be driven to be connected through the switch submodule under the control of the second node.

5. The pixel circuit of claim 4, wherein the time control module comprises at least one of:

the first writing submodule comprises a ninth transistor, the grid electrode of the ninth transistor is connected with the second scanning signal end, the first pole of the ninth transistor is connected with the ith sub-pixel data signal end, and the second pole of the ninth transistor is connected with the second node;

the bootstrap sub-module comprises a bootstrap capacitor, a first pole plate of the bootstrap capacitor is connected with the second node, and a second pole plate of the bootstrap capacitor is connected with the time control signal end;

the switch submodule comprises an eighth transistor, the grid electrode of the eighth transistor is connected with the second node, and the first pole and the second pole of the eighth transistor are respectively connected with the first pole and the second pole of the ith element to be driven.

6. The pixel circuit according to claim 1, wherein the n gray scale control modules comprise n current regulation modules, the n current regulation modules are in one-to-one correspondence with and connected in parallel with the n to-be-driven elements, the ith current regulation module is connected with the ith sub-pixel data signal terminal, and the n current regulation modules are configured to regulate the current flowing through each to-be-driven element during the transmission of the driving electrical signal from the first node to the second power supply terminal based on the data signals of the n sub-pixel data signal terminals.

7. The pixel circuit of claim 6, wherein the current regulation module comprises a third write submodule, a regulation submodule, and a second storage submodule;

the third write-in submodule is respectively connected with the ith sub-pixel data signal end, the second scanning signal end and the sixth node and is configured to provide a data signal of the ith sub-pixel data signal end for the sixth node under the control of the second scanning signal end;

the adjusting submodule is respectively connected with a sixth node and two ends of an ith element to be driven and is configured to adjust the current flowing through the adjusting submodule based on the data signal of the sixth node;

the second storage submodule is respectively connected with a sixth node and the first power supply terminal and is configured to store the data voltage of the sixth node.

8. The pixel circuit of claim 7, wherein the current regulation module comprises at least one of:

the third write-in submodule comprises a tenth transistor, the grid electrode of the tenth transistor is connected with the second scanning signal end, the first pole of the tenth transistor is connected with the ith sub-pixel data signal end, and the second pole of the tenth transistor is connected with a sixth node;

the adjusting submodule comprises an eleventh transistor, the grid electrode of the eleventh transistor is connected with a sixth node, and the first pole and the second pole of the eleventh transistor are respectively connected with two ends of the ith element to be driven;

the second storage submodule comprises a second storage capacitor, a first plate of the second storage capacitor is connected with the sixth node, and a second plate of the second storage capacitor is connected with the first power supply end.

9. The pixel circuit according to claim 1, wherein the pixel comprises m elements to be driven, m is a positive integer greater than 2, and n is less than m.

10. The pixel circuit according to any one of claims 1 to 9, wherein the current control block is further connected to a control signal terminal, a reset signal terminal, and an initial signal terminal, and is configured to provide a driving electrical signal to the first node based on a signal of the first power terminal and a data signal of the first data signal terminal under control of the first scan signal terminal, the control signal terminal, and the reset signal terminal;

the current control module includes:

a reset submodule, connected to the initial signal terminal, the first node, the third node and the reset signal terminal, respectively, and configured to provide an initial signal of the initial signal terminal to the first node and the third node under the control of the reset signal terminal;

a second write submodule, connected to the first data signal terminal, the first scanning signal terminal, the fourth node, the fifth node, and the third node, respectively, and configured to provide the data signal of the first data signal terminal to the third node under the control of the first scanning signal terminal;

a first storage submodule connected to the third node and the first power terminal, respectively, and configured to store a data signal of the third node;

a driving submodule respectively connected to the third node, the fourth node and the fifth node and configured to provide a corresponding electrical signal to the fifth node based on the electrical signal of the fourth node under the control of the third node;

and the switch control submodule is respectively connected with the first power supply end, the fourth node, the fifth node, the first node and the control signal end and is configured to provide a driving electric signal to the first node through the fourth node, the driving submodule and the fifth node based on the voltage of the first power supply end under the control of the control signal end.

11. The pixel circuit of claim 10, wherein the current control module comprises at least one of:

the reset submodule comprises a sixth transistor and a seventh transistor, the grid electrode of the sixth transistor is connected with the reset signal end, the first pole of the sixth transistor is connected with the initial signal end, and the second pole of the sixth transistor is connected with the third node; a gate of the seventh transistor is connected to the reset signal terminal, a first pole of the seventh transistor is connected to the initial signal terminal, and a second pole of the seventh transistor is connected to the first node;

the second write submodule comprises a second transistor and a fourth transistor, the grid electrode of the second transistor is connected with the first scanning signal end, the first pole of the second transistor is connected with the first data signal end, and the second pole of the second transistor is connected with the fourth node; a gate of the fourth transistor is connected to the first scan signal terminal, a first pole of the fourth transistor is connected to the fifth node, and a second pole of the fourth transistor is connected to the third node;

the first storage submodule comprises a first storage capacitor, a first pole plate of the first storage capacitor is connected with the first power supply end, and a second pole plate of the first storage capacitor is connected with the third node;

the driving sub-module comprises a third transistor, wherein the grid electrode of the third transistor is connected with the third node, the first pole of the third transistor is connected with the fourth node, and the second pole of the third transistor is connected with the fifth node;

the switch control submodule comprises a first transistor and a fifth transistor, the grid electrode of the first transistor is connected with the control signal end, the first electrode of the first transistor is connected with the first power supply end, and the second electrode of the first transistor is connected with the fourth node; the gate of the fifth transistor is connected to the control signal terminal, the first pole of the fifth transistor is connected to the fifth node, and the second pole of the fifth transistor is connected to the first node.

12. A method of driving a pixel circuit, which is applied to the pixel circuit according to claim 4 or 5, the method comprising:

in the data writing stage, providing a data signal of an ith sub-pixel data signal end to a second node;

in the light emitting stage, the potential of the second node is changed based on the signal of the time control signal end under the bootstrap action of the bootstrap submodule, and the switch submodule controls the conducting time length of the switch submodule under the control of the potential of the second node.

13. A method of driving a pixel circuit, which is applied to the pixel circuit according to claim 7 or 8, the method comprising:

in the data writing stage, providing a data signal of an ith sub-pixel data signal end to a sixth node;

in the lighting phase, the current flowing through the regulating submodule is regulated based on the data signal of the sixth node.

14. A display device comprising the pixel circuit according to any one of claims 1 to 11.

Technical Field

The present disclosure relates to but not limited to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.

Background

Light Emitting Diodes (LEDs) include Micro LEDs and submillimeter LEDs (Mini LEDs). Among Light Emitting Diode (LED) display products, especially glass-based Mini LED and Micro LED display products, there is a need to solve the problems of low gray color uniformity, low gray flicker, and gray scale level. In the related art, the pixel driving is usually realized by adopting a current + duration control mode, wherein the current control mode is adopted in the high gray scale, and the duration control mode is adopted in the low gray scale. However, in the conventional pixel circuit, the power consumption of the thin film transistor in the back plate is more than 50%, so that the power consumption of the whole module is higher, and the product competitiveness is reduced.

Disclosure of Invention

Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, and a display device to solve or alleviate one or more technical problems in the prior art.

As a first aspect of embodiments of the present disclosure, embodiments of the present disclosure provide a pixel circuit including:

a current control module, respectively connected to the first power terminal, the first data signal terminal, the first scan signal terminal and the first node, configured to provide a driving electrical signal to the first node based on a signal of the first power terminal and a data signal of the first data signal terminal under the control of the first scan signal terminal;

the driving unit comprises n to-be-driven elements which are sequentially connected in series, a first pole of a first to-be-driven element is connected with a first node, a second pole of an nth to-be-driven element is connected with a second power supply end, and n is a positive integer greater than 1;

the n gray scale control modules are in one-to-one correspondence with the n elements to be driven and are connected in parallel, the ith gray scale control module is respectively connected with the ith sub-pixel data signal end and the second scanning signal end, and the n gray scale control modules are configured to control the conduction time length of each element to be driven in the process of transmitting a driving electric signal from the first node to the second power supply end on the basis of the n sub-pixel data signal ends under the control of the second scanning signal end; alternatively, the current flowing through each element to be driven is controlled, where i is 1,2, …, n.

In some possible implementation manners, the n gray scale control modules include n time control modules, the n time control modules correspond to the n to-be-driven elements in a one-to-one manner and are connected in parallel, the ith time control module is respectively connected with the ith sub-pixel data signal terminal, the second scanning signal terminal and the time control signal terminal, and the n time control modules are configured to control the conduction time length of each to-be-driven element in the process of transmitting the driving electric signal from the first node to the second power supply terminal based on the data signals of the n sub-pixel data signal terminals and the signals of the time control signal terminal under the control of the second scanning signal terminal.

In some possible implementations, the time control signal terminal is configured to output a pulse width modulation signal including a falling edge in a ramp and/or a rising edge in a ramp.

In some possible implementations, the time control module includes a first write submodule, a bootstrap submodule, and a switch submodule;

the first writing sub-module is respectively connected with the ith sub-pixel data signal end, the second scanning signal end and the second node and is configured to provide a data signal of the ith sub-pixel data signal end for the second node under the control of the second scanning signal end;

the bootstrap module is respectively connected with the second node and the time control signal end, and the potential of the second node is changed based on the signal of the time control signal end under the bootstrap action of the bootstrap module;

and the switch submodule is respectively connected with the two ends of the ith element to be driven and the second node and is configured to enable the two ends of the corresponding element to be driven to be connected through the switch submodule under the control of the second node.

In some possible implementations, the time control module includes at least one of:

the first writing submodule comprises a ninth transistor, the grid electrode of the ninth transistor is connected with the second scanning signal end, the first pole of the ninth transistor is connected with the ith sub-pixel data signal end, and the second pole of the ninth transistor is connected with the second node;

the bootstrap module comprises a bootstrap capacitor, a first pole plate of the bootstrap capacitor is connected with the second node, and a second pole plate of the bootstrap capacitor is connected with the time control signal end;

the switch submodule comprises an eighth transistor, the grid electrode of the eighth transistor is connected with the second node, and the first pole and the second pole of the eighth transistor are respectively connected with the first pole and the second pole of the ith element to be driven.

In some possible implementations, the n gray scale control modules include n current adjustment modules, the n current adjustment modules correspond to the n to-be-driven elements one to one and are connected in parallel, the ith current adjustment module is connected to the ith sub-pixel data signal terminal, and the n current adjustment modules are configured to adjust a current flowing through each to-be-driven element based on data signals of the n sub-pixel data signal terminals in a process that the driving electrical signal is transmitted from the first node to the second power supply terminal.

In some possible implementations, the current regulation module includes a third write submodule, a regulation submodule, and a second storage submodule;

the third writing sub-module is respectively connected with the ith sub-pixel data signal end, the second scanning signal end and the sixth node and is configured to provide the data signal of the ith sub-pixel data signal end to the sixth node under the control of the second scanning signal end;

the adjusting submodule is respectively connected with the sixth node and two ends of the ith element to be driven and is configured to adjust the current flowing through the adjusting submodule based on the data signal of the sixth node;

the second storage submodule is respectively connected with the sixth node and the first power supply terminal and is configured to store the data voltage of the sixth node.

In some possible implementations, the current regulation module includes at least one of:

the third write-in submodule comprises a tenth transistor, the grid electrode of the tenth transistor is connected with the second scanning signal end, the first pole of the tenth transistor is connected with the ith sub-pixel data signal end, and the second pole of the tenth transistor is connected with the sixth node;

the adjusting submodule comprises an eleventh transistor, the grid electrode of the eleventh transistor is connected with the sixth node, and the first pole and the second pole of the eleventh transistor are respectively connected with two ends of the ith element to be driven;

the second storage submodule comprises a second storage capacitor, a first electrode plate of the second storage capacitor is connected with the sixth node, and a second electrode plate of the second storage capacitor is connected with the first power supply end.

In some possible implementations, the pixel includes m elements to be driven, m being a positive integer greater than 2, and n being less than m.

In some possible implementations, the current control module is further connected to the control signal terminal, the reset signal terminal, and the initial signal terminal, and the current control module is configured to provide a driving electrical signal to the first node based on a signal of the first power terminal and a data signal of the first data signal terminal under the control of the first scan signal terminal, the control signal terminal, and the reset signal terminal;

the current control module includes:

the reset submodule is respectively connected with the initial signal terminal, the first node, the third node and the reset signal terminal and is configured to provide the initial signal of the initial signal terminal for the first node and the third node under the control of the reset signal terminal;

the second writing sub-module is respectively connected with the first data signal terminal, the first scanning signal terminal, the fourth node, the fifth node and the third node and is configured to provide a data signal of the first data signal terminal for the third node under the control of the first scanning signal terminal;

the first storage submodule is respectively connected with the third node and the first power supply end and is configured to store the data signal of the third node;

the driving submodule is respectively connected with the third node, the fourth node and the fifth node and is configured to provide corresponding electric signals to the fifth node based on the electric signals of the fourth node under the control of the third node;

and the switch control submodule is respectively connected with the first power supply end, the fourth node, the fifth node, the first node and the control signal end and is configured to provide a driving electric signal to the first node through the fourth node, the driving submodule and the fifth node based on the voltage of the first power supply end under the control of the control signal end.

In some possible implementations, the current control module includes at least one of:

the reset sub-module comprises a sixth transistor and a seventh transistor, the grid electrode of the sixth transistor is connected with the reset signal end, the first pole of the sixth transistor is connected with the initial signal end, and the second pole of the sixth transistor is connected with the third node; the grid electrode of the seventh transistor is connected with the reset signal end, the first pole of the seventh transistor is connected with the initial signal end, and the second pole of the seventh transistor is connected with the first node;

the second write-in submodule comprises a second transistor and a fourth transistor, the grid electrode of the second transistor is connected with the first scanning signal end, the first pole of the second transistor is connected with the first data signal end, and the second pole of the second transistor is connected with the fourth node; a grid electrode of the fourth transistor is connected with the first scanning signal end, a first pole of the fourth transistor is connected with the fifth node, and a second pole of the fourth transistor is connected with the third node;

the first storage submodule comprises a first storage capacitor, a first pole plate of the first storage capacitor is connected with a first power supply end, and a second pole plate of the first storage capacitor is connected with a third node;

the driving sub-module comprises a third transistor, the grid electrode of the third transistor is connected with a third node, the first pole of the third transistor is connected with a fourth node, and the second pole of the third transistor is connected with a fifth node;

the switch control submodule comprises a first transistor and a fifth transistor, the grid electrode of the first transistor is connected with the control signal end, the first electrode of the first transistor is connected with the first power supply end, and the second electrode of the first transistor is connected with the fourth node; the grid electrode of the fifth transistor is connected with the control signal end, the first pole of the fifth transistor is connected with the fifth node, and the second pole of the fifth transistor is connected with the first node.

As a second aspect of the embodiments of the present disclosure, an embodiment of the present disclosure provides a driving method of a pixel circuit, which is applied to the pixel circuit in the embodiments of the present disclosure, the method including:

in the data writing stage, providing a data signal of an ith sub-pixel data signal end to a second node;

in the light emitting stage, the potential of the second node is changed based on the signal of the time control signal end under the bootstrap action of the bootstrap submodule, and the switch submodule controls the conducting time length of the switch submodule under the control of the potential of the second node.

As a third aspect of the embodiments of the present disclosure, an embodiment of the present disclosure provides a driving method of a pixel circuit, which is applied to the pixel circuit in the embodiments of the present disclosure, and the method includes:

in the data writing stage, providing a data signal of an ith sub-pixel data signal end to a sixth node;

in the lighting phase, the current flowing through the regulating submodule is regulated based on the data signal of the sixth node.

As a fourth aspect of the embodiments of the present disclosure, embodiments of the present disclosure provide a display device including the pixel circuit in any one of the embodiments of the present disclosure.

According to the technical scheme of the embodiment of the disclosure, n to-be-driven elements D are sequentially connected in series, so that the requirements of each to-be-driven element can be met as long as a driving electrical signal, such as a driving current, provided to a first node is larger than or equal to the maximum current value in the currents of each to-be-driven element, and different gray scales of a pixel are realized through n gray scale control modules. The pixel circuit greatly reduces the current of one pixel, reduces the power consumption of the display device and improves the product competitiveness.

The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will be readily apparent by reference to the drawings and following detailed description.

Drawings

In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are not to be considered limiting of its scope.

FIG. 1 is a schematic diagram of a pixel circuit in the related art;

fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure;

FIG. 8 is a timing diagram illustrating operation of a pixel circuit according to an embodiment of the present disclosure;

FIG. 9a is a schematic diagram of a portion of a pixel circuit according to another embodiment of the present disclosure;

FIG. 9b is a schematic diagram of another portion of a pixel circuit according to another embodiment of the present disclosure;

FIG. 10 is a timing diagram illustrating the operation of the pixel circuit shown in FIGS. 9a and 9 b;

FIG. 11 is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure;

FIG. 12 is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a pixel circuit in another embodiment of the present disclosure.

Description of reference numerals:

10. a current control module; 11. resetting the submodule; 12. a second write submodule; 13. a first storage submodule; 14. a switch control submodule; 15. a second write submodule; 20. a unit to be driven; 30. a gray scale control module; 31. a time control module; 311. a first write submodule; 312. a bootstrap module; 313. a switch submodule; 32. a current control module; 321. a third write submodule; 322. a second storage submodule; 323. and adjusting the submodule.

Detailed Description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art can appreciate, the described embodiments can be modified in various different ways, without departing from the spirit or scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics, and the transistors used in embodiments of the present invention are mainly switching transistors depending on the role in the circuit. Since the source and drain of the switching transistor used herein are symmetrical, the source and drain may be interchanged. In the embodiments of the present invention, a source (source electrode) is referred to as a first pole and a drain (drain electrode) is referred to as a second pole, or alternatively, the drain may be referred to as the first pole and the source may be referred to as the second pole. In the form shown in the drawings, the transistor has a gate (which may be called a gate electrode) as an intermediate terminal, a source as a signal input terminal, and a drain as a signal output terminal. The switch transistor adopted by the embodiment of the invention can be a P-type switch transistor or an N-type transistor, wherein the P-type switch transistor is switched on when the grid electrode is at a low level and is switched off when the grid electrode is at a high level; the N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. In addition, the plurality of signals in the embodiments of the present invention correspond to the first potential and the second potential. The first potential and the second potential represent only 2 state quantities of the potential of the signal, and do not represent that the first potential or the second potential has a specific value throughout the text. In the embodiment of the present invention, the first potential is taken as an example of the effective potential.

Wherein the coupling may comprise: the two ends are electrically connected or the two ends are directly connected (for example, the two ends are connected through a signal wire). The embodiment of the present invention does not limit the coupling manner between the two ends.

Fig. 1 is a schematic structural diagram of a pixel circuit in the related art. In the related art, one pixel may include three light emitting devices R, G, B, and three light emitting devices R, G, B are connected in parallel, and different gray scales are implemented by combining current control and duration control. The three light emitting devices R, G, B are connected in parallel, that is, one pixel is composed of the light emitting device R, the light emitting device G, and the light emitting device B connected in parallel, and each individual light emitting device realizes different gray scales by a combination of a specific current and duration control circuit. In such a parallel manner, the pixel current of each pixel is the sum of three light emitting devices, and the pixel current is large, resulting in large voltage (IR) and power consumption.

The current control, i.e. the current magnitude is used to realize different gray scales, for example, in a pixel circuit of an Organic Light Emitting Diode (OLED), the current magnitude is controlled by a data voltage to switch a thin film transistor to realize different gray scales. Due to the small size of the LED light-emitting device, the color coordinates are unstable at low current, resulting in inconsistent low gray performance.

And time length control is to realize different gray scales by controlling the light emitting time length of the LED under the condition of ensuring that the LED light emitting device works at stable current.

Fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure. As shown in fig. 2, the pixel circuit may include a current control module 10, a unit to be driven 20, and n grayscale control modules 30.

The current control module 10 is respectively connected to the first power source terminal VDD, the first Data signal terminal Data, the first scan signal terminal Gate1 and the first node N1, and the current control module 10 is configured to supply a driving electric signal to the first node N1 based on a signal of the first power source terminal VDD and a Data signal of the first Data signal terminal Data under the control of the first scan signal terminal Gate 1.

The to-be-driven unit 20 includes N to-be-driven elements D, the N to-be-driven elements D are sequentially connected in series, a first pole of a first to-be-driven element D1 is connected to the first node N1, a second pole of an nth to-be-driven element Dn is connected to the second power supply terminal VSS, and N is a positive integer greater than 1.

The N gray scale control modules 30 are in one-to-one correspondence with the N to-be-driven elements D and are connected in parallel, the ith gray scale control module 30-i is respectively connected with the ith sub-pixel Data signal terminal Data-i and the second scanning signal terminal Gate2, and the N gray scale control modules 30 are configured to control the conduction time length of each to-be-driven element D in the process of transmitting a driving electric signal from the first node N1 to the second power supply terminal VSS based on the N sub-pixel Data signal terminals under the control of the second scanning signal terminal Gate 2; alternatively, the current flowing through each element D to be driven is controlled.

In the pixel circuit of the embodiment of the disclosure, N to-be-driven elements D are sequentially connected in series, N gray scale control modules 30 are in one-to-one correspondence with and connected in parallel with the N to-be-driven elements D, and the N gray scale control modules 30 are configured to control the on-time length of each to-be-driven element D in the process of transmitting a driving electrical signal from a first node N1 to a second power supply terminal VSS on the basis of N sub-pixel data signal terminals under the control of a second scanning signal terminal Gate 2; or, the current flowing through each element D to be driven is controlled, thereby realizing different gray scales of the pixel.

In the related art, a plurality of elements to be driven, for example, a plurality of LEDs, in one pixel are connected in parallel, and the current of one pixel is the sum of the currents of the plurality of LEDs. In the pixel circuit of the embodiment of the disclosure, n to-be-driven elements D are sequentially connected in series, so that the driving electrical signal provided to the first node, for example, the driving current, can meet the requirement of each to-be-driven element as long as the driving electrical signal is greater than or equal to the maximum current value in the currents of each to-be-driven element, and different gray scales of the pixel are realized by n gray scale control modules. The pixel circuit greatly reduces the current of one pixel, reduces the power consumption of the display device and improves the product competitiveness.

In one embodiment, the element to be driven may be a light emitting element, for example, the element to be driven may be any one of an organic light emitting diode OLED, a quantum dot light emitting diode, and an LED of an inorganic light emitting diode. The element to be driven may employ a Micro-scale light emitting element, such as a Micro light emitting diode (Micro LED), a submillimeter light emitting diode (Mini LED), or a Micro organic light emitting diode (Micro OLED). The embodiments of the present disclosure are not limited thereto. For example, taking the element to be driven as the light emitting element LED as an example, the element to be driven may include a first pole (e.g., an anode) and a second pole (e.g., a cathode).

Fig. 3 is a schematic structural diagram of a pixel circuit according to another embodiment of the disclosure. In one embodiment, as shown in fig. 3, the n gray-scale control modules 30 may include n time control modules 31, and the n time control modules 31 are connected in parallel with the n to-be-driven elements D in a one-to-one correspondence. The ith time control module 31-i is respectively connected with the ith sub-pixel Data signal terminal Data-i, the second scan signal terminal Gate2 and the time control signal terminal PWM, and the N time control modules 31 are configured to control the on-time length of each element D to be driven in the process of transmitting the driving electric signal from the first node N1 to the second power source terminal VSS based on the Data signal of the N sub-pixel Data signal terminals Data-i and the signal of the time control signal terminal PWM under the control of the second scan signal terminal Gate 2.

In the following embodiments, the description of the embodiments is made by taking n as 3 and the to-be-driven elements are the to-be-driven element R, the to-be-driven element G, and the to-be-driven element B as examples, in which case, Data-1 may be referred to as Data _ R, Data-2 may be referred to as Data _ G, and Data-3 may be referred to as Data _ B.

For example, gray scales of the element to be driven R, the element to be driven G, and the element to be driven B in the pixel may be calculated according to image data to be presented, so as to obtain a current of the element to be driven R, a current of the element to be driven G, and a current of the element to be driven B. Since R, G, B are connected in series, in the process of transmitting the electrical signal from the first node N1 to the second power supply terminal VSS, in order to meet the requirements of each element to be driven, the current flowing through each element to be driven may be the maximum value among the current of the element to be driven R, the current of the element to be driven G and the current of the element to be driven B. That is, taking R, G, B as examples of the elements to be driven, respectively, then I_pixel＝Max{I_R，I_G，I_BIn which I_pixelIs a pixel current, I_RIs the current of the element R to be driven, I_GIs the current of the element G to be driven, I_BIs the current of the element B to be driven. The driving chip (Driver IC) in the display device can be based on the pixel current I_pixelGenerating a corresponding data signal V_dataThe Data signal is supplied to the current control block 10 through the first Data signal terminal Data. Accordingly, the current control module 10 may provide the pixel current I to the first node N1 based on the Data signal of the first Data signal terminal Data under the control of the first scan signal terminal Gate1_pixelMatched drive current.

It is understood that the driving current provided by the current control module 10 to the first node N1 may be greater than the pixel current I_pixelThe on-time length of each element D to be driven is controlled by the n time control modules 31, so as to realize the light emitting duration of each element D to be driven in one frame, and further realize the gray scale corresponding to each element D to be driven.

Therefore, in the pixel circuit of the embodiment of the present disclosure, the current flowing through each element D to be driven isGreater than or equal to pixel current I_pixelThe n time control modules 31 control the light emitting duration of each element D to be driven in one frame based on the Data signals of the n sub-pixel Data signal terminals Data-i and the signals of the time control signal terminals PWM, so that the equivalent current of each element D to be driven in one frame corresponds to the gray scale, thereby realizing the corresponding gray scale of each element D to be driven. The pixel circuit can ensure that each element D to be driven can still work under stable larger current in low gray scale, and can keep high enough refresh rate in low gray scale, thereby effectively avoiding the problem of low gray scale flicker of display products.

Fig. 4 is a schematic structural diagram of a pixel circuit in another embodiment of the present disclosure. In one embodiment, as shown in fig. 4, the time control module 31 may include a first write submodule 311, a bootstrap submodule 312, and a switch submodule 313.

As shown in fig. 4, the first write submodule 311 is connected to the ith sub-pixel Data signal terminal Data-i, the second scan signal terminal Gate2, and the second node N2, respectively, and the first write submodule 311 is configured to supply the Data voltage of the ith sub-pixel Data signal terminal Data-i to the second node N2 under the control of the second scan signal terminal Gate 2. It is understood that, in the case where the level supplied from the second scan signal terminal Gate2 is an active level, the first write submodule 311 supplies the Data voltage of the ith sub-pixel Data signal terminal Data-i to the second node N2.

As shown in fig. 4, the bootstrap sub-module 312 is respectively connected to the second node N2 and the time control signal terminal PWM, and the potential of the second node N2 is changed by the bootstrap sub-module 312 based on the signal of the time control signal terminal PWM.

As shown in fig. 4, the switch sub-modules 313 are respectively connected to both ends of the corresponding to-be-driven element Di and the second node N2, and the switch sub-modules 313 are configured such that both ends of the corresponding to-be-driven element Di are connected through the switch sub-modules 313 under the control of the second node N2. In the case where the level provided by the second node N2 is the active level, the switch submodule 313 is turned on, so that the current flows through the switch submodule 313 without flowing through the corresponding to-be-driven element Di, and the to-be-driven element Di is short-circuited.

The time control signal terminal PWM is used for generating a Pulse Width Modulation (PWM) signal, and the PWM signal includes a signal with an amplitude varying with time, and may include a falling edge and/or a rising edge. In one embodiment, the PWM signal may be a triangular wave signal in which both the falling edge and the rising edge of the signal waveform are sloped. In another embodiment, the PWM signal may be a sawtooth signal, i.e., a single-edge ramp signal, including a rising edge or a falling edge, which is a ramp. Such a time control signal terminal may generate a gradually changing signal, so that the potential of the second node N2 may be adjusted, such that the potential of the second node N2 is changed based on the signal of the time control signal terminal PWM, and the on-time of the switch sub-module 313 may be adjusted.

In the pixel circuit of the embodiment of the disclosure, the system end of the display device may generate the sub-pixel data voltage corresponding to the gray scale of each element to be driven according to the gray scale data. The data voltage output from the sub-pixel data signal terminal is written into the second node N2 through the first write submodule 311, and the potential of the second node N2 is changed by the bootstrap submodule 312 based on the signal of the time control signal terminal PWM. When the potential of the second node N2 satisfies the conduction condition of the switch submodule 313, the second node N2 controls the switch submodule 313 to conduct, and current flows through the switch submodule 313, so that the corresponding element to be driven is short-circuited. Therefore, by controlling the on-time of the switch sub-module 313, the short-circuited time of the corresponding element to be driven can be controlled, and further the working time of the corresponding element to be driven in one frame is controlled, so that the equivalent current of the element to be driven in one frame corresponds to the gray scale, and the corresponding gray scale of the element to be driven D is realized.

Fig. 5 is a schematic structural diagram of a pixel circuit according to another embodiment of the disclosure. In one embodiment, as shown in fig. 5, the first writing sub-module 311 may include a ninth transistor T9, a Gate of the ninth transistor T9 being connected to the second scan signal terminal Gate2, a first pole of the ninth transistor T9 being connected to the ith sub-pixel Data signal terminal Data-i, and a second pole of the ninth transistor T9 being connected to the second node N2.

In one embodiment, as shown in fig. 5, the bootstrap sub-module 312 may include a bootstrap capacitor C, a first plate of which is connected to the second node N2, and a second plate of which is connected to the time control signal terminal PWM.

In one embodiment, as shown in fig. 5, the switching submodule 313 may include an eighth transistor T8, a gate of the eighth transistor T8 is connected to the second node N2, and a first pole and a second pole of the eighth transistor T8 are connected to the first pole and the second pole of the ith element D to be driven, respectively.

It should be noted that fig. 5 shows an exemplary structure of the first write submodule, the bootstrap submodule, and the switch submodule, and those skilled in the art can understand that the first write submodule, the bootstrap submodule, and the switch submodule are not limited to the structure shown in fig. 5 as long as the functions thereof can be implemented.

Fig. 6 is a schematic structural diagram of a pixel circuit according to another embodiment of the disclosure. In one embodiment, as shown in fig. 6, the current control module 10 is further connected to the control signal terminal EM, the reset signal terminal RST and the initial signal terminal Vinit, and the current control module 10 is configured to provide a driving electric signal to the first node N1 based on a signal of the first power terminal VDD and a Data signal of the first Data signal terminal Data under the control of the first scan signal terminal Gate1, the control signal terminal EM and the reset signal terminal RST.

The current control module 10 may include a reset sub-module 11, a second write sub-module 12, a first storage sub-module 13, a switch control sub-module 14, and a drive sub-module 15.

The reset submodule 11 is connected to the initial signal terminal Vinit, the first node N1, the third node N3, and the reset signal terminal RST. The reset submodule 11 is configured to provide an initial signal of the initial signal terminal Vinit to the first node N1 and the third node N3 under the control of the reset signal terminal RST, so as to reset the first node N1 and the third node N3.

The second write submodule 12 is connected to the first Data signal terminal Data, the first scan signal terminal Gate1, the fourth node N4, the fifth node N5, and the third node N3, respectively. The second write submodule 12 is configured to supply the Data signal of the first Data signal terminal Data to the third node N3 under the control of the first scan signal terminal Gate 1.

The first memory sub-module 13 is connected to the third node N3 and the first power terminal VDD, respectively, and is configured to store the charge of the third node N3.

The driving sub-module 15 is respectively connected with the third node N3, the fourth node N4 and the fifth node N5, and is configured to provide a corresponding electrical signal to the fifth node N5 based on the electrical signal of the fourth node N4 under the control of the third node N3.

The switch control submodule 14 is connected to the first power supply terminal VDD, the fourth node N4, the fifth node N5, the first node N1 and the control signal terminal EM, respectively, and is configured to supply a driving electric signal to the first node N1 through the fourth node N4, the driving submodule 15 and the fifth node N5 based on the voltage of the first power supply terminal VDD under the control of the control signal terminal EM.

Illustratively, in the process of supplying the Data signal of the first Data signal terminal Data to the third node N3, the driving sub-module 15 is turned on under the control of the third node N3, so that the Data signal of the first Data signal terminal Data is written to the third node N3 through the second writing sub-module 12, the fourth node N4, the driving sub-module 15, and the fifth node N5. In the process that the switch control submodule 14 supplies the driving electric signal to the first node N1 based on the first power source terminal VDD, the driving submodule 15 makes the first power source terminal VDD supply the driving electric signal to the first node N1 through the switch control submodule 14, the fourth node N4, the driving submodule 15 and the fifth node N5 under the control of the data signal of the third node N3.

Fig. 6 shows a pixel circuit obtained by combining the current control module 10 and the n time control modules shown in fig. 5. It will be appreciated that the current control module shown in fig. 6 may be equally applicable to the pixel circuits shown in fig. 2, 3 or 4 in one exemplary embodiment.

Fig. 7 is a schematic structural diagram of a pixel circuit in another embodiment of the present disclosure. In one embodiment, as shown in fig. 7, the reset sub-module 11 may include a sixth transistor T6 and a seventh transistor T7, a gate of the sixth transistor T6 is connected to the reset signal terminal RST, a first pole of the sixth transistor T6 is connected to the initial signal terminal Vinit, and a second pole of the sixth transistor T6 is connected to the third node N3; the gate of the seventh transistor T7 is connected to the reset signal terminal RST, the first pole of the seventh transistor T7 is connected to the initial signal terminal Vinit, and the second pole of the seventh transistor T7 is connected to the first node N1.

In one exemplary embodiment, as shown in fig. 7, the second write sub-module 12 may include a second transistor T2 and a fourth transistor T4, a Gate of the second transistor T2 is connected to the first scan signal terminal Gate1, a first pole of the second transistor T2 is connected to the first Data signal terminal Data, and a second pole of the second transistor T2 is connected to the fourth node N4; a Gate of the fourth transistor T4 is connected to the first scan signal terminal Gate1, a first pole of the fourth transistor T4 is connected to the fifth node N5, and a second pole of the fourth transistor T4 is connected to the third node N3.

In one exemplary embodiment, as shown in fig. 7, the first storage sub-module 13 may include a first storage capacitor C1, a first plate of the first storage capacitor C1 being connected to the first power terminal VDD, and a second plate of the first storage capacitor C2 being connected to the third node N3.

In one exemplary embodiment, as shown in fig. 7, the switch control submodule 14 may include a first transistor T1 and a fifth transistor T5. A gate of the first transistor T1 is connected to the control signal terminal EM, a first pole of the first transistor T1 is connected to the first power source terminal VDD, and a second pole of the first transistor T1 is connected to the fourth node N4; a gate of the fifth transistor T5 is connected to the control signal terminal EM, a first pole of the fifth transistor T5 is connected to the fifth node N5, and a second pole of the fifth transistor T5 is connected to the first node N1.

In one exemplary embodiment, as shown in fig. 7, the driving sub-module 15 includes a third transistor T3. A gate of the third transistor T3 is connected to the third node N3, a first pole of the third transistor T3 is connected to the fourth node N4, and a second pole of the third transistor T3 is connected to the fifth node N5.

Exemplarily, fig. 7 shows an exemplary structure of the reset submodule 11, the second write submodule 12, the first storage submodule 13, the switch control submodule 14 and the driving submodule 15, and it can be understood by those skilled in the art that the reset submodule 11, the second write submodule 12, the first storage submodule 13, the switch control submodule 14 and the driving submodule 15 are not limited to the structure shown in fig. 7 as long as the functions thereof can be realized.

The current control module 10 in the pixel circuit shown in fig. 7 has a 7T1C structure, and it is understood that the current control module 10 is not limited to the 7T1C structure, and the current control module 10 may adopt a pixel driving circuit capable of controlling the amplitude of the output current by controlling the amplitude of the input voltage in the related art, such as 2T1C, 3T1C, 4T1C, 5T1C, etc., as long as the function of the current control module can be achieved.

In an exemplary embodiment, the types of the first to ninth transistors T1 to T9 may be the same, or the types of the first to ninth transistors T1 to T9 may not be the same. For example, the first to ninth transistors T1 to T9 may be P-type transistors, or the first to ninth transistors T1 to T9 may be N-type transistors. The same type of transistors are adopted in the pixel circuit, so that the process flow can be simplified, the process difficulty is reduced, and the yield of products is improved. For example, the P-type transistor may be implemented by a low temperature polysilicon thin film transistor or an amorphous silicon thin film transistor, and the N-type transistor may be implemented by an oxide thin film transistor or an amorphous silicon thin film transistor.

In the pixel circuit shown in fig. 7, the number n of the to-be-driven elements is 3, which is R, G, B respectively, and correspondingly, the number of the time control modules 31 is also 3, the first sub-pixel Data signal terminal is Data-R, the second sub-pixel Data signal terminal is Data-G, and the third sub-pixel Data signal terminal is Data-B.

Fig. 8 is a timing diagram illustrating an operation of a pixel circuit according to an embodiment of the disclosure. The pixel circuit shown in fig. 7 can adopt the operation timing shown in fig. 8. The operation timing diagram shown in fig. 8 may include a first stage T1, a second stage T2, and a third stage T3.

The first phase T1 can be called a reset phase, and in the first phase T1, the control signal terminal EM is at an inactive level, the reset signal terminal RST is at an active level, and the first scan signal terminal Gate1 is at an inactive level. The first transistor T1 and the fifth transistor T5 are turned off under the control of the control signal terminal EM; the second transistor T2 and the fourth transistor T4 are turned off under the control of the first scan signal terminal Gate 1; under the control of the reset signal terminal RST, the sixth transistor T6 and the seventh transistor T7 are turned on, and the initial signal of the initial signal terminal Vinit is supplied to the first node N1 and the third node N3, thereby resetting the first node N1 and the third node N3.

The second phase T2 can be called a write data phase, and in the second phase T2, the control signal terminal EM is at an inactive level, the reset signal terminal RST is at an inactive level, and the first scan signal terminal Gate1 is at an active level. The first transistor T1 and the fifth transistor T5 are turned off under the control of the control signal terminal EM; the sixth and seventh transistors T6 and T7 are turned off under the control of the reset signal terminal RST; the second transistor T2 and the fourth transistor T4 are turned on under the control of the first scan signal terminal Gate 1; the third transistor T3 is turned on under the control of the first node N1. The Data signal of the first Data signal terminal Data is written into the third node N3 through the second transistor T2, the fourth node N4, the third transistor T3, the fifth node N5, and the fourth transistor T4. The first storage capacitor C1 stores the data signal of the third node N3.

In the second phase T2, the second scan signal terminal Gate2 is at an active level, and under the control of the second scan signal terminal Gate2, the ninth transistor T9 in each time control block 31 is turned on, and the data signal of each sub-pixel data signal terminal is written into the corresponding second node N2. As shown in fig. 7, the Data signal Data-R of the first sub-pixel Data signal terminal is written into the second node N2 corresponding to R; the Data signal Data-G of the second sub-pixel Data signal terminal is written in the second node N2 corresponding to G, and the Data signal Data-B of the third sub-pixel Data signal terminal is written in the second node N2 corresponding to B.

The third stage T3 can be called a light emitting stage, in the third stage T3, the control signal terminal EM is at an active level, the reset signal terminal RST is at an inactive level, the first scan signal terminal Gate1 is at an inactive level, and the second scan signal terminal Gate2 is at an inactive level. The first transistor T1 and the fifth transistor T5 are both turned on under the control of the control signal terminal EM, and the third transistor T3 supplies a driving current to the first node N1 based on the voltage of the first power source terminal VDD under the control of the third node N3.

The system terminal of the display device provides Data signals to the current control module 10 through the first Data signal terminal Data according to the gray scale Data, and controls the current control module to generate the pixel current I_pixel＝Max{I_R，I_G，I_B}. With I_pixel＝I_RFor example, at this time, the current control module 10 outputs the current I required by the device to be driven R to the first node N1_R. The current flowing through the element G to be driven and the element B to be driven is also I_R。

In the third stage T3, the second node N2 is in a floating state. In order to control the elements G and B to be driven to generate corresponding gray scales, the voltage of the corresponding second node N2 may be controlled by the time control signal terminal PWM to control the light emitting time of the elements B and G to be driven in one frame to realize the corresponding gray scales. For example, the current I actually required by the element G to be driven_G＝0.5I_RThe Data signal Data-G of the second node N2 and the PWM signal output by the time control signal terminal PWM control the switching state of the corresponding eighth transistor T8. As shown in fig. 8, as the PWM signal decreases, the voltage of the corresponding second node N2 decreases due to the bootstrap capacitor C, and when the voltage of the second node N2 is less than the threshold voltage Vth of the eighth transistor T8, the eighth transistor T8 corresponding to the sub-pixel G is turned on, and I is turned on_pixelFlowing through the eighth transistor T8, the element G to be driven is short-circuited and no current flows and does not emit light; as the PWM signal increases, the voltage of the corresponding second node N2 increases, and when the voltage of the second node N2 is greater than the threshold voltage Vth of the eighth transistor T8, the eighth transistor T8 corresponding to the sub-pixel G is turned off, and I_pixelFlows through the element G to be driven. In this way, the light emitting duration of the element G to be driven in one frame can be controlled to realize the corresponding gray scale. The control method of the element to be driven B is the same as that of the element to be driven G, and is not described herein again.

As can be seen from fig. 8, when the data signals output from the sub-pixel data signal terminals are different, the on-time of the eighth transistor T8 is different, and the time of the current flowing through the element to be driven is different. Accordingly, the on-period of the eighth transistor T8 can be controlled by the data signal of the sub-pixel data signal terminal and the PWM signal output from the timing control signal terminal, thereby controlling the period during which the current flows through the element to be driven.

In the embodiment of the present disclosure, as shown in fig. 8, the duty ratio of the PWM signal is a time period occupied by a signal for turning on an element (i.e., the eighth transistor T8) connected to the time control signal terminal in one period, and the period and the duty ratio of the PWM signal are schematically shown in fig. 8. It can be understood that the duty ratio is related to the Data signal of the sub-pixel Data signal terminal Data-i, and when the Data signal of the sub-pixel Data signal terminal Data-i is different, the turn-on time periods of the corresponding eighth transistors T8 are different, and the duty ratios of the corresponding PWM signals are different.

Illustratively, the frequency of the PWM signal output by the time control signal end can be increased to improve the refresh rate of the product in the light-emitting stage and avoid the problem of low-gray flicker.

In the above embodiment, n is set to 3, it is understood that n is not limited to 3, and n may be 2 or 4 or other positive integer greater than 1. The element to be driven is not limited to red (R), green (G), blue (B), and the element to be driven may be an element that generates other colors such as white.

Note that the transistors in the pixel circuit shown in fig. 7 are all P-type transistors. It is to be understood that when the transistors in the pixel circuit employ N-type transistors, the states of the respective signals in the timing chart, such as EM, RST, Gate1, PWM, etc., may be reversed from fig. 8.

Fig. 9a is a schematic partial structure diagram of a pixel circuit in another embodiment of the present disclosure, and fig. 9b is a schematic partial structure diagram of a pixel circuit in another embodiment of the present disclosure. In one embodiment, the pixel comprises m elements to be driven, m being a positive integer greater than 2. n is greater than or equal to 2 and n is less than m.

In one embodiment, as shown in fig. 9a and 9b, one pixel may include 3 sub-pixels, i.e., 3 elements to be driven. Wherein 2 elements to be driven (e.g., G and B) employ the pixel circuit in the embodiment of the present disclosure, and the element to be driven R employs the pixel circuit of 7T 1C. That is, in the embodiment shown in fig. 9a and 9b, in the case where the pixel includes more than 2 elements to be driven, part of the elements to be driven in the pixel may be driven using the pixel circuit in the embodiment of the present disclosure, and the remaining elements to be driven may be driven using a conventional pixel circuit such as 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, or the like.

For m elements to be driven, which need to adopt the pixel circuit in the embodiment of the present disclosure, the current of each element to be driven can be determined. For example, the m elements to be driven are R, G and B, respectively, Data1 in FIG. 9a can be referred to as Data _ R, Data2 in FIG. 9B can be referred to as Data _ GB, Data-1 can be referred to as Data _ G, and Data-2 can be referred to as Data _ B. If the working current of the to-be-driven element R is large and the working voltage Vf is small, and the working currents of the to-be-driven elements G and B are small and the working voltage Vf is large, the to-be-driven elements G and B may be connected in series, the to-be-driven elements G and B may be driven by using the pixel circuit in the embodiment of the present disclosure, and the to-be-driven element R may be driven by using the conventional pixel circuit alone, as shown in fig. 9a and 9B.

Fig. 10 is a timing diagram illustrating the operation of the pixel circuit shown in fig. 9a and 9 b. For the element to be driven R in fig. 9a and 9b, the operation timing is the same as that of the pixel circuit 7T1C in the conventional technology, and the description thereof is omitted. For the to-be-driven elements G and B in fig. 9a and 9B, the operation principle and timing are the same as those in fig. 8, and are not described again here.

In one embodiment, the first power source terminal VDD generates a high level, for example, 6.6V; the second power source terminal VSS generates a low level, for example, -3V; the initial signal terminal Vinit generates an initial signal, for example-3V.

Fig. 11 is a schematic structural diagram of a pixel circuit in another embodiment of the present disclosure. In one embodiment, as shown in fig. 11, the N gray scale control modules include N current adjustment modules 32, the N current adjustment modules 32 correspond to the N to-be-driven elements D in a one-to-one manner and are connected in parallel, the ith current adjustment module 32-i is connected to the ith sub-pixel Data signal terminal Data-i, and the N current adjustment modules are configured to adjust the current flowing through each to-be-driven element D during the transmission of the driving electrical signal from the first node N1 to the second power source terminal VSS based on the Data signals of the N sub-pixel Data signal terminals.

The current adjusting module in the embodiment of the disclosure is connected in parallel with the element to be driven, so that the current adjusting module can generate a shunting effect, and the current flowing through the corresponding element to be driven can be adjusted by adjusting the current flowing through the current adjusting module, thereby realizing the gray scale of the element to be driven.

Illustratively, the 3 elements to be driven in fig. 11 may be R, G, B, respectively. The system end of the display device can control the current control module to generate pixel current I according to the gray scale data_pixel＝Max{I_R，I_G，I_B}. With I_pixel＝I_RFor example, at this time, the current control module 10 outputs the current I required by the device to be driven R to the first node N1_R. The current flowing through the element G to be driven and the element B to be driven is also I_R. In order to control the current flowing through the element G to be driven and the current flowing through the element B to be driven to correspond to the gray scale, the corresponding current adjusting module may adjust the current flowing through the current adjusting module based on the data signal of the corresponding sub-pixel data signal terminal, so as to adjust the current flowing through the corresponding element to be driven, thereby implementing the corresponding gray scale. For example, the actual required current of the element G to be driven is I_G＝0.5I_R. The current adjusting module 32-2 can be controlled by the data signal of the sub-pixel data signal terminal corresponding to the element G to be driven, so that the current flowing through the current adjusting module 32-2 is 0.5I_RSo that the actual current flowing through the element to be driven G is 0.5I_RAnd realizing the corresponding gray scale. The driving principle of the element to be driven B is the same as that of the element to be driven G, and is not described herein again.

Fig. 12 is a schematic structural diagram of a pixel circuit according to another embodiment of the disclosure. In one embodiment, as shown in FIG. 12, the current regulation module includes a third write submodule 321, a regulation submodule 323, and a second storage submodule 322.

In one embodiment, the third write submodule 321 is respectively connected to the ith sub-pixel Data signal terminal Data-i, the second scan signal terminal Gate2 and the sixth node N6, and is configured to supply the Data signal of the ith sub-pixel Data signal terminal Data-i to the sixth node N6 under the control of the second scan signal terminal Gate 2.

In one embodiment, the adjusting sub-module 323 is connected to the sixth node N6 and both ends of the ith element to be driven Di, respectively, and configured to adjust the current flowing through the adjusting sub-module 323 based on the data signal of the sixth node N6;

in one embodiment, the second storage submodule 322 is connected to the sixth node N6 and the first power terminal VDD, respectively, and is configured to store the data voltage of the sixth node N6.

The current adjusting module in the embodiment of the present disclosure may adjust the current flowing through the adjusting sub-module 323 according to the data signal of the sixth node N6, so as to adjust the current flowing through the corresponding element to be driven, thereby implementing the corresponding gray scale.

Fig. 13 is a schematic structural diagram of a pixel circuit in another embodiment of the present disclosure. In one embodiment, as shown in fig. 13, the third write sub-module 321 includes a tenth transistor T10, a Gate of the tenth transistor T10 is connected to the second scan signal terminal Gate2, a first pole of the tenth transistor T10 is connected to the ith sub-pixel Data signal terminal Data-i, and a second pole of the tenth transistor T10 is connected to the sixth node N6;

in one embodiment, as shown in fig. 13, the adjusting sub-module 323 includes an eleventh transistor T11, a gate of the eleventh transistor T11 is connected to the sixth node N6, and a first pole and a second pole of the eleventh transistor T11 are respectively connected to both ends of the ith element to be driven Di;

in one embodiment, as shown in fig. 13, the second storage submodule 322 includes a second storage capacitor C2, a first plate of the second storage capacitor C2 is connected to the sixth node N6, and a second plate of the second storage capacitor C2 is connected to the first power terminal VDD.

Exemplarily, in the second stage T2 of the pixel circuit, the tenth transistor T10 writes the Data signal of the ith sub-pixel Data signal terminal Data-i into the sixth node N6 under the control of the second scan signal terminal Gate, and the second storage capacitor C2 stores the Data signal of the sixth node N6; in the third stage T2 of the pixel circuit, the eleventh transistor T11 adjusts the current flowing through the eleventh transistor T11 under the control of the sixth node N6 so that the current flowing through the element to be driven Di corresponds to a gray scale, and a corresponding gray scale is realized. It is to be understood that the eleventh transistor T11 is a driving transistor, and when the data signals at the sixth node N6 are different, the current flowing between the first pole and the second pole of the eleventh transistor T11 is different.

The current regulation module shown in fig. 13 has a structure of 2T 1C. In other embodiments, the current regulation module may adopt a structure of 3T1C, 4T1C, 5T1C, 6T1C or 7T1C in a conventional OLED pixel circuit, and a first pole and a second pole of a driving transistor in the OLED pixel circuit are respectively connected in parallel with two ends of a corresponding element to be driven.

Exemplarily, an exemplary structure of the third writing sub-module 321, the adjusting sub-module 323, and the second storing sub-module 322 is shown in fig. 13, and it can be understood by those skilled in the art that the third writing sub-module 321, the adjusting sub-module 323, and the second storing sub-module 322 are not limited to the structure shown in fig. 13 as long as functions thereof can be realized.

It will be appreciated that the current regulation module is equally applicable to the embodiments shown in figures 6 and 7.

The embodiment of the disclosure also provides a driving method of the pixel circuit, which is suitable for the pixel circuit in the above embodiments. The driving method of the pixel circuit may include: in the data writing phase (i.e., the second phase t2), the data signal of the ith sub-pixel data signal terminal is supplied to the second node; in the light emitting stage (i.e. the third stage t3), the potential of the second node changes based on the signal of the time control signal terminal under the bootstrap action of the bootstrap submodule, and the switch submodule controls the conducting time length of the switch submodule under the control of the potential of the second node.

Refer to the pixel circuit of any one of fig. 4-7. In the Data writing phase, the first write sub-module 311 supplies the Data signal of the ith sub-pixel Data signal terminal Data-i to the second node N2 under the control of the second scan signal terminal Gate 2. In the light emitting period, the potential of the second node N2 is changed by the bootstrap of the bootstrap submodule 312 based on the signal of the time control signal terminal PWM, and the switch submodule 313 controls the conducting time length of the switch submodule 313 under the control of the potential of the second node N2.

The embodiment of the disclosure also provides a driving method of the pixel circuit, which is suitable for the pixel circuit in the above embodiments. The driving method of the pixel circuit may include: in the data writing phase (i.e., the second phase t2), the data signal of the ith sub-pixel data signal terminal is supplied to the sixth node; during the lighting phase (i.e., the second phase t3), the current flowing through the regulating submodule is regulated based on the data signal of the sixth node.

Reference is made to the pixel circuit of either of the embodiments of fig. 12 and 13. In the Data writing phase, the third write submodule 321 supplies the Data signal of the ith sub-pixel Data signal terminal Data-i to the sixth node N6 under the control of the second scan signal terminal Gate2, and the second storage submodule 322 stores the Data signal of the sixth node N6; during the light-up phase, the data signal at the sixth node regulates the current flowing through the regulation submodule 323.

Based on the inventive concept of the foregoing embodiments, embodiments of the present disclosure also provide a display device including the pixel circuit in any embodiment of the present disclosure. The display device may be an OLED display device or an LED display device, etc. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

In the description of the present specification, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present disclosure and to simplify the description, but are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present disclosure.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

In the present disclosure, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise the first and second features being in direct contact, or may comprise the first and second features being in contact, not directly, but via another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.

The above disclosure provides many different embodiments or examples for implementing different features of the disclosure. The components and arrangements of specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present disclosure. Moreover, the present disclosure may repeat reference numerals and/or reference letters in the various examples, which have been repeated for purposes of simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed.

While the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.