阅读说明：本技术 一种基于时间竞争的同步信号生成电路 (Synchronous signal generating circuit based on time competition ) 是由 王世晨 陈雷清 彭志辉 于 2020-11-27 设计创作，主要内容包括：本发明公开了一种基于时间竞争的同步信号生成电路,包括：控制芯片,其上升沿中断输入用于实现对Syn信号上升沿的捕获,其PWM输出端口输出PWM信号,其I/O输出端口输出信号CTL-(Tri)用于控制三态门G1的通断；三态门G1,其输入端与所述控制芯片1的PWM输出端口连接、其控制端与所述控制芯片1的输出信号CTL-(Tri)连接,其输出端与同步信号Syn连接；接线端子J,用于接入/输出同步信号Syn；电阻R,其一端与所述同步信号Syn连接,另一端与地连接,用于保证同步信号Syn电平的确定性。本发明具有结构简单,成本低、速度快、抗干扰能力强、可靠性高和实用性好的特点。(The invention discloses a synchronizing signal generating circuit based on time competition, which comprises: a control chip, the rising edge interrupt input of which is used for realizing the capture of the rising edge of the Syn signal, the PWM output port of which outputs the PWM signal, and the I/O output port of which outputs a signal CTL Tri The three-state gate G1 is used for controlling the on-off of the three-state gate; a tri-state gate G1, the input terminal of which is connected with the PWM output port of the control chip 1, and the control terminal of which is connected with the output signal CTL of the control chip 1 Tri A connection, the output of which is connected to the synchronization signal Syn; the connecting terminal J is used for accessing/outputting a synchronous signal Syn; and one end of the resistor R is connected with the synchronous signal Syn, and the other end of the resistor R is connected with the ground, and the resistor R is used for ensuring the certainty of the level of the synchronous signal Syn. The invention has the characteristics of simple structure, low cost, high speed, strong anti-interference capability, high reliability and good practicabilityAnd (4) point.)

1. A synchronization signal generation circuit based on time contention, comprising: the control chip, the tri-state gate G1, the connecting terminal J and the resistor R;

a control chip, the rising edge interrupt input of which is used for realizing the capture of the rising edge of the Syn signal, the PWM output port of which outputs the PWM signal, and the I/O output port of which outputs a signal CTL_TriThe three-state gate G1 is used for controlling the on-off of the three-state gate;

a tri-state gate G1, the input terminal of which is connected with the PWM output port of the control chip 1, and the control terminal of which is connected with the output signal CTL of the control chip 1_TriA connection, the output of which is connected to the synchronization signal Syn;

the connecting terminal J is used for accessing/outputting a synchronous signal Syn;

and one end of the resistor R is connected with the synchronous signal Syn, and the other end of the resistor R is connected with the ground, and the resistor R is used for ensuring the certainty of the level of the synchronous signal Syn.

2. The time-competition based synchronization signal generation circuit according to claim 1, wherein the generation method of the time-competition based synchronization signal circuit is performed by:

initializing a program for initializing PWM module output and interrupt setting, Syn loss timer setting, rising edge interrupt setting and I/O output setting;

second, the PWM overflow interrupt processing program realizes the power-on delay and the CTL of the I/O output signal_TriControl of (2);

rising edge interrupt processing program to realize the identification of the rising edge of the Syn signal and the zero clearing control of the Syn loss timer;

and (4) the yn loss timer overflows an interrupt processing program to realize the resetting of related parameters so as to restart the competition of the Syn.

Technical Field

The present invention relates to a system synchronization method, and more particularly, to a synchronization signal generation circuit based on time contention.

Background

In the fields of control such as machinery, electronics, electricity, power, computers, and chemical engineering, it is generally necessary to control a plurality of devices in synchronization. For example: in a solar power generation system, when inverters supply power in parallel, the phase of voltage needs to be synchronously output; when the UPS supplies power, the inverter supplies power in parallel and also needs to synchronize the phase of the output voltage; in the field of multi-axis numerical control machining, synchronous adjustment and control of controllers with multiple degrees of freedom are required. The synchronous control performance is directly related to the output performance of the system, and even the safe and reliable operation of the system. It can be seen that the synchronization signal is a precondition for realizing the synchronization control.

The existing synchronization signal is mainly realized by two schemes: first, external synchronization signal scheme — the external device provides a reference signal as the synchronization signal. There is a major problem of poor reliability. Once the synchronous signal generator fails or is lost, the system cannot realize synchronous control, which causes the control disorder of the whole system and leads to system failure. Two, synchronization scheme based on a communication bus-each device of the system sends an identification code with unique characteristics (e.g. the SN number of the chip) to the other devices and receives the identification codes of the other devices of the system via the communication bus. The master modules in the system are then determined by a specific algorithm (e.g., solving for the maximum or minimum value of the identification code values) based on the identification codes of all devices in the system. The main module takes the functions of coordinating and controlling the whole system, including synchronization, current sharing, status information uploading, command issuing and the like.

The existing synchronous signal generation method has poor reliability, or needs communication bus networking and complex algorithms, and has prominent defects in the aspects of cost, reliability, circuit scale, software program complexity and the like.

Disclosure of Invention

The invention aims to provide a synchronizing signal generating circuit based on time competition. The invention has the characteristics of simple structure, low cost, high speed, strong anti-interference capability, high reliability and good practicability.

The technical scheme of the invention is as follows: a synchronization signal generation circuit based on time contention, comprising: the control chip, the tri-state gate G1, the connecting terminal J and the resistor R;

a control chip, the rising edge interrupt input of which is used for realizing the capture of the rising edge of the Syn signal, the PWM output port of which outputs the PWM signal, and the I/O output port of which outputs a signal CTL_TriThe three-state gate G1 is used for controlling the on-off of the three-state gate;

a tri-state gate G1, the input terminal of which is connected with the PWM output port of the control chip 1, and the control terminal of which is connected with the output signal CTL of the control chip 1_TriA connection, the output of which is connected to the synchronization signal Syn;

the connecting terminal J is used for accessing/outputting a synchronous signal Syn;

and one end of the resistor R is connected with the synchronous signal Syn, and the other end of the resistor R is connected with the ground, and the resistor R is used for ensuring the certainty of the level of the synchronous signal Syn.

In the above-described synchronization signal generation circuit based on time competition, the generation method of the synchronization signal circuit based on time competition is performed by the following steps:

initializing a program for initializing PWM module output and interrupt setting, Syn loss timer setting, rising edge interrupt setting and I/O output setting;

second, the PWM overflow interrupt processing program realizes the power-on delay and the CTL of the I/O output signal_TriControl of (2);

rising edge interrupt processing program to realize the identification of the rising edge of the Syn signal and the zero clearing control of the Syn loss timer;

and (4) the yn loss timer overflows an interrupt processing program to realize the resetting of related parameters so as to restart the competition of the Syn.

Compared with the prior art, the method has the following advantages:

according to the invention, a non-master-slave dynamic synchronization scheme based on time competition is adopted, and compared with a static master-slave synchronization scheme, even if a circuit for providing a synchronization signal Syn is pulled out or a signal is lost due to failure, a new synchronization signal can be regenerated from the rest PWM signals through time competition within set time, so that the reliability is higher;

because the PWM overflow interruption signal occurrence time of each circuit is different, the PWM signal which is correspondingly output by the circuit with the earliest PWM overflow interruption signal occurrence is selected as Syn based on the difference, and therefore, the synchronous signal Syn is unique.

The invention supports the circuit to carry out hot plug, can effectively inhibit Syn signals from being lost in short time due to poor contact, element failure or interference and the like, and has strong anti-interference capability and stable reliability.

Compared with a synchronization scheme via a communication bus, the invention has the following advantages: firstly, the invention does not need data exchange; secondly, the frequency of the synchronization signal is completely determined by the frequency of the PWM signal, and the bandwidth of the synchronization signal frequency is large. The communication bus synchronization scheme is limited by communication baud rate and various checks, so that the bandwidth of the synchronization signal frequency is limited; again, the respective circuits can almost simultaneously acquire the synchronization signal Syn. Since the synchronization signal Syn appears at the connection terminals J of the respective circuits at the same time, all the modules can receive the synchronization signal Syn at the same time, and there is theoretically no time difference. However, in the communication bus synchronization scheme, from the sending of the synchronization signal to the receiving of the synchronization signal, due to the processes of data transmission, receiving, verification, program processing and the like, a certain difference exists in the time for each module to acquire the synchronization signal; then, the synchronization signal generation circuit and the method provided by the invention do not need a communication protocol, do not influence the operation of the internal software of the module, and can synchronize the modules of different models and different manufacturers, thereby having wide compatibility; finally, the electronic elements required by the synchronization signal generation circuit and method provided by the invention are common elements and modules, and the synchronization signal generation circuit and method have the advantages of convenience in implementation, low cost, high cost performance, stability, reliability and the like.

Drawings

FIG. 1 is a diagram of the production circuit of the present invention;

FIG. 2 is a schematic diagram of the production circuit of the present invention;

FIG. 3 is a schematic diagram of a system connection incorporating a synchronization signal generation circuit;

FIG. 4a is an initialization flow diagram;

FIG. 4b is a flowchart of a PWM overflow interrupt handler;

FIG. 4c is a flow diagram of a rising edge interrupt handler;

FIG. 4d is a flowchart of the Syn lost timer overflow interrupt handler.

Detailed Description

The invention is further illustrated by the following figures and examples, which are not to be construed as limiting the invention.

Examples are given. A synchronization signal generation circuit based on time competition is configured as shown in FIG. 1, and comprises: the circuit comprises a control chip 1, a tri-state gate G1, a connecting terminal J and a resistor R;

the control chip has rising edge interrupt input for capturing the rising edge of Syn signal, PWM output port for outputting PWM signal, and I/O output port for outputting signal CTL_TriThe three-state gate G1 is used for controlling the on-off of the three-state gate;

a tri-state gate G1, the input terminal of which is connected with the PWM output port of the control chip 1, and the control terminal of which is connected with the output signal CTL of the control chip 1_TriA connection, the output of which is connected to the synchronization signal Syn;

the connecting terminal J is used for accessing/outputting a synchronous signal Syn;

and one end of the resistor R is connected with the synchronous signal Syn, and the other end of the resistor R is connected with the ground, and the resistor R is used for ensuring the certainty of the level of the synchronous signal Syn.

Fig. 2 is a schematic diagram of a synchronization signal generation, which mainly includes a power-on delay, a PWM module, a tri-state gate, a PWM output control module, a synchronization signal Syn loss timing/counting module, and a connection terminal. Wherein, the power-on time delay realizing circuit delays T after power-on_d，T_dIt must satisfy: t is_d>T_s. Wherein, T_sIs the period of the PWM signal. To facilitate the implementation of the procedure, let T_d＝KT_s(K is a positive integer greater than 1). The PWM module outputs a PWM signal and an overflow signal OV, the PWM signal is connected to the input of the three-state gate, and the overflow signal OV is input to the PWM output control module. The three-state gate receives an output signal CTL of the PWM output control module, controls the connection or disconnection of the PWM signal and the terminal, and plays a role of a bus control switch. Syn loss timing/counting moduleAnd judging whether the Syn continuous loss time (or the number) reaches a set trigger value or not. And if the preset trigger value is reached, outputting a Reset signal to the PWM output control module. The PWM output control module receives the output OV of the PWM module, the Reset of the Syn lost timing/counting module and the synchronous signal Syn, obtains an output control signal CTL based on a time competition relationship, realizes on-off control of the tri-state gate, and further determines the synchronous signal Syn.

Fig. 3 is a schematic diagram of a system connection integrated with a synchronization signal generation circuit based on time competition according to the present invention, which connects the terminals of the synchronization signal generation circuits of all modules together through a wire, where the signal on the wire is a synchronization signal Syn.

Fig. 4 is a flowchart of a method for generating a synchronization signal based on the circuit of fig. 1 and the principle of fig. 2, which includes the following steps:

the method comprises the steps of initializing PWM module output and interrupt setting, Syn loss timer setting, rising edge interrupt setting, I/O output setting and the like;

the PWM overflows an interrupt processing program to realize power-on delay and I/O output signal CTL_TriControl of (2);

interrupting the program by the rising edge to realize the identification of the rising edge of the Syn signal and the zero clearing control of the Syn loss timer;

and fourthly, the Syn loss timer overflows an interrupt handler to reset relevant parameters so as to restart the competition of the Syn.

In conclusion, the synchronization signal generation circuit based on time competition provided by the invention not only has strong anti-interference capability and reliability and supports the system to carry out hot plug, but also can realize the generation of system synchronization signals by only needing few common elements and wire connection, and has the characteristics of simple structure, low cost, high speed, strong anti-interference capability, high reliability, good practicability and the like.