阅读说明：本技术 压敏电阻 (Voltage dependent resistor ) 是由 刘旭 陈锦邦 姚斌 王清华 于 2020-10-16 设计创作，主要内容包括：本申请公开一种压敏电阻,所述压敏电阻包括压敏电阻本体、端电极、侧电极和内电极；所述压敏电阻本体包括压敏电阻层,所述压敏电阻层开设有两个孔槽,所述两个孔槽内分别安装有左内电极和右内电极,所述左内电极的部分或者全部落入所述右内电极的正投影涵盖范围之内而与所述右内电极形成电容结构；所述左侧电极的一端与所述左内电极电连接,另一端则与所述左端电极电连接；所述右侧电极的一端与所述右内电极连接,另一端则与所述右端电极电连接。本发明提供的压敏电阻,利用两槽的内电极形成平行板电容结构,利用两槽间距形成压敏电性,提供一种新型压敏电阻结构。(The application discloses a piezoresistor, which comprises a piezoresistor body, a terminal electrode, a side electrode and an inner electrode; the piezoresistor body comprises a piezoresistor layer, the piezoresistor layer is provided with two hole grooves, a left inner electrode and a right inner electrode are respectively arranged in the two hole grooves, and part or all of the left inner electrode falls into the orthographic projection coverage range of the right inner electrode to form a capacitor structure with the right inner electrode; one end of the left side electrode is electrically connected with the left inner electrode, and the other end of the left side electrode is electrically connected with the left end electrode; one end of the right side electrode is connected with the right inner electrode, and the other end of the right side electrode is electrically connected with the right end electrode. The piezoresistor provided by the invention has the advantages that the inner electrodes of the two grooves form a parallel plate capacitor structure, and the distance between the two grooves forms the piezoresistance property, so that a novel piezoresistor structure is provided.)

1. The piezoresistor is characterized by comprising a piezoresistor body, a terminal electrode, a side electrode and an inner electrode; the piezoresistor body comprises a piezoresistor layer, the end electrodes comprise a left end electrode and a right end electrode, the side electrodes comprise a left side electrode and a right side electrode, and the inner electrodes comprise a left inner electrode and a right inner electrode; the left end electrode and the right end electrode are respectively arranged at two ends of the piezoresistor body; the voltage-sensitive resistance layer is provided with two hole grooves, a left inner electrode and a right inner electrode are respectively arranged in the two hole grooves, and part or all of the left inner electrode falls into the orthographic projection coverage range of the right inner electrode to form a capacitor structure with the right inner electrode; one end of the left side electrode is electrically connected with the left inner electrode, and the other end of the left side electrode is electrically connected with the left end electrode; one end of the right side electrode is connected with the right inner electrode, and the other end of the right side electrode is electrically connected with the right end electrode.

2. The varistor of claim 1, wherein said left inner electrode and said right inner electrode are parallel to each other.

3. The varistor of claim 2, wherein said left inner electrode and said right inner electrode are the same size.

4. The varistor of claim 3, wherein said left and right internal electrodes are formed in said via by slurry filling.

5. The varistor according to claim 2, wherein said hole grooves are opened in a side surface of said varistor layer.

6. The varistor of claim 2, wherein said perforations open into said varistor layer.

7. The varistor according to claim 5 or 6, wherein said left electrode is integrally formed with said left electrode, and/or said right electrode is integrally formed with said right electrode.

8. A varistor according to claim 5 or 6, wherein said left side electrode is integrally formed with said left inner electrode, and/or said right side electrode is integrally formed with said right inner electrode.

9. The varistor of claim 1, wherein said varistor body comprises a plurality of varistor layers, said plurality of varistor layers being arranged in a stack.

10. The varistor of claim 9, further comprising an upper substrate and a lower substrate, wherein said varistor body is disposed intermediate said upper and lower substrates.

Technical Field

The application relates to the field of electronic components, in particular to a piezoresistor.

Background

In the existing piezoresistor, a structure that a plurality of layers of electrodes are connected in parallel or in series is generally adopted in the piezoresistor, but due to the influence of a manufacturing process, the thickness between electrode layers is extremely poor and the alignment accuracy between the electrodes is insufficient, so that certain deviation exists between the electrodes and the area between parallel capacitor plates, the influence on the electrical uniformity of the piezoresistor is very large, and the protection precision of a product in an actual circuit is directly influenced by the dispersion of electrical property; for the small-capacitance piezoresistor, when a multilayer series electrode structure is adopted, the piezovoltage can be very high, but the electrical consistency is very dispersed, so that the piezoresistor is not suitable for a low-voltage circuit environment, and the protection precision of the piezoresistor in a high-voltage circuit environment is not enough.

Content of application

Based on this, this application provides a piezo-resistor to solve present piezo-resistor protection precision low, the not wide problem of range of application. The application content is as follows:

a piezoresistor comprises a piezoresistor body, a terminal electrode, a side electrode and an inner electrode; the piezoresistor body comprises a piezoresistor layer, the end electrodes comprise a left end electrode and a right end electrode, the side electrodes comprise a left side electrode and a right side electrode, and the inner electrodes comprise a left inner electrode and a right inner electrode; the left end electrode and the right end electrode are respectively arranged at two ends of the piezoresistor body; the voltage-sensitive resistance layer is provided with two hole grooves, a left inner electrode and a right inner electrode are respectively arranged in the two hole grooves, and part or all of the left inner electrode falls into the orthographic projection coverage range of the right inner electrode to form a capacitor structure with the right inner electrode; one end of the left side electrode is electrically connected with the left inner electrode, and the other end of the left side electrode is electrically connected with the left end electrode; one end of the right side electrode is connected with the right inner electrode, and the other end of the right side electrode is electrically connected with the right end electrode.

In some embodiments, the left inner electrode and the right inner electrode are parallel to each other.

In some embodiments, the left inner electrode and the right inner electrode are the same size.

In some embodiments, the hole groove is opened on a side surface of the varistor layer.

In some embodiments, the hole groove is opened in the inner portion of the varistor layer.

In some embodiments, the left electrode is integrally formed with the left electrode, and/or the right electrode is integrally formed with the right electrode.

In some embodiments, the left electrode is integrally formed with the left inner electrode, and/or the right electrode is integrally formed with the right inner electrode.

In some embodiments, the varistor body includes a plurality of varistor layers disposed in a stack.

In some embodiments, the varistor further comprises an upper substrate and a lower substrate, and the varistor body is disposed intermediate the upper and lower substrates.

The piezo-resistor of this embodiment, the inner electrode that utilizes two hole grooves forms the parallel plate capacitance structure, utilize two groove intervals to form the piezo-electric property, can avoid the electrode that traditional manufacturing process caused to counterpoint the accuracy problem, thereby improve piezo-resistor's electric property uniformity, make piezo-resistor possess higher protection precision on the one hand, on the other hand, in little electric capacity piezo-resistor, because this structure electric property uniformity is good, consequently possible lower piezo-voltage, make this piezo-resistor applicable in lower operating voltage's circuit environment.

Drawings

Fig. 1 is a schematic perspective view of a varistor according to an embodiment of the present disclosure;

fig. 2 is a schematic perspective view of a varistor body of a varistor according to an embodiment of the present disclosure;

fig. 3 is a top view of a varistor structure according to an embodiment of the present application;

fig. 4 is a top view of a varistor structure according to another embodiment of the present application;

fig. 5 is a schematic perspective view of a varistor body of a varistor according to another embodiment of the present application;

fig. 6 is a schematic perspective view of a varistor according to another embodiment of the present application;

fig. 7 is a cross-sectional view taken along a-a of a varistor according to another embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. The following embodiments and their technical features may be combined with each other without conflict. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The application provides a piezoresistor, which can be a chip piezoresistor and other forms, and is not limited specifically. Referring to fig. 1, which is a schematic structural diagram of the varistor in an embodiment of the present application, in this embodiment, the varistor 100 includes a varistor body 110, terminal electrodes, side electrodes, and inner electrodes, where the varistor body 110 includes a varistor layer 111, the terminal electrodes include a left terminal electrode 121 and a right terminal electrode 122, the side electrodes include a left electrode 131 and a right electrode 132, and the inner electrodes include a left inner electrode 141 and a right inner electrode 142; the left end electrode 121 and the right end electrode 122 are respectively disposed at two ends of the varistor body 110. Referring to fig. 2, the varistor layer 111 has two slots 151 and 152, a left inner electrode 141 and a right inner electrode 142 are respectively installed in the two slots, and a part or all of the left inner electrode 141 falls within the range covered by the orthographic projection of the right inner electrode 142, so that the left inner electrode 141 and the right inner electrode 142 can form a capacitor structure, and when the left inner electrode 141 and the right inner electrode 142 are parallel, the capacitor structure is a parallel plate capacitor, of course, in other cases, the capacitor structure can be other structure capacitors, and in addition, the left inner electrode 141 and the right inner electrode 142 can have the same size to ensure better electrical characteristics, and the left inner electrode and the right inner electrode can be formed in the slots by filling paste.

In this embodiment, referring to fig. 3, the slots 151 and 152 on the piezoresistive layer 111 may be opened on the surface of the piezoresistive layer 111, and the opening manner may be one or more of mechanical opening, laser opening, photolithography, and etching, which is not limited herein. As an alternative size of the hole and the groove, the size of the two grooves can be consistent, the depth of the groove can be less than or equal to the thickness of the piezoresistor layer, the width of the groove can be between 1 and 20 μm, the length of the groove can be between 50 and 500 μm, and the distance between the grooves can be between 10 and 800 μm. In addition, in this embodiment, two slots are oppositely disposed, and a left internal electrode 141 and a right internal electrode 142 are respectively disposed in the slots, and the two internal electrodes may form a parallel-plate capacitor structure. As an alternative embodiment, the two internal electrodes may be formed by filling the electrode paste. Referring to fig. 4, the left electrode 131 and the right electrode 132 are mounted on the surface of the varistor layer 111, and the left and right electrodes may be formed by one or more of screen printing, steel plate printing, photolithography, and etching. One end of the left electrode 131 is electrically connected to the left inner electrode 141, and the other end is electrically connected to the left end electrode 121, so that the left end electrode 121 is electrically connected to the left inner electrode 141; one end of the right electrode 132 is connected to the right internal electrode 142, and the other end is electrically connected to the right electrode 122, so that the right electrode 122 is electrically connected to the right internal electrode 142. Further, the widths of the left and right electrodes and the electrodes in the cell may be the same, and the left electrode 132 does not exceed the right boundary of the left hole groove 151 and the right electrode 131 does not exceed the left boundary of the right hole groove 152.

In another embodiment of the present application, in addition to the structure described in the above embodiment, the structure of the varistor may also refer to fig. 5 and fig. 6, wherein the slots 151 and 152 on the varistor layer 111 may be opened inside the varistor layer 111, and the opening manner may be one or more of mechanical opening, laser opening, photolithography, and etching. In addition, in this solution, two slots are oppositely arranged, a left internal electrode 141 and a right internal electrode 142 are respectively installed in the slots, and the two internal electrodes may form a capacitor structure. Referring to fig. 7, the left electrode 131 and the right electrode 132 may be installed inside the varistor layer 111, one end of the left electrode 131 is electrically connected to the left inner electrode 141, and the other end is electrically connected to the left end electrode 121, so that the left end electrode 121 is electrically connected to the left inner electrode 141; one end of the right electrode 132 is connected to the right internal electrode 142, and the other end is electrically connected to the right electrode 122, so that the right electrode 122 is electrically connected to the right internal electrode 142.

In this embodiment, referring to fig. 7, two hole grooves may be respectively disposed in parallel with the left and right end electrodes 121 and 122, and the two hole grooves or two inner electrodes (left and right inner electrodes) may be disposed in parallel with each other, and the hole grooves or two inner electrodes (left and right inner electrodes) may have the same size. The left electrode 121 may be integrally formed with the left electrode 131, and similarly, the right electrode 122 may be integrally formed with the right electrode 132. In addition, the left electrode 131 is integrally formed with the left internal electrode 141, and the right electrode 132 may be integrally formed with the right internal electrode 142.

In this embodiment, the varistor body 110 may further include a plurality of varistor layers, and the plurality of varistor layers are stacked to form the varistor body, wherein each varistor layer may adopt the hole and groove arrangement scheme shown in fig. 2 or fig. 5, that is, the varistor layer in one varistor may adopt a surface hole and groove or an internal hole and groove, and form the varistor body 110 formed by varistor layers with different hole structures. In addition, referring to fig. 7, the varistor 100 may further include an upper substrate 161 and a lower substrate 162, and the varistor body 110 may be disposed as an intermediate electrode layer substrate between the upper substrate 161 and the lower substrate 162. The upper substrate 161 and the lower substrate 162 may be used to insulate the varistor from the outside, or to protect the varistor body, etc.

In the embodiment, more implementation possibilities are provided by providing a technical scheme for installing the inner electrode and the side electrode in the inner opening groove of the piezoresistor and providing a piezoresistor structure consisting of a plurality of piezoresistor layers. In addition, the piezoresistor has better performance by perfecting the upper substrate and the lower substrate of the piezoresistor.

To better illustrate the beneficial effects of the present application, the inventors conducted the following experiments, respectively:

experiment one:

the piezoresistor in the above embodiment of the present application is used as the invention product 1, the external dimension of the invention product 1 is (1.0 ± 0.15) × (0.5 ± 0.15) mm, the reference range of the voltage-dependent voltage VB is 22-28V, and the reference range of the capacitance Cp is 2.5-7.5 pF. In addition, a piezoresistor with a series or parallel structure in the prior art is adopted as a comparison product 1, and the comparison product 1 has the same size as the invention product 1, and has the same reference range of the voltage-sensitive voltage VB and the capacitance Cp. In addition, the product 1 is made of the same piezoresistor material as the comparative product 1, the material parameters are the same, the intersection area of two electrodes in the two piezoresistors is the same as the distance between the upper electrode and the lower electrode, and the design range of the voltage-dependent voltage VB and the design range of the capacitor Cp of the product 1 is consistent with that of the comparative product 1.

The inventive product 1 and the comparative product 1 were tested separately, and the test results showed that: the actual measurement range of the voltage-sensitive voltage VB of the product 1 is 24-24.6V, and the actual measurement range of the capacitor Cp is 4.89-5.25 pF; the actual measurement range of the voltage-sensitive voltage VB of the comparative product 1 is 22.7-27.2V, and the actual measurement range of the capacitance Cp is 3.28-6.63 pF. The above experimental results show that, within the same electrical design reference range, the electrical precision of the product 1 of the invention is superior to that of the comparative product 1, so that the piezoresistor has higher protection precision in the products within the same reference range.

Experiment two:

the piezoresistor in the embodiment of the present application is used as the invented product 2, the external dimension of the invented product 2 is (1.0 ± 0.15) × (0.5 ± 0.15) mm, and the reference range of the capacitance Cp is 0.25-1 pF. In addition, the traditional series structure small-capacitance piezoresistor is adopted as a comparison product 2, the size of the comparison product 2 is the same as that of the product 2 of the invention, and the reference range of the capacitance Cp is the same, and in addition, the comparison product and the product are made of the same piezoresistor material, so that the material parameters are ensured to be consistent; the voltage-sensitive voltages VB of the two are between 100 and 160V.

The distribution of the voltage-sensitive voltage VB and the capacitance Cp of the piezoresistor in the inventive product 2 and the comparative product 2 was tested, and the test results show that: the actual measurement range of the voltage-sensitive voltage VB of the product 2 is 11.85-12.69V, the actual measurement range of the capacitor Cp is 0.47-0.66pF, the actual measurement range of the voltage-sensitive voltage VB of the comparative product 2 is 105.1-158.6V, and the actual measurement range of the capacitor Cp is 0.23-1.35 pF.

The experimental results show that compared with the small-capacitance piezoresistor designed by the traditional series structure, the piezoresistor provided by the invention adopts the same material, the piezoresistor has lower voltage, so that the small-capacitance product can be applied to a circuit working environment with lower voltage, and meanwhile, the precision of the piezoresistor VB and the precision of the capacitor Cp can be higher, so that the piezoresistor has higher protection precision in products with the same reference range.

In conclusion, the piezoresistor of the embodiment utilizes the inner electrodes of the two grooves to form the parallel plate capacitor structure, and utilizes the distance between the two grooves to form the piezoresistor property, so that the problem of electrode alignment accuracy caused by the traditional manufacturing process can be avoided, the electrical consistency of the piezoresistor is improved, on one hand, the piezoresistor has higher protection precision, and on the other hand, in the small-capacitor piezoresistor, because the electrical consistency of the structure is good, the lower piezovoltage can be realized, and the piezoresistor can be applicable to the circuit environment with lower working voltage.

Although the application has been shown and described with respect to one or more implementations, alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. This application is intended to embrace all such modifications and variations and is limited only by the scope of the appended claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification. In addition, while a particular feature of the specification may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for a given or particular application. Furthermore, to the extent that the terms "includes," has, "" contains, "or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term" comprising. Further, it is understood that reference to "a plurality" herein means two or more. For the steps mentioned in the text, the numerical suffixes are only used for clearly expressing the embodiments and are convenient for understanding, the execution sequence of the steps is not completely represented, and the logical relationship should be set as the consideration

The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.