阅读说明：本技术 形成封装结构的方法 (Method for forming packaging structure ) 是由 陈志豪 潘志坚 郑礼辉 高金福 卢思维 于 2020-08-21 设计创作，主要内容包括：提供了一种形成封装结构的方法。形成封装结构的方法包括经由多个第一连接器将封装构件接合到基板的第一表面。封装构件包括中介层、在中介层上方的第一半导体晶粒以及第二半导体晶粒。形成封装结构的方法还包括在基板的第一表面上方形成阻挡结构。阻挡结构在封装构件周围并且与封装构件分离。形成封装结构的方法还包括在阻挡结构与封装构件之间形成底部填充层,以及在形成底部填充层之后去除阻挡结构。(A method of forming a package structure is provided. A method of forming a package structure includes bonding a package member to a first surface of a substrate via a plurality of first connectors. The package assembly includes an interposer, a first semiconductor die over the interposer, and a second semiconductor die. The method of forming the encapsulation structure further includes forming a barrier structure over the first surface of the substrate. The blocking structure is around and separated from the encapsulation member. The method of forming the encapsulation structure further includes forming an underfill layer between the barrier structure and the encapsulation member, and removing the barrier structure after forming the underfill layer.)

1. A method of forming an encapsulation structure, comprising:

bonding a packaging component to a first surface of a substrate via a plurality of first connectors, wherein the packaging component includes an interposer, a first semiconductor die and a second semiconductor die located over the interposer;

forming a barrier structure over the first surface of the substrate, wherein the barrier structure is located around and separated from the encapsulation member;

forming an underfill layer between the barrier structure and the package member; and

the barrier structure is removed after the underfill layer is formed.

Technical Field

Embodiments of the present disclosure relate to a method of forming a package structure, and more particularly, to a package structure.

Background

Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer over a semiconductor substrate, and patterning the various material layers using photolithography and etching processes to form circuit elements and devices on the semiconductor substrate.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. In some applications, these smaller electronic components also use smaller packages that utilize smaller areas or lower heights.

New packaging techniques have been developed to further improve the density and functionality of semiconductor dies. For example, three-dimensional integrated circuit (3D-IC) packages have been developed. These relatively new types of packaging techniques for semiconductor dies face manufacturing challenges and they are not entirely satisfactory in all respects.

Disclosure of Invention

According to some embodiments of the present disclosure, a method of forming a package structure is provided, including bonding a package member to a first surface of a substrate via a plurality of first connectors, wherein the package member includes an interposer, a first semiconductor die and a second semiconductor die positioned over the interposer, forming a barrier structure positioned over the first surface of the substrate, wherein the barrier structure is positioned around and separated from the package member, forming an underfill layer between the barrier structure and the package member, and removing the barrier structure after forming the underfill layer.

According to some embodiments of the present disclosure, a method of forming a package structure is provided that includes bonding a package component to a substrate via a plurality of connectors, wherein the package component includes an interposer, a plurality of semiconductor dies, and a molding compound layer. A plurality of semiconductor dies is located over the interposer. The molding compound layer is over the interposer and laterally surrounds the semiconductor die. Forming a barrier structure over the substrate, wherein each corner of the encapsulation member is surrounded by the barrier structure, forming an underfill layer surrounding the connector and in direct contact with the barrier structure, and removing the barrier structure after forming the underfill layer.

According to some embodiments of the present disclosure, a package structure is provided, including a package member bonded to a first surface of a substrate via a plurality of first connectors, and an underfill layer, wherein the package member includes an interposer, a first semiconductor die and a second semiconductor die positioned over the interposer. The underfill layer laterally surrounds the first connector, wherein the extension portion of the underfill layer laterally protrudes from an edge of the encapsulation member, and a ratio of a maximum height of the extension portion to a first width of a bottommost surface of the extension portion is greater than or equal to about 0.8.

Drawings

Aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features are not necessarily drawn to scale. In fact, the dimensions of the various features and geometries may be arbitrarily expanded or reduced for clarity.

Fig. 1A-1F are cross-sectional views of various stages of a process of forming a package structure, according to some embodiments of the present disclosure.

Fig. 2 is a cross-sectional view of a package structure according to some embodiments of the present disclosure.

Fig. 3A-3C are cross-sectional views of various stages of a process of forming a package structure, according to some embodiments of the present disclosure.

Fig. 4 is a cross-sectional view of a package structure according to some embodiments of the present disclosure.

Fig. 5A-5C are cross-sectional views of various stages of a process of forming a package structure, according to some embodiments of the present disclosure.

Fig. 6 is a cross-sectional view of a package structure according to some embodiments of the present disclosure.

Fig. 7 is a cross-sectional view of a stage in the process of forming a package structure according to some embodiments of the present disclosure.

Fig. 8 is a cross-sectional view of a stage in the process of forming a package structure according to some embodiments of the present disclosure.

Fig. 9 is a cross-sectional view of a stage in the process of forming a package structure according to some embodiments of the present disclosure.

Fig. 10A-10D are top views of various stages of a process of forming a package structure according to some embodiments of the present disclosure.

Fig. 11A-11B are top views of various stages of a process of forming a package structure according to some embodiments of the present disclosure.

Description of reference numerals:

100a,100b,200a,200b,300a,300 b: packaging structure

101: interposer wafer

101': interposer

103,109,125: connector with a locking member

105 a: first semiconductor die

105 b: a second semiconductor die

107: layer of moulding compound

110: packaging member

110E: edge of a container

111: substrate

111 a: first surface

111 b: second surface

112: device for measuring the position of a moving object

114a,114b,114 c: polymer material

115,115a,115b,115b ', 115c,115d,115f, 115': barrier structure

115a1,115b1,115c 1: lower part

115a2,115b2,115c 2: middle part

115a3,115b3,115c 3: upper part

117: underfill layer

117a,117b,117c,117d,117e,117f,117 EP: extension part

117a1,117c 1: lower part

117a2,117c 2: middle part

117a3,117c 3: upper part

119: adhesive layer

121: heat dissipating paste

123a,123 b: cover cap

130: passive component

H,H_1a,H_1b,H_1c,H_1d,H_1e,H_1f,H₂,H₃: maximum height

W,W_1a,W_1b,W_1c,W_1e,W_1f,W_2a,W_2b,W_2c,W_3a,W_3b,W_3c: width of

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, if the specification states a first feature formed over a second feature, that is, embodiments that may include the first feature in direct contact with the second feature, there may be additional features formed between the first and second features, such that the first and second features may not be in direct contact. In addition, in various examples, the present disclosure may use repeated reference characters and/or letters. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially related terms such as: the use of words of "below," "lower," "above," "upper," and the like in … … is used herein to facilitate describing the relationship of one element or feature to another element(s) or feature(s) in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be turned to a different orientation (rotated 90 degrees or at other orientations) and the spatially relative terms used herein should be interpreted accordingly.

Some embodiments of the disclosure are described. Additional operations may be provided before, during, and/or after the stages described in these embodiments. Certain stages described may be replaced or eliminated with respect to different embodiments. Additional features may be added to the semiconductor device structure. Certain functions described below may be replaced or eliminated with respect to different embodiments. Although some embodiments of operations performed in a particular order are discussed, the operations may be performed in another logical order.

Embodiments of the present disclosure may relate to three-dimensional packages or three-dimensional integrated circuit devices. Other features and processes may also be included. For example, test structures may be included to facilitate verification testing of three-dimensional packages or three-dimensional integrated circuit devices. The test structures may include, for example, test pads formed in a redistribution layer (redistribution layer) or on a substrate, which allow testing of a three-dimensional package or three-dimensional integrated circuit, or use of probes and/or probe cards, etc. Verification tests may be performed on the intermediate structure as well as the final structure. In addition, the structures and methods disclosed herein may be used with test methods that incorporate intermediate verification of known good dice to increase yield and reduce cost.

Embodiments of forming a package structure are provided. A method of forming an encapsulation structure may include bonding an encapsulation member to a substrate, forming a barrier structure over the substrate, forming an underfill layer between the barrier structure and the encapsulation member, and removing the barrier structure after forming the underfill layer. By forming an underfill layer between the barrier structure and the encapsulation member, the size and profile of the underfill layer may be controlled. Thus, delamination (delamination) problems, such as cracks in the underfill layer that grow along the interface between the encapsulation member and the underfill layer, may be reduced or eliminated.

Fig. 1A-1F are cross-sectional views of various stages of a process of forming a package structure 100a, according to some embodiments of the present disclosure.

As shown in fig. 1A, according to some embodiments, a singulation process is performed on an interposer wafer 101 having a first semiconductor die 105a, a second semiconductor die 105b, and a plurality of connectors 109. More specifically, in some embodiments, the first semiconductor die 105a and the second semiconductor die 105b are bonded to a surface of the interposer wafer 101 via a plurality of connectors 103, and a plurality of connectors 109 are bonded to another surface of the interposer wafer 101, which is opposite to the surface to which the first semiconductor die 105a and the second semiconductor die 105b are bonded. Further, according to some embodiments, the first semiconductor die 105a, the second semiconductor die 105b, and the connector 103 are surrounded by a molding compound layer 107.

In some embodiments, interposer wafer 101 has a substrate (not shown) and vias (not shown) in the substrate. The substrate for interposer wafer 101 may be an active layer, such as a doped or undoped silicon substrate, or a silicon-on-insulator (SOI) substrate, for providing support for interposer wafer 101. However, the substrate for the interposer wafer 101 may also be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that may provide suitable protection and/or interconnect functionality.

Vias in the substrate of interposer wafer 101 may serve as conductive vias to provide electrical connections in the vertical direction. In some embodiments, the opening is created by applying and developing a photoresist over the substrate, and then etching the substrate. Thereafter, the opening for the via hole may be filled with a conductive layer to form the via hole.

The conductive layer of the via may be made of copper, cobalt, titanium, aluminum, tungsten, gold, platinum, nickel, one or more other suitable materials, or a combination thereof. The conductive layer may be formed by depositing a seed layer, then electroplating a conductive layer onto the seed layer, filling and overfilling (overfilling) the openings for the vias. Once the opening of the via hole has been filled, excess conductive layer outside the opening for the via hole may be removed via a planarization process.

In some embodiments, first semiconductor die 105a and second semiconductor die 105b are logic dies, system-on-chip (SoC) dies, memory dies, or other suitable dies. The memory die may include memory devices such as Static Random Access Memory (SRAM) devices, Dynamic Random Access Memory (DRAM) devices, other suitable devices, or combinations thereof. In some embodiments, first semiconductor die 105a is a memory die that functions as a High Bandwidth Memory (HBM) and second semiconductor die 105b is a system-on-chip die. In some embodiments, the first semiconductor die 105a and the second semiconductor die 105b are system-on-chip dies.

In some embodiments, the connectors 103 are solder bump (solder bumps), solder balls, other suitable connectors, or combinations thereof. In some embodiments, the connectors 103 are micro-bumps (micro-bumps), controlled collapse chip connection (C4) bumps, and/or Ball Grid Array (BGA) bumps.

Furthermore, according to some embodiments, the method of forming the molding compound layer 107 includes forming a molding compound material (not shown) covering the first and second semiconductor dies 105a, 105b and thinning the molding compound material by using a planarization process to form the molding compound layer 107 surrounding the first and second semiconductor dies 105a, 105 b. The molding compound material may be formed by an injection process, a spin-on process, a spray-on process, one or more other suitable processes, or a combination thereof.

The planarization process may include a polishing process, a Chemical Mechanical Polishing (CMP) process, a dry polishing process, an etching process, a cutting process, one or more other suitable processes, or a combination thereof. After the planarization process, the first semiconductor die 105a and the second semiconductor die 105b may be exposed to enhance the heat dissipation effect of the first semiconductor die 105a and the second semiconductor die 105 b.

According to some embodiments, after the planarization process used to form the molding compound layer 107, the interposer wafer 101, the connectors 103, the first semiconductor die 105a, the second semiconductor die 105b, and the molding compound layer 107 bonded together are flipped upside down to form the connectors 109 on the other surface of the interposer wafer 101. Some of the materials used to form the connector 109 may be similar or identical to those used to form the connector 103 previously described and will not be described in detail herein. In some embodiments, the size of the connector 109 is larger than the size of the connector 103.

According to some embodiments, as shown in fig. 1A, it should be noted that a singulation process is performed along the line I-I to cut the interposer wafer 101 and the molding compound layer 107 into a plurality of package members 110. According to some embodiments, after performing the singulation process, a plurality of package components 110 are formed and the interposer wafer 101 is diced into a plurality of interposers 101'.

In some embodiments, each package member 110 is a chip-on-wafer (CoW) package. Although two first semiconductor dies 105a and one second semiconductor die 105b are shown in each package member 110 in fig. 1A, the number of first semiconductor dies 105a and the number of second semiconductor dies 105b in each package member 110 are not limited thereto.

According to some embodiments, as shown in fig. 1B, after the package members 110 are formed, one of the package members 110 is bonded to the first surface 111a of the substrate 111 via the connector 109. In some embodiments, the substrate 111 is a Printed Circuit Board (PCB), a ceramic substrate, other suitable substrate, or other packaging structure.

Next, according to some embodiments, as shown in fig. 1C, a barrier structure 115a is formed over the first surface 111a of the substrate 111. More specifically, according to some embodiments, the blocking structure 115a is formed around the encapsulation member 110 and separated from the encapsulation member 110. In some embodiments, the barrier structure 115a is made of a polymer material 114a, such as an acrylic-based polymer (acryl-based polymer), a polyimide (polyimide), an epoxy (epoxy), other suitable materials, or combinations thereof. In some embodiments, polymeric material 114a is a three-dimensional cross-linked polymer (3D cross-linking polymer).

The polymer material 114a of the barrier structure 115a may have a different etch selectivity, e.g., a different etch rate, than the material of the molding compound layer 107 and the material of the subsequently formed underfill layer, so that in subsequent processes, the barrier structure 115a may be easily removed without damaging other elements in the final package structure 100 a. In some embodiments, the polymeric material 114a is made of a water-soluble polymer and can be easily dissolved in water without leaving any residue.

In some embodiments, the barrier structure 115a is formed by dispensing the polymer material 114a in liquid or gel form on the first surface 111a of the substrate 111 via a dispensing tool in the apparatus 112. More specifically, in some embodiments, the polymeric material 114a is dispensed in a designated area around the encapsulation member 110. Then, the polymer material 114a over the first surface 111a of the substrate 111 is cured to form the barrier structure 115 a.

In some embodiments, the polymeric material 114a is dispensed by an injection molding process, or other suitable dispensing process. In some embodiments, after the polymeric material 114a is dispensed over the first surface 111a of the substrate, the polymeric material 114a is cured via a curing tool in the apparatus 112 with an Ultraviolet (UV) curing process, a thermal curing process, or other curing process.

The barrier structure 115a may include a lower portion 115a1 adjacent the first surface 111a of the substrate 111, a middle portion 115a2 above the lower portion 115a1, and an upper portion 115a3 above the middle portion 115a 2. It should be noted that, according to some embodiments, the sidewalls of lower portion 115a1 of barrier structure 115a are curved, and the width of lower portion 115a1 gradually increases in a direction from the top of lower portion 115a1 to substrate 111.

In some embodiments, the widths of the intermediate portions 115a2 of the barrier structures 115a are substantially the same. Furthermore, according to some embodiments, the top surface and sidewalls of upper portion 115a3 of barrier structure 115a are curved, and the width of upper portion 115a3 gradually increases in a direction from the top of upper portion 115a3 to substrate 111.

In some embodiments, the width W of the middle portion 115a2 of the barrier structure 115a is in the range of about 50 μm to about 500 μm, and the maximum height H of the barrier structure is greater than about 20 μm. The profile of the blocking structure 115a may be adjusted via the moving speed of the control device 112 (e.g., dispensing speed and curing speed), and/or parameters of the curing process (e.g., the dose of the uv light in the uv curing process, or the temperature in the thermal curing process). Furthermore, the above-mentioned parameters for forming the profile of the blocking structure 115a can be easily controlled, and the associated cost can be reduced (e.g., the moving speed of the device 112 can be slow), and in the present embodiment, the blocking structure 115a can provide an improved process window (process window).

Thereafter, according to some embodiments, as shown in fig. 1D, the underfill layer 117 is filled in the space between the encapsulation member 110 and the first surface 111a of the substrate 111, and the underfill layer 117 extends to the space between the encapsulation member 110 and the barrier structure 115 a. In particular, according to some embodiments, the underfill layer 117 has an extension portion 117a that protrudes laterally from the edge 110E of the encapsulation member 110, and the extension portion 117a is sandwiched between the barrier structure 115a and the encapsulation member 110, and the extension portion 117a is in direct contact with the barrier structure 115a and the encapsulation member 110.

In some embodiments, the underfill layer 117 is made of liquid epoxy, deformable gel, silicone rubber, other suitable material, or combinations thereof. Further, the underfill layer 117 may be formed by performing a dispensing process using a dispensing tool, and then the material of the underfill layer 117 may be cured to harden the material of the underfill layer 117.

It should be noted that, according to some embodiments, the material of the underfill layer 117 is different from the material of the barrier structure 115a, such that the barrier structure 115a has a higher etch selectivity than the underfill layer 117. Accordingly, the barrier structure 115a may be substantially removed by the etching process, and the underfill layer 117 may be substantially left.

The extended portion 117a of the underfill layer 117 includes a lower portion 117a1 adjacent to the first surface 111a of the substrate 111, an intermediate portion 117a2 above the lower portion 117a1, and an upper portion 117a3 above the intermediate portion 117a 2. In some embodiments, lower portion 117a1 of extension portion 117a has curved sidewalls, and the width of lower portion 117a1 gradually decreases in a direction from the top of lower portion 117a1 to substrate 111.

Further, in some embodiments, the width of the intermediate portion 117a2 of the extension portion 117a is substantially the same. In some embodiments, the top surface of the upper portion 117a3 of the extension 117a is the topmost surface of the underfill layer 117, which is curved and sloped. According to some embodiments, as shown in fig. 1D, for example, the contact point between the underfill layer 117 and the encapsulation member 110 is higher than the contact point between the underfill layer 117 and the barrier structure 115 a. However, in some embodiments, the top surface of the upper portion 117a3 is flat.

In some embodiments, the lower portion 117a1 of the extension portion 117a has a width W_1aAnd is in direct contact with the first surface 111a of the substrate 111, and the intermediate portion 117a2 of the extension portion 117a has a width W_2aAnd a width W_2aIs greater than width W_1a. Furthermore, the extension portion 117a of the underfill layer 117 has a maximum height H above the first surface 111a of the substrate 111_1a. In some embodiments, the maximum height H_1aAnd width W_1aRatio (H)_1a/W_1a) Greater than or equal to about 0.8.

When the maximum height H of the extension 117a_1aAnd width W_1aRatio (H)_1a/W_1a) Too small (e.g., less than 0.8), high stresses (e.g., bending forces) applied from the substrate 111 to the underfill layer 117 may cause delamination problems in the underfill layer 117. For example, cracks may grow in the extension portion 117a along the interface between the encapsulation member 110 and the underfill layer 117. In some embodiments, due to the maximum of the extension 117aHeight H_1aAnd width W_1aRatio (H)_1a/W_1a) Greater than or equal to 0.8, the delamination problem can be reduced or eliminated. As a result, the quality of the package structure 100a can be improved.

According to some embodiments, as shown in fig. 1E, after the underfill layer 117 is formed, the barrier structure 115a is removed through an etching process. The etching process may include a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the etching process is a wet etching process using water as an etchant, and the barrier structure 115a is dissolved by the water. In some embodiments, the etching process is a wet etching process using potassium hydroxide (KOH) as an etchant. It should be noted that, since the etch selectivity of the barrier structure 115a with respect to the underfill layer 117 and the encapsulation member 110 is high, the barrier structure 115a may be easily removed without leaving any residue.

According to some embodiments, as shown in fig. 1F, after removing the blocking structure 115a, the cap 123a is attached to the first surface 111a of the substrate 111 via the adhesion layer 119 and a heat dissipation paste (heat dissipation paste) 121. Next, layer 119 may be used to fix cover cap 123a, cover cap 123a may be used to protect package member 110, and thermal paste 121 may be used to enhance the thermal dissipation effect of first semiconductor die 105a and second semiconductor die 105 b.

The next layer 119 may be glue or tape. In some embodiments, the thermal grease 121 is made of a viscous silicone compound (silicone compound) having mechanical properties similar to grease or colloid. In some embodiments, the thermal grease 121 is made of silicone grease (silicone grease) in which silver, nickel, or aluminum particles are suspended. Further, the cap 123a is made of copper, aluminum, other metals, alloys, ceramic materials, or combinations thereof.

In some embodiments, the encapsulating member 110 is covered by a cover 123 a. According to some embodiments, as shown in fig. 1F, after attaching the cover cap 123a to the first surface 111a of the substrate 111, the encapsulation structure 110, and the cover cap 123a, which are bonded together, are turned upside down to form the connector 125 over the second surface 111b of the substrate 111. The second surface 111b is opposite to the first surface 111 a.

Some of the materials used to form the connectors 125 may be similar or identical to the materials used to form the connectors 109 previously described and will not be described in detail herein. In some embodiments, the size of the connector 125 is greater than the size of the connector 109. After the connectors 125 are formed, the package structure 100a is obtained.

In the method of forming the package structure 100a, the profile and the size (i.e., the ratio (H) of the extension portion 117a of the underfill layer 117 are controlled by the barrier structure 115a_1a/W_1a)). Thus, the delamination problem of the underfill layer 117 may be reduced or eliminated. Furthermore, the barrier structure 115a allows for a reduction in the width (e.g., width W) of the extension portion 117a of the underfill layer 117 by allowing for a reduction in the width of the barrier structure 115a_1a) Allowing the substrate 111 to be reduced in size and the barrier structure 115a to be removed after the underfill layer 117 is formed, the package structure 100a may be reduced in size.

Fig. 2 is a cross-sectional view of a package structure 100b according to some embodiments of the present disclosure. Some materials and processes for forming the package structure 100b shown in fig. 2 may be similar or identical to those for forming the package structure 100a shown in fig. 1A to 1F, and are not described herein again.

According to some embodiments, as shown in fig. 2, the package structure 100a of fig. 1F differs from the package structure 100b of fig. 2 in that, unlike the cap 123a of the package structure 100a and the cap 123b of the package structure 100b, the cap 123b is attached to the first surface 111a of the substrate 111, and the thermal paste 121 is not formed over the encapsulation member 110. In some embodiments, the encapsulation member 110 is surrounded by the cover 123b, and the top surface of the encapsulation member 110 is not covered by the cover 123 b.

Fig. 3A-3C are cross-sectional views of various stages of a process of forming a package structure 200a, according to some embodiments of the present disclosure.

According to some embodiments, as shown in fig. 3A, similar to the process of fig. 1C, a barrier structure 115b is formed over the first surface 111a of the substrate 111 by dispensing and curing a polymer material 114b via the apparatus 112. In some embodiments, the polymeric material 114b is an acrylic-based polymer, polyimide, epoxy, other suitable material, or a combination thereof. In some embodiments, the polymeric material 114b is a two-dimensional cross-linked polymer.

The polymer material 114b of the barrier structure 115b may have a different etch selectivity, e.g., a different etch rate, than the material of the molding compound layer 107 and the material of the subsequently formed underfill layer, so that in subsequent processes, the barrier structure 115b may be easily removed without damaging other elements in the final package structure 200 a. In some embodiments, the polymeric material 114b is made of a water-soluble polymer and can be easily dissolved in water without leaving any residue.

Some processes for forming the barrier structure 115b shown in fig. 3A may be similar or identical to the processes for forming the barrier structure 115a shown in fig. 1C, and are not repeated herein. The barrier structure 115b may include a lower portion 115b1 adjacent to the first surface 111a of the substrate 111, a middle portion 115b2 above the lower portion 115b1, and an upper portion 115b3 above the middle portion 115b 2. It should be noted that according to some embodiments, the width of lower portion 115b1 gradually decreases in a direction from the top of lower portion 115b1 to base panel 111.

In some embodiments, the widths of the intermediate portions 115b2 of the barrier structures 115b are substantially the same. Furthermore, according to some embodiments, the top surface and sidewalls of upper portion 115b3 of barrier structure 115b are curved, and the width of upper portion 115b3 gradually increases in a direction from the top of upper portion 115b3 to substrate 111. It should be noted that the profile of the blocking structure 115b may be adjusted via controlling the moving speed of the device 112 (e.g., dispensing speed and curing speed), and/or parameters of the curing process (e.g., the dose of the uv light in the uv curing process, or the temperature in the thermal curing process). For example, to form the blocking structure 115b, the movement of the device 112 may be accelerated.

Thereafter, according to some embodiments, as shown in fig. 3B, an underfill layer 117 is formed, and a barrier structure 115B' is formed from the barrier structure 115B. In some embodiments, the underfill layer 117 has an extension portion 117b that protrudes laterally from the edge 110E of the encapsulation member 110.

More specifically, in some embodiments, since the material of the barrier structure 115b is a two-dimensional cross-linked polymer, the barrier structure 115b may be deformed during a curing process used to form the underfill layer 117. For example, the barrier structure 115b may become wider and shorter during the curing process. In some embodiments, the height of the blocking structure 115b 'is less than the height of the blocking structure 115b, and the width of the blocking structure 115 b' is greater than the width of the blocking structure 115 b.

In some embodiments, the barrier structure 115b becomes wider during the curing process used to harden the underfill layer 117. Accordingly, the barrier structure 115b may provide a pushing force in a lateral direction from the barrier structure 115b to the underfill layer 117, thereby further limiting the size of the extended portion 117b of the underfill layer 117.

Further, since the flow of the underfill layer 117 is restricted by the lateral thrust of the barrier structure 115b during the curing process for forming the underfill layer 117, the underfill layer 117 with less internal voids (voids) can be formed. According to some embodiments, as shown in fig. 3B, the profile of the barrier structure 115B' is close to circular after the curing process for forming the underfill layer 117.

Thereafter, according to some embodiments, as shown in fig. 3C, similar to the process of fig. 1E-1F, the blocking structure 115b is removed, the cap cover 123a is attached to the first surface 111a of the substrate 111 via the adhesion layer 119 and the thermal paste 121, and the connector 125 is bonded to the second surface 111b of the substrate 111. After the connectors 125 are formed, the package structure 200a is obtained. Some materials and processes for forming the package structure 200a shown in fig. 3C may be similar or identical to those for forming the package structure 100a shown in fig. 1F, and are not repeated herein.

In some embodiments, the extension 117b of the underfill layer 117 has a width W_1bAnd is in direct contact with the first surface 111a of the substrate 111, and the extension portion 117b has a width W_2bWidth ofW_2bIs the minimum lateral distance between the barrier structure 115B' (as shown in fig. 3B) and the underfill layer 117, the encapsulation member 110 and the contact point, and has a width W_1bIs greater than width W_2b. Furthermore, the extension portion 117b of the underfill layer 117 has a maximum height H above the first surface 111a of the substrate 111_1b. In some embodiments, the maximum height H_1bAnd width W_1bRatio (H)_1b/W_1b) Greater than or equal to about 0.8, and may reduce or eliminate delamination problems.

Fig. 4 is a cross-sectional view of a package structure 200b according to some embodiments of the present disclosure. Some materials and processes for forming the package structure 200b shown in fig. 4 may be similar or identical to those for forming the package structure 100b shown in fig. 2, and are not repeated herein.

According to some embodiments, as shown in fig. 4, the package structure 200a of fig. 3C is different from the package structure 200b of fig. 4 in that the cap 123b is attached to the first surface 111a, and the thermal paste 121 is not formed over the encapsulation member 110, unlike the cap 123a of the package structure 200a and the cap 123b of the package structure 200 b. In some embodiments, the encapsulation member 110 is surrounded by the cover 123b, and the top surface of the encapsulation member 110 is not covered by the cover 123 b.

Fig. 5A-5C are cross-sectional views of various stages of a process of forming a package structure 300a, according to some embodiments of the present disclosure.

According to some embodiments, as shown in fig. 5A, similar to the process of fig. 1C, a barrier structure 115C is formed over the first surface 111a by dispensing and curing a polymer material 114C via the device 112. In some embodiments, the polymer material 114c is an acrylic-based polymer, a polyimide, an epoxy, another suitable material, or a combination thereof. In some embodiments, polymeric material 114c is a three-dimensional cross-linked polymer.

The polymer material 114c of the barrier structure 115c may have a different etch selectivity, e.g., etch rate, than the material of the molding compound layer 107 and the material of the subsequently formed underfill layer, so that in subsequent processes, the barrier structure 115c may be easily removed without damaging other elements in the final package structure 300 a. In some embodiments, the polymeric material 114c is made of a water-soluble polymer and can be easily dissolved in water without leaving any residue.

Some processes for forming the barrier structure 115C shown in fig. 5A may be similar or identical to the processes for forming the barrier structure 115A shown in fig. 1C, and will not be described herein again. The barrier structure 115c may include a lower portion 115c1 adjacent to the first surface 111a of the substrate 111, a middle portion 115c2 above the lower portion 115c1, and an upper portion 115c3 above the middle portion 115c 2. It should be noted that lower portion 115c1 is substantially the same width as middle portion 115c2 according to some embodiments.

Furthermore, according to some embodiments, the top surface and sidewalls of upper portion 115c3 of barrier structure 115c are curved, and the width of upper portion 115c3 gradually increases in a direction from the top of upper portion 115c3 to substrate 111. It should be noted that the profile of the blocking structure 115c may be adjusted via controlling the moving speed of the device 112 (e.g., dispensing speed and curing speed), and/or parameters of the curing process (e.g., the dose of the uv light in the uv curing process, or the temperature in the thermal curing process). In some embodiments, the movement speed of the means for forming the barrier structure 115c 112 is between the movement speed of the means for forming the barrier structure 115a 112 and the movement speed of the means for forming the barrier structure 115b 112.

Thereafter, according to some embodiments, an underfill layer 117 is formed, as shown in fig. 5B. In some embodiments, the underfill layer 117 has an extension portion 117c that protrudes laterally from the edge 110E of the encapsulation member 110.

The extension portion 117c of the underfill layer 117 includes a lower portion 117c1 adjacent to the first surface 111a of the substrate 111, a middle portion 117c2 above the lower portion 117c1, and an upper portion 117c3 above the middle portion 117c 2. In some embodiments, the lower portion 117c1 of the underfill layer 117 is substantially the same width as the intermediate portion 117c 2. Further, according to some embodiments, the top surface and the side wall of the upper portion 117c3 of the extension portion 117c are curved, and the width of the upper portion 117c3 gradually increases in a direction from the top of the upper portion 117c3 to the substrate 111.

In some embodiments, the lower portion 117c1 of the extension portion 117c has a width W_lcAnd is in direct contact with the first surface 111a of the substrate 111, and a middle portion 117c2 of the extension portion 117c has a width W_2cAnd a width W_2cAnd width W_1cAre substantially the same. Furthermore, the extended portion 117c of the underfill layer 117 has a maximum height H above the first surface 111a of the substrate 111_1c. In some embodiments, the maximum height H_1cAnd width W_1cRatio (H)_1c/W_1c) Greater than or equal to about 0.8, and may reduce or eliminate delamination problems.

Thereafter, according to some embodiments, as shown in fig. 5C, similar to the process of fig. 1E-1F, the blocking structure 115C is removed, the cap 123C is attached to the first surface 111a of the substrate 111 via the adhesion layer 119 and the thermal paste 121, and the connector 125 is bonded to the second surface 111b of the substrate 111. After the connector 125 is formed, the package structure 300a is obtained. Some materials and processes for forming the package structure 300a shown in fig. 5C may be similar or identical to those for forming the package structure 100a shown in fig. 1F, and are not repeated herein.

Fig. 6 is a cross-sectional view of a package structure 300b according to some embodiments of the present disclosure. Some materials and processes for forming the package structure 300b shown in fig. 6 may be similar or identical to those for forming the package structure 100b shown in fig. 2, and are not repeated herein.

According to some embodiments, as shown in fig. 6, the package structure 300a of fig. 5C is different from the package structure 300b of fig. 6 in that the cap 123b is attached to the first surface 111a, and the thermal paste 121 is not formed over the encapsulation member 110, unlike the cap 123a of the package structure 300a and the cap 123b of the package structure 300 b. In some embodiments, the encapsulation member 110 is surrounded by the cover 123b, and the top surface of the encapsulation member 110 is not covered by the cover 123 b.

Fig. 7 is a cross-sectional view of a stage in the process of forming a package structure according to some embodiments of the present disclosure. In some embodiments, the height H of the connector 109₂Greater than the maximum height H of the barrier structure 115d₃And the underfill layer 117 partially exposes the sidewalls of the interposer 101'.

In some embodiments, the underfill layer 117 has an extension portion 117d that protrudes laterally from the edge 110E of the encapsulation member 110. It should be noted that, according to some embodiments, the extension 117d has a width W_1dAnd is in direct contact with the first surface 111a of the substrate 111 and has a width W_1dWidth W greater than FIG. 1D_1aWidth W of FIG. 3C_1bAnd width W of FIG. 5B_1c. However, the extended portion 117d of the underfill layer 117 has a maximum height H above the first surface 111a of the substrate 111_1d. In some embodiments, the maximum height H_1dAnd width W_1dRatio (H)_1d/W_1d) Greater than or equal to about 0.8, and may reduce or eliminate delamination problems.

Fig. 8 is a cross-sectional view of a stage in the process of forming a package structure according to some embodiments of the present disclosure. In some embodiments, the top surface of the barrier structure 115e is higher than the top surface of the encapsulation member 110, and the underfill layer 117 partially exposes the sidewalls of the molding compound layer 107. In some embodiments, the underfill layer 117 has an extension portion 117E that protrudes laterally from the edge 110E of the encapsulation member 110.

It should be noted that, according to some embodiments, the extension 117e has a maximum height H_1eAnd a maximum height H_1eMaximum height H greater than FIG. 1D_1aMaximum height H in FIG. 3C_1bMaximum height H in FIG. 5B_1cAnd the maximum height H of FIG. 7_1d. Further, the extension portion 117e has a width W_1eAnd is in direct contact with the first surface 111a of the substrate 111. In some embodiments, the maximum height H_1eAnd width W_1eRatio (H)_1e/W_1e) Greater than or equal to about 0.8, and may reduce or eliminate delamination problems。

Fig. 9 is a cross-sectional view of a stage in the process of forming a package structure according to some embodiments of the present disclosure. In some embodiments, the barrier structure 115f is formed in direct contact with the sidewalls of the encapsulation member 110, and the barrier structure 115f is formed by some processes similar to the barrier structure 115B' shown in fig. 3B.

In some embodiments, the underfill layer 117 has an extension portion 117f that protrudes laterally from the edge 110E of the encapsulation member 110. It should be noted that according to some embodiments, the extension portion 117f has curved sidewalls, and the width of the extension portion 117f gradually increases in a direction from the top of the extension portion 117f to the substrate 111.

The extension 117f has a maximum height H_1fAnd the extension portion 117e has a width W_1fAnd is in direct contact with the first surface 111a of the substrate 111. In some embodiments, the maximum height H_1fAnd width W_1fRatio (H)_1f/W_1f) Greater than or equal to about 0.8, and may reduce or eliminate delamination problems.

Fig. 10A-10D are top views of various stages of a process of forming a package structure according to some embodiments of the present disclosure. The package structure may be similar to or the same as the package structure described above, and is not described herein again.

According to some embodiments, as shown in fig. 10A, the package member 110 and the plurality of passive members 130 are bonded to the first surface 111a of the substrate 111. Some materials and processes for forming the encapsulation member 110 shown in fig. 10A may be similar or identical to those used for forming the encapsulation member 110 shown in fig. 1A, and are not repeated herein.

Although four first semiconductor dies 105a and one second semiconductor die 105b are shown in each package member 110 in fig. 10A, the number of first semiconductor dies 105a and the number of second semiconductor dies 105b in each package member 110 are not limited thereto. In some embodiments, the passive member 130 is disposed around the encapsulation member 110 and is separate from the encapsulation member 110.

Thereafter, according to some embodiments, as shown in fig. 10B, a barrier structure 115 is formed between the passive member 130 and the encapsulation member 110. In some embodiments, the barrier structure 115 may be the barrier structure 115A of fig. 1C, the barrier structure 115b of fig. 3A, the barrier structure 115C of fig. 5A, the barrier structure 115d of fig. 7, the barrier structure 115e of fig. 8, or the barrier structure 115f of fig. 9.

Further, according to some embodiments, in the top view of fig. 10B, the blocking structure 115 includes four L-shaped portions, and each L-shaped portion is disposed around each corner of the encapsulation member 110.

According to some embodiments, as shown in fig. 10C, after forming the barrier structure 115, an underfill layer 117 is formed between the barrier structure 115 and the encapsulation member 110. Thereafter, according to some embodiments, as shown in fig. 10D, the barrier structure 115 is removed by an etching process.

According to some embodiments, as shown in fig. 10D, the underfill layer 117 has an extension portion 117EP, the extension portion 117EP protruding laterally from the edge 110E of the encapsulation member 110. In some embodiments, the extended portion 117EP of the underfill layer 117 may be the extended portion 117a of the underfill layer 117 in fig. 1D, the extended portion 117B of the underfill layer 117 in fig. 3B, the extended portion 117c of the underfill layer 117 in fig. 5B, the extended portion 117D of the underfill layer 117 in fig. 7, the extended portion 117e of the underfill layer 117 in fig. 8, or the extended portion 117f of the underfill layer 117 in fig. 9.

In some embodiments, in the top view of fig. 10D, extension 117EP has a width W_3aWidth W_3bAnd a width W_3cAnd a width W_3bIn the width W_3aAnd width W_3cIn the meantime. In some embodiments, the underfill layer 117 is confined by an L-shaped portion of the barrier structure 115, the barrier structure 115 being disposed around each corner of the package member 110. Thus, according to some embodiments, the width W_3bIs greater than width W_3aAnd width W_3c. Further, in some embodiments, the width W_3aAnd width W_3cAre substantially the same.

Furthermore, most delamination problems (e.g., cracks) in the underfill layer 117 occur at locations around the corners of the package member 110, particularly when more than one semiconductor die is disposed in the package member 110. Providing the L-shaped portion of the blocking structure 115 around the corners of the package member 110 has a lower process cost and is a more economical way to reduce or eliminate this problem.

Furthermore, since the blocking structure 115 is disposed between the encapsulation member 110 and the passive member 130, the underfill layer 117 may be prevented from contacting the passive member 130, and the passive member 130 may be prevented from being damaged.

Fig. 11A-11B are top views of various stages of a process of forming a package structure according to some embodiments of the present disclosure.

Similar to the structure of fig. 10C. According to some embodiments, a barrier structure 115' and an underfill layer 117 are formed in fig. 11A. In the top view of fig. 11A, the barrier structure 115 of fig. 10C differs from the barrier structure 115 'of fig. 11A in that the barrier structure 115' is formed to surround the edge of the encapsulation member 110, and the underfill layer 117 is enclosed by the barrier structure 115.

Since the blocking structure 115' is disposed between the encapsulation member 110 and the passive member 130, the underfill layer 117 may be prevented from contacting the passive member 130, and damage to the passive member 130 may be avoided.

In embodiments of the above-described package structures 100a,100b,200a,200b,300a,300b and the above-described methods of forming the package structures, the profile and dimensions (i.e., the ratio (H) of (H) to (H) is a ratio of) the profile and size (i.e., the ratio of (H) to (H) is a ratio of) the extensions of the underfill layer 117 (including the extensions 117a,117b,117c,117d,117e,117f, and 117EP) may be controlled and limited by the barrier structures (including the barrier structures 115a,115b,115 c,115d,115 e, 115f,115, and 115_1a/W_1a、H_1b/W_1b、H_1c/W_1c、H_1d/W_1d、H_1e/W_1eAnd H_1f/W_1f)). Thus, the delamination problem in the underfill layer 117 may be reduced or eliminated.

In addition, the barrier structure allows for an extension of the underfill layer 117 (bag)Including extension portions 117a,117b,117c,117d,117e,117f, and 117EP) have a reduced width (e.g., width W_la、W_lb、W_lc、W_ld、W_leAnd W_lf) Allowing the size of the substrate 111 to be reduced and forming the underfill layer 117 after removing the barrier structures (including the barrier structures 115a,115b,115 c,115d,115 e, 115f,115, and 115') may reduce the size of the package structures 100a,100b,200a,200b,300a,300 b.

Embodiments of package structures and methods of forming the same are provided. A method of forming an encapsulation structure may include bonding an encapsulation member to a substrate, forming a barrier structure over the substrate, forming an underfill layer between the barrier structure and the encapsulation member, and removing the barrier structure after forming the underfill layer. The package assembly includes an interposer and a plurality of semiconductor dies over the interposer. Since there is more than one semiconductor die in the encapsulation member, delamination problems (e.g., cracks) may easily occur in the portions of the underfill layer around the corners of the encapsulation member. By forming an underfill layer between the barrier structure and the encapsulation member, the size and profile of the underfill layer may be controlled. Thus, delamination problems, such as cracks in the underfill layer that grow along the interface between the encapsulation member and the underfill layer, may be reduced or eliminated.

In some embodiments, a method of forming a package structure is provided. A method of forming a package structure includes bonding a package member to a first surface of a substrate via a plurality of first connectors. The package assembly includes an interposer, a first semiconductor die and a second semiconductor die positioned over the interposer. The method of forming the encapsulation structure also includes forming a barrier structure over the first surface of the substrate. The blocking structure is located around and separated from the encapsulation member. The method of forming the encapsulation structure further includes forming an underfill layer between the barrier structure and the encapsulation member, and removing the barrier structure after forming the underfill layer. In some embodiments, forming the package component further includes bonding the first semiconductor die and the second semiconductor die to the interposer wafer via a plurality of second connectors. Forming a molding compound layer over the interposer wafer and laterally surrounding the first and second semiconductor dies, and singulating the molding compound layer and the interposer wafer to form the package member. In some embodiments, the barrier structure includes a lower portion abutting the substrate, a middle portion above the lower portion, and an upper portion above the middle portion, and wherein a width of the middle portion of the barrier structure is substantially the same, the lower portion of the barrier structure has curved sidewalls, and the width of the lower portion increases in a direction from a top of the lower portion to the substrate. In some embodiments, forming the barrier structure further comprises dispensing a polymer material over the first surface of the substrate, and curing the polymer material to form the barrier structure, wherein a height of the barrier structure before curing the polymer material is greater than a height of the barrier structure after curing the polymer material, and a width of the barrier structure before curing the polymer material is less than a width of the barrier structure after curing the polymer material. In some embodiments, an interface between the barrier structure and the underfill layer is substantially perpendicular to the first surface of the substrate. In some embodiments, the method further comprises forming a passive member over the first surface of the substrate, wherein the blocking structure is between the passive member and the encapsulation member. In some embodiments, the method further includes attaching a cap over the first surface of the substrate via an adhesion layer after removing the barrier structure, wherein the encapsulation member is surrounded by the cap, and forming a plurality of third connectors over a second surface of the substrate, wherein the second surface is opposite to the first surface.

In some embodiments, a method of forming a package structure is provided. A method of forming a package structure includes bonding a package member to a substrate via a plurality of connectors. The package component includes an interposer, a plurality of semiconductor dies over the interposer, and a molding compound layer over the interposer and laterally surrounding the plurality of semiconductor dies. The method of forming the package structure also includes forming a barrier structure over the substrate. Each corner of the enclosing member is surrounded by a blocking structure. The method of forming the package structure further includes forming an underfill layer surrounding the connector and in direct contact with the barrier structure, and removing the barrier structure after forming the underfill layer. In some embodiments, the encapsulation member is a chip on wafer package, and the underfill partially exposes sidewalls of the molding compound layer. In some embodiments, the barrier structure is made of an acrylic-based polymer, and wherein removing the barrier structure comprises dissolving the barrier structure with water. In some embodiments, the blocking structure comprises four L-shaped portions, and each of the L-shaped portions is located around each corner of the encapsulation member in a top view. In some embodiments, the underfill layer is enclosed by the barrier structure in a top view. In some embodiments, the height of the connector is greater than the height of the barrier structure, and the underfill partially exposes the sidewalls of the interposer.

In some embodiments, a package structure is provided. The package structure includes a package member bonded to a first surface of a substrate via a plurality of first connectors. The package assembly includes an interposer, a first semiconductor die and a second semiconductor die positioned over the interposer. The package structure also includes an underfill layer that laterally surrounds the first connector. The extension portion of the underfill layer protrudes laterally from an edge of the encapsulation member, and a ratio of a maximum height of the extension portion to a first width of a bottommost surface of the extension portion is greater than or equal to about 0.8. In some embodiments, the package structure further includes a molding compound layer laterally surrounding the first semiconductor die and the second semiconductor die, wherein a top surface of the molding compound layer is higher than a top surface of the extended portion of the underfill layer. In some embodiments, the extended portion of the underfill layer includes a lower portion adjacent to the first surface of the substrate, a middle portion over the lower portion, and an upper portion over the middle portion, and wherein in a cross-sectional view perpendicular to the first surface of the substrate, widths of the middle portions are substantially the same. In some embodiments, a lower portion of the extended portion of the underfill layer has curved sidewalls, and a width of the lower portion decreases in a direction from a top of the lower portion to the substrate. In some embodiments, a width of a lower portion of the extended portion of the underfill layer is substantially the same as a width of a middle portion of the extended portion of the underfill layer, and a sidewall of the lower portion is substantially perpendicular to the first surface of the substrate. In some embodiments, in a top view, the extending portion of the underfill layer that protrudes laterally from the edge of the encapsulation member has a second width, a third width, and a fourth width, the third width being between the second width and the fourth width, and wherein the second width is substantially the same as the fourth width, and the third width is greater than the second width. In some embodiments, the package structure further includes a passive member, a cover, and a plurality of second connectors. The passive member is over the first surface of the substrate, wherein the underfill layer is separated from the passive member. The cover lid is attached to the first surface of the substrate via an adhesive layer, wherein the encapsulation member and the passive member are surrounded by the cover lid. A plurality of second connectors are bonded to a second surface of the substrate, wherein the second surface is opposite the first surface.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent arrangements do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.