阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 新井雅俊 于 2020-02-21 设计创作，主要内容包括：实施方式提供能够降低关断时的漏电流的半导体装置。实施方式的半导体装置,包括：第1导电型的半导体部；在上述半导体部的背面上设置的第1电极；在上述半导体部的表面上设置的第2电极；第2导电型的第1半导体层,配置于在上述半导体部的上述表面侧设置的沟槽的内部；及绝缘层,设置于上述沟槽的内部,将上述第1半导体层从上述半导体部电绝缘。上述第2电极经由具有整流性的接触面而连接于上述半导体部,与上述第1半导体层电连接。(Embodiments provide a semiconductor device capable of reducing a leakage current at the time of turn-off. The semiconductor device of an embodiment includes: a semiconductor portion of a 1 st conductivity type; a 1 st electrode provided on a rear surface of the semiconductor section; a 2 nd electrode provided on a surface of the semiconductor section; a 1 st semiconductor layer of a 2 nd conductivity type disposed inside a trench provided on the front surface side of the semiconductor section; and an insulating layer provided inside the trench and electrically insulating the 1 st semiconductor layer from the semiconductor section. The 2 nd electrode is connected to the semiconductor section via a contact surface having a rectifying property, and is electrically connected to the 1 st semiconductor layer.)

1. A semiconductor device, comprising:

a semiconductor portion of a 1 st conductivity type;

a 1 st electrode provided on a rear surface of the semiconductor section;

a 2 nd electrode provided on a surface of the semiconductor section;

a 1 st semiconductor layer of a 2 nd conductivity type disposed inside a trench provided on the front surface side of the semiconductor section; and

an insulating layer provided inside the trench to electrically insulate the 1 st semiconductor layer from the semiconductor section,

the 2 nd electrode is connected to the semiconductor section via a contact surface having a rectifying property, and is electrically connected to the 1 st semiconductor layer.

2. The semiconductor device according to claim 1, further comprising:

a 2 nd semiconductor layer of a 1 st conductivity type provided inside the trench and having an end portion disposed closer to a bottom of the trench than the 1 st semiconductor layer,

the 2 nd semiconductor layer is electrically insulated from the semiconductor section by the insulating layer.

3. The semiconductor device according to claim 2,

the 1 st semiconductor layer is located between the 2 nd semiconductor layer and the 2 nd electrode.

4. The semiconductor device according to claim 3,

the 2 nd semiconductor layer is directly connected to the 1 st semiconductor layer.

5. The semiconductor device according to claim 4,

the 1 st semiconductor layer has a width wider than that of the 2 nd semiconductor layer in a direction along the surface of the semiconductor section.

6. The semiconductor device according to claim 2, further comprising:

a 3 rd semiconductor layer of a 1 st conductivity type provided between the 1 st semiconductor layer and the 1 st electrode,

the 3 rd semiconductor layer is electrically insulated from the semiconductor section by the insulating layer and is in direct contact with the 1 st semiconductor layer,

the 1 st semiconductor layer has a width wider than that of the 2 nd semiconductor layer in a direction along the surface of the semiconductor section.

7. The semiconductor device according to claim 3, further comprising:

a 3 rd semiconductor layer of a 1 st conductivity type provided between the 1 st semiconductor layer and the 1 st electrode,

the 3 rd semiconductor layer is electrically insulated from the semiconductor section by the insulating layer and is in direct contact with the 1 st semiconductor layer,

the 1 st semiconductor layer has a width wider than that of the 2 nd semiconductor layer in a direction along the surface of the semiconductor section.

8. The semiconductor device according to claim 6,

the 3 rd semiconductor layer has the same width as the 1 st semiconductor layer in a direction along the surface of the semiconductor section.

9. The semiconductor device according to claim 7,

the 3 rd semiconductor layer has the same width as the 1 st semiconductor layer in a direction along the surface of the semiconductor section.

10. The semiconductor device according to claim 2,

the 1 st semiconductor layer has a 1 st end on the 1 st electrode side and a 2 nd end on the 2 nd electrode side,

the 2 nd semiconductor layer has a 1 st end on the 1 st electrode side and a 2 nd end on the 2 nd electrode side,

the 2 nd end of the 1 st semiconductor layer and the 2 nd end of the 2 nd semiconductor layer are directly connected to the 2 nd electrode,

the 1 st semiconductor layer is located between the semiconductor section and the 2 nd semiconductor layer.

11. The semiconductor device according to any one of claims 1 to 10,

the semiconductor section includes a 1 st region and a 2 nd region, the 2 nd region including an n-type impurity at a lower concentration than the n-type impurity in the 1 st region,

the 2 nd region is located between the 1 st region and the 2 nd electrode,

the 2 nd electrode is in contact with the 2 nd region.

Technical Field

Embodiments relate to a semiconductor device.

Background

In the power semiconductor device, it is desirable to have characteristics of high withstand voltage and low leakage current at the time of turning off of the switching operation.

Disclosure of Invention

Embodiments provide a semiconductor device capable of reducing a leakage current at the time of turn-off.

The semiconductor device of the embodiment includes: a semiconductor portion of a 1 st conductivity type; a 1 st electrode provided on a rear surface of the semiconductor section; a 2 nd electrode provided on a surface of the semiconductor section; a 1 st semiconductor layer of a 2 nd conductivity type disposed inside a trench provided on the front surface side of the semiconductor section; and an insulating layer provided inside the trench and electrically insulating the 1 st semiconductor layer from the semiconductor section. The 2 nd electrode is connected to the semiconductor section via a contact surface having a rectifying property, and is electrically connected to the 1 st semiconductor layer.

Drawings

Fig. 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment.

Fig. 2 (a) and (b) are schematic views showing other cross sections of the semiconductor device according to the embodiment.

Fig. 3 (a) and (b) are schematic diagrams showing characteristics of the semiconductor device according to the embodiment.

Fig. 4 (a) and (b) are schematic cross-sectional views showing a semiconductor device according to modification 1 of the embodiment.

Fig. 5 (a) and (b) are schematic cross-sectional views showing a semiconductor device according to modification 2 of the embodiment.

Fig. 6 (a) and (b) are schematic cross-sectional views of a semiconductor device according to modification 3 of the embodiment.

Fig. 7 (a) and (b) are schematic cross-sectional views showing a semiconductor device according to a 4 th modification of the embodiment.

Fig. 8 (a) and (b) are schematic cross-sectional views showing a semiconductor device according to a modification example 5 of the embodiment.

Detailed Description

Hereinafter, the embodiments will be described with reference to the drawings. The same components in the drawings are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate, and different components will be described. The drawings are schematic or conceptual, and the relationship between the thickness and width of each portion, the ratio of the sizes of the portions, and the like are not necessarily the same as those in reality. Even when the same portions are shown, the sizes and ratios may be different from each other in some cases.

The arrangement and structure of each part will be described using the X, Y, and Z axes shown in the drawings. The X, Y and Z axes are orthogonal to each other and respectively represent the X, Y and Z directions. In some cases, the Z direction is described as an upper direction, and the opposite direction is described as a lower direction.

Fig. 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is, for example, a Schottky Barrier Diode (SBD).

The semiconductor device 1 includes: a semiconductor section 10 having n-type conductivity, an anode electrode 20, a cathode electrode 30, and a p-type semiconductor layer 40. The anode electrode 20 is provided on the front surface of the semiconductor section 10, and the cathode electrode 30 is provided on the rear surface of the semiconductor section 10. The semiconductor portion 10 is, for example, silicon, and the p-type semiconductor layer 40 is, for example, a p-type polysilicon layer.

The anode electrode 20 includes, for example, a contact layer 23 and a bonding layer 25. The contact layer 23 is directly connected to the semiconductor section 10 via a contact surface having a rectifying property. The contact layer 23 makes a so-called schottky connection with the semiconductor section 10. The contact layer 23 is, for example, a metal layer containing titanium or cobalt. The bonding layer 25 is, for example, a metal layer containing aluminum.

The p-type semiconductor layer 40 is disposed inside the trench FT provided on the front surface side of the semiconductor section 10. The p-type semiconductor layer 40 is electrically insulated from the semiconductor section 10 by an insulating layer 41. The insulating layer 41 contains, for example, silicon oxide. The p-type semiconductor layer 40 functions as a field plate, for example.

The p-type semiconductor layer 40 is electrically connected to the anode electrode 20. That is, the p-type semiconductor layer 40 and the anode electrode 20 have the same potential. In this example, the p-type semiconductor layer 40 is directly connected to the contact layer 23.

The semiconductor part 10 includes, for example, an n-type region 11 and n⁺And a molding region 13. Contact layer 23 is in contact with n-type region 11. n is⁺Type region 13 is located between n-type region 11 and cathode electrode 30. n is⁺Type region 13 contains an n-type impurity at a higher concentration than the n-type impurity of n-type region 11. Cathode electrodeElectrode 30, for example, with n⁺The pattern regions 13 are in contact and electrically connected.

Fig. 2 (a) and (b) are schematic diagrams showing other cross sections of the semiconductor device 1 according to the embodiment. Fig. 2 (a) and (b) are schematic views showing cross sections taken along the line a-a shown in fig. 1. In addition, fig. 1 is a schematic view showing a cross section along the line C-C shown in fig. 2 (a) or a cross section along the line D-D shown in fig. 2 (b).

As shown in fig. 2 (a), a plurality of grooves FT extending in the Y direction are provided. The p-type semiconductor layer 40 is disposed in each of the trenches FT. In this example, a plurality of p-type semiconductor layers 40 are provided.

As shown in fig. 2 (b), the trenches FT are arranged in a lattice shape. The p-type semiconductor layer 40 is provided in a lattice shape inside the trench FT. In this example, the p-type semiconductor layer 40 is integrally provided.

Fig. 3 (a) and (b) are schematic cross-sectional views showing characteristics of the semiconductor device 1 according to the embodiment. Fig. 3 (a) is a schematic diagram showing the electric field intensity distribution in n-type region 11 when semiconductor device 1 is turned off. The electric field intensity distribution along the broken line B shown in fig. 1 is shown in (a) of fig. 3. Fig. 3 (b) is a schematic diagram showing current/voltage characteristics of the semiconductor device 1 in the reverse bias.

The symbol "NP" shown in the figure indicates the characteristics of the semiconductor device 1. The symbol "NN" represents the characteristics of the semiconductor device of the comparative example. In the semiconductor device of the comparative example, an n-type semiconductor layer is disposed inside the trench FT instead of the p-type semiconductor layer 40.

Further, symbol "SB" shown in fig. 3 (a) indicates the position of the interface of n-type region 11 and anode electrode 20 (i.e., the position of the schottky junction). The symbol "FPE" indicates the position of the cathode electrode 30 side end in the p-type semiconductor layer 40.

As shown in fig. 3 (a), in the semiconductor device 1, the electric field strength is maximized at the cathode electrode 30 side end FPE of the p-type semiconductor layer 40. Therefore, depletion of the n-type region 11 located between the adjacent trenches FT can be promoted. That is, even if the n-type impurity concentration of n-type region 11 is increased, n-type region 11 can be depleted, and a high withstand voltage at the time of shutdown can be maintained. In other words, by providing the semiconductor section 10 with the trench structure in which the p-type semiconductor layer 40 is arranged, the n-type region 11 can be made highly concentrated without lowering the withstand voltage at the time of turn-off. This can reduce the on-resistance of the semiconductor device 1.

In this embodiment, depletion of n-type region 11 in the vicinity of the schottky junction can be promoted by a potential difference between n-type region 11 and p-type semiconductor layer 40. That is, the electric field intensity at the position SB of the schottky junction can be reduced as compared with the comparative example in which the n-type semiconductor layer is disposed in the trench FT (see the portion denoted by NN in fig. 3 a).

As a result, as shown in fig. 3 (b), in the semiconductor device 1, the reverse current (i.e., the leakage current) can be reduced as compared with the semiconductor device of the comparative example. This can reduce power consumption of the semiconductor device 1.

Fig. 4 (a) and (B) are schematic cross-sectional views of semiconductor devices 2A and 2B according to modification 1 of the embodiment.

The semiconductor devices 2A and 2B include a p-type semiconductor layer 40a and an n-type semiconductor layer 40B. The p-type semiconductor layer 40a and the n-type semiconductor layer 40b are disposed inside the trench FT and electrically insulated from the semiconductor section 10 by the insulating layer 41.

As shown in fig. 4 (a), the p-type semiconductor layer 40a is located between the n-type region 11 and the n-type semiconductor layer 40b in the X direction. In addition, the n-type semiconductor layer 40b includes a portion between the 2 p-type semiconductor layers 40 a.

The p-type semiconductor layer 40a has an upper end on the anode electrode 20 side and a lower end on the cathode electrode 30 side. The n-type semiconductor layer 40b has an upper end on the anode electrode 20 side and a lower end on the cathode electrode 30 side. The lower end of the n-type semiconductor layer 40b is located closer to the bottom of the trench FT than the lower end of the p-type semiconductor layer 40 a. The upper end of the p-type semiconductor layer 40a and the upper end of the n-type semiconductor layer 40b are directly connected to the contact layer 23 of the anode electrode 20, for example.

The n-type semiconductor layer 40b has an end portion closer to the bottom of the trench FT than the p-type semiconductor layer 40 a. This can promote depletion of the n-type region 11 between adjacent trenches FT, and can improve the breakdown voltage at the time of turn-off. By disposing p-type semiconductor layer 40a above trench FT, the electric field at the interface between n-type region 11 and contact layer 23 (i.e., at the schottky junction) can be reduced, and the leakage current during reverse bias can be reduced.

In the semiconductor device 2B shown in fig. 4 (B), n is provided between the n-type region 11 and the anode electrode 20^－And a molding region 15. n is^－Type region 15 contains an n-type impurity at a lower concentration than the n-type impurity of n-type region 11. Contact layer 23 and n of anode electrode 20^－The pattern regions 15 are in contact. This can further promote n in reverse bias^－Depletion in the vicinity of the interface between type region 15 and contact layer 23. As a result, n can be further reduced^－The electric field intensity at the interface between type region 15 and contact layer 23 can suppress leakage current.

Fig. 5 (a) and (B) are schematic cross-sectional views of semiconductor devices 3A and 3B according to modification 2 of the embodiment.

The semiconductor devices 3A and 3B include a p-type semiconductor layer 40a, an n-type semiconductor layer 40B, and an n-type semiconductor layer 40 c. The p-type semiconductor layer 40a, the n-type semiconductor layer 40b, and the n-type semiconductor layer 40c are disposed inside the trench FT and electrically insulated from the semiconductor section 10 by the insulating layer 41.

As shown in fig. 5 (a), the p-type semiconductor layer 40a is located between the n-type region 11 and the n-type semiconductor layer 40b in the X direction. The n-type semiconductor layer 40c is located between the n-type region 11 and the n-type semiconductor layer 40b in the X direction. The p-type semiconductor layer 40a is located between the anode electrode 20 and the n-type semiconductor layer 40 c. The n-type semiconductor layer 40b includes portions between the 2 p-type semiconductor layers 40a and between the 2 n-type semiconductor layers 40 c.

The p-type semiconductor layer 40a has an upper end on the anode electrode 20 side and a lower end on the n-type semiconductor layer 40c side. The n-type semiconductor layer 40c has an upper end on the p-type semiconductor layer 40a side and a lower end on the cathode electrode 30 side. The lower end of the p-type semiconductor layer 40a is in direct contact with the upper end of the n-type semiconductor layer 40 c.

The n-type semiconductor layer 40b has an upper end on the anode electrode 20 side and a lower end on the cathode electrode 30 side. The upper end of the p-type semiconductor layer 40a and the upper end of the n-type semiconductor layer 40b are directly connected to the contact layer 23 of the anode electrode 20, for example.

The n-type semiconductor layer 40c may be electrically connected to the anode electrode 20 at a portion not shown. Accordingly, the n-type semiconductor layer 40c is also at the same potential as the anode electrode 20.

On the other hand, the lower end of the n-type semiconductor layer 40b is located closer to the bottom of the trench FT than the lower end of the n-type semiconductor layer 40 c. That is, the n-type semiconductor layer 40b has a portion extending further downward than the lower end of the n-type semiconductor layer 40 c. This can promote depletion of the n-type region 11 between adjacent trenches FT, and can improve the breakdown voltage at the time of turn-off.

By disposing p-type semiconductor layer 40a above trench FT, the electric field at the interface between n-type region 11 and contact layer 23 can be reduced, and leakage current during reverse bias can be reduced.

In the semiconductor device 3B shown in fig. 5 (B), n is provided between the n-type region 11 and the anode electrode 20^－And a molding region 15. n is^－Type region 15 contains an n-type impurity at a lower concentration than the n-type impurity of n-type region 11. Contact layer 23 and n of anode electrode 20^－The pattern regions 15 are in contact. This can further promote n in reverse bias^－Depletion in the vicinity of the interface between type region 15 and contact layer 23. As a result, n can be further reduced^－The electric field intensity at the interface between type region 15 and contact layer 23 can suppress leakage current.

Fig. 6 (a) and (B) are schematic cross-sectional views of semiconductor devices 4A and 4B according to modification 3 of the embodiment.

The semiconductor devices 4A and 4B include a p-type semiconductor layer 40a and an n-type semiconductor layer 40B. The p-type semiconductor layer 40a and the n-type semiconductor layer 40b are disposed inside the trench FT and electrically insulated from the semiconductor section 10 by the insulating layer 41.

As shown in fig. 6 (a), the p-type semiconductor layer 40a is located between the anode electrode 20 and the n-type semiconductor layer 40 b. The n-type semiconductor layer 40b has a width narrower than that of the p-type semiconductor layer 40a in the X direction.

The p-type semiconductor layer 40a has an upper end on the anode electrode 20 side and a lower end on the n-type semiconductor layer 40b side. The n-type semiconductor layer 40b has an upper end on the p-type semiconductor layer 40a side and a lower end on the cathode electrode 30 side. The upper end of the n-type semiconductor layer 40b is in direct contact with the lower end of the p-type semiconductor layer 40 a.

The upper end of the p-type semiconductor layer 40a is directly connected to the contact layer 23 of the anode electrode 20, for example. The n-type semiconductor layer 40b may be electrically connected to the anode electrode 20 at a portion not shown. Thereby, the n-type semiconductor layer 40b is also at the same potential as the anode electrode 20.

In this example, by disposing the n-type semiconductor layer 40b below the p-type semiconductor layer 40a, depletion of the n-type region 11 between adjacent trenches FT can be promoted, and the breakdown voltage at the time of off-state can be improved. By disposing p-type semiconductor layer 40a above trench FT, the electric field at the interface between n-type region 11 and contact layer 23 can be reduced, and leakage current during reverse bias can be reduced.

In the semiconductor device 4B shown in fig. 6 (B), n is provided between the n-type region 11 and the anode electrode 20^－And a molding region 15. Contact layer 23 and n of anode electrode 20^－The pattern regions 15 are in contact. This can further promote n in reverse bias^－Depletion in the vicinity of the interface between type region 15 and contact layer 23 can further reduce n^－The electric field strength at the interface of type region 15 and contact layer 23. This can suppress leakage current at the time of reverse bias.

Fig. 7 (a) and (B) are schematic cross-sectional views of semiconductor devices 5A and 5B according to modification 4 of the embodiment.

The semiconductor devices 5A and 5B include a p-type semiconductor layer 40a, an n-type semiconductor layer 40B, and an n-type semiconductor layer 40 c. The p-type semiconductor layer 40a, the n-type semiconductor layer 40b, and the n-type semiconductor layer 40c are disposed inside the trench FT and electrically insulated from the semiconductor section 10 by the insulating layer 41.

As shown in fig. 7 (a), the p-type semiconductor layer 40a and the n-type semiconductor layer 40c are located between the anode electrode 20 and the n-type semiconductor layer 40 b. The p-type semiconductor layer 40a is located between the anode electrode 20 and the n-type semiconductor layer 40c, and the n-type semiconductor layer 40c is located between the p-type semiconductor layer 40a and the n-type semiconductor layer 40 b. The n-type semiconductor layer 40b has a width narrower than the width of the p-type semiconductor layer 40a and the width of the n-type semiconductor layer 40c in the X direction.

The p-type semiconductor layer 40a has an upper end on the anode electrode 20 side and a lower end on the n-type semiconductor layer 40c side. The n-type semiconductor layer 40b has an upper end on the n-type semiconductor layer 40c side and a lower end on the cathode electrode 30 side. The upper end of the n-type semiconductor layer 40c is in direct contact with the lower end of the p-type semiconductor layer 40a, and the lower end of the n-type semiconductor layer 40c is in contact with the upper end of the n-type semiconductor layer 40 b.

The upper end of the p-type semiconductor layer 40a is directly connected to the contact layer 23 of the anode electrode 20, for example. The n-type semiconductor layer 40b or the n-type semiconductor layer 40c may be electrically connected to the anode electrode 20 at a portion not shown. Accordingly, the n-type semiconductor layers 40b and 40c are also at the same potential as the anode electrode 20.

In this example, by disposing the n-type semiconductor layer 40b below the n-type semiconductor layer 40c, depletion of the n-type region 11 between adjacent trenches FT can be promoted, and the breakdown voltage at the time of off-state can be improved. By disposing p-type semiconductor layer 40a above trench FT, the electric field at the interface between n-type region 11 and contact layer 23 can be reduced, and leakage current during reverse bias can be reduced.

In the semiconductor device 5B shown in fig. 7 (B), n is provided between the n-type region 11 and the anode electrode 20^－And a molding region 15. n is^－The type region 15 is located between the adjacent p-type semiconductor layers 40 a. Contact layer 23 and n of anode electrode 20^－The pattern regions 15 are in contact. This can further promote n in reverse bias^－Depletion in the vicinity of the interface between type region 15 and contact layer 23 can further reduce n^－The electric field strength at the interface of type region 15 and contact layer 23. This can suppress leakage current at the time of reverse bias.

Fig. 8 (a) and (b) are schematic cross-sectional views of semiconductor devices 6 and 7 according to modification 5 of the embodiment.

The semiconductor device 6 shown in fig. 8 (a) includes a p-type semiconductor layer 40a and an n-type semiconductor layer 40 b. The p-type semiconductor layer 40a and the n-type semiconductor layer 40b are disposed inside the trench FT and electrically insulated from the semiconductor section 10 by the insulating layer 41.

As shown in fig. 8 (a), the p-type semiconductor layer 40a is located between the anode electrode 20 and the n-type semiconductor layer 40 b. The n-type semiconductor layer 40b has a width narrower than that of the p-type semiconductor layer 40a in the X direction.

The p-type semiconductor layer 40a has an upper end on the anode electrode 20 side and a lower end on the n-type semiconductor layer 40b side. The n-type semiconductor layer 40b has an upper end on the p-type semiconductor layer 40a side and a lower end on the cathode electrode 30 side. The n-type semiconductor layer 40b is provided at a position separated from the p-type semiconductor layer 40 a.

The upper end of the p-type semiconductor layer 40a is directly connected to the contact layer 23 of the anode electrode 20, for example. The n-type semiconductor layer 40b is electrically connected to the anode electrode 20 at a portion not shown. Thereby, the n-type semiconductor layer 40b is also at the same potential as the anode electrode 20.

In this example, by disposing the n-type semiconductor layer 40b below the n-type semiconductor layer 40a, depletion of the n-type region 11 between adjacent trenches FT can be promoted, and the breakdown voltage at the time of off-state can be improved. By disposing p-type semiconductor layer 40a above trench FT, the electric field at the interface between n-type region 11 and contact layer 23 can be reduced, and leakage current during reverse bias can be reduced. N may be provided between n-type region 11 and anode electrode 20^－And a molding region 15.

The semiconductor device 7 shown in fig. 8 (b) includes a p-type semiconductor layer 40a, an n-type semiconductor layer 40b, and an n-type semiconductor layer 40 c. The p-type semiconductor layer 40a, the n-type semiconductor layer 40b, and the n-type semiconductor layer 40c are disposed inside the trench FT and electrically insulated from the semiconductor section 10 by the insulating layer 41.

As shown in fig. 8 (b), the p-type semiconductor layer 40a and the n-type semiconductor layer 40c are located between the anode electrode 20 and the n-type semiconductor layer 40 b. The p-type semiconductor layer 40a is located between the anode electrode 20 and the n-type semiconductor layer 40c, and the n-type semiconductor layer 40c is located between the p-type semiconductor layer 40a and the n-type semiconductor layer 40 b. The n-type semiconductor layer 40b has a width narrower than that of the p-type semiconductor layer 40a in the X direction.

The n-type semiconductor layer 40c has a width narrower than the width of the p-type semiconductor layer 40a and a width wider than the n-type semiconductor layer 40b in the X direction. The width of the n-type semiconductor layer 40c in the X direction is wider as it approaches the p-type semiconductor layer 40a, and is narrower as it approaches the n-type semiconductor layer 40 b.

The p-type semiconductor layer 40a has an upper end on the anode electrode 20 side and a lower end on the n-type semiconductor layer 40c side. The n-type semiconductor layer 40b has an upper end on the n-type semiconductor layer 40c side and a lower end on the cathode electrode 30 side. The upper end of the n-type semiconductor layer 40c directly contacts the lower end of the p-type semiconductor layer 40a, and the lower end of the n-type semiconductor layer 40c directly contacts the upper end of the n-type semiconductor layer 40 b.

The upper end of the p-type semiconductor layer 40a is directly connected to the contact layer 23 of the anode electrode 20, for example. The n-type semiconductor layer 40b or the n-type semiconductor layer 40c may be electrically connected to the anode electrode 20 at a portion not shown. Accordingly, the n-type semiconductor layers 40b and 40c are also at the same potential as the anode electrode 20.

In this example, by disposing the n-type semiconductor layer 40b below the n-type semiconductor layer 40c, depletion of the n-type region 11 between adjacent trenches FT can be promoted, and the breakdown voltage at the time of off-state can be improved. By disposing p-type semiconductor layer 40a above trench FT, the electric field at the interface between n-type region 11 and contact layer 23 can be reduced, and leakage current during reverse bias can be reduced.

Although the embodiments have been described above, the embodiments are not limited thereto. In either case, n can be provided between n-type region 11 and anode electrode 20^－And a molding region 15.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.