阅读说明：本技术 一种振荡器电路及flash芯片 (Oscillator circuit and flash chip ) 是由 南锺基 吴彤彤 刘梦 于 2020-12-15 设计创作，主要内容包括：本发明公开了一种振荡器电路及flash芯片,本振荡器电路的结构连接简单,当使能信号为0,第一mos管和第二mos管均导通,振荡器时钟脉冲始终保持低电平,但是振荡器的电流没有被关断,因此,等使能信号再次恢复高电平时,整个振荡器电路能快速振荡至稳定状态；在尽可能降低flash芯片的面积的同时满足振荡器电路的快速振荡稳定要求。(The invention discloses an oscillator circuit and a flash chip, the oscillator circuit has simple structural connection, when an enabling signal is 0, a first mos tube and a second mos tube are both conducted, clock pulse of the oscillator is always kept at a low level, but the current of the oscillator is not turned off, so that the whole oscillator circuit can rapidly oscillate to a stable state when the enabling signal recovers to a high level again; the area of the flash chip is reduced as much as possible, and the requirement of the oscillator circuit on quick oscillation stability is met.)

1. An oscillator circuit is characterized by comprising an odd number of inverters, wherein the number of the inverters is at least 3, the input end of the first inverter is connected with the output end of the last inverter, and the output end of the previous inverter is connected with the input end of the next inverter between the first inverter and the last inverter; the current input end of each phase inverter is connected with one end of a second current source I0, the other end of the second current source I0 is connected with one end of a first current source Itot, the other end of the second current source I0 is connected with a power supply voltage VCC, the other end of the first current source Itot is connected with the power supply voltage VCC, the current output end of each phase inverter is connected with one end of a third current source I1, the other end of the third current source I1 is grounded GND, and the output end of the last phase inverter outputs oscillator clock pulse OSC _ CLK; a mos tube is connected between every two adjacent inverters, a first mos tube nm0 is connected between the odd-numbered inverters and the even-numbered inverters, the drain electrode of the first mos tube nm0 is connected with the output end of the odd-numbered inverters, the source electrode of the first mos tube nm0 is grounded GND, the gate electrode of the first mos tube nm0 is connected with an enable signal enb, a second mos tube pm0 is connected between the even-numbered inverters and the odd-numbered inverters, the drain electrode of the second mos tube pm0 is connected with a power supply voltage VCC, the source electrode of the second mos tube pm0 is connected with the output end of the even-numbered inverters, the gate electrode of the second mos tube pm0 is connected with an enable signal en, and the enable signal enb is the opposite phase of the enable signal en;

the second current source I0 is a third mos tube pm1, the inverter comprises a fourth mos tube pm2 and a fifth mos tube nm1, the third current source I1 is a sixth mos tube nm2, the oscillator circuit further comprises a seventh mos tube nm3, an eighth mos tube nm4 and a ninth mos tube pm3, the drain and the gate of the seventh mos tube nm3 are connected together and then connected with the other end of the first current source Itot, the source of the seventh mos tube nm3 is grounded, the gate and the drain of the eighth mos tube nm4 are connected together and then connected with the gate of the seventh mos tube nm3, the source of the eighth mos tube 4 is grounded, the drain of the eighth mos tube nm4 is connected with the source of the ninth mos tube pm3, the drain of the ninth mos tube 3 is connected with the drain of the third mos tube 1, the drain of the third mos tube I59628 is connected together with the gate of the third mos tube pm, the drain of the ninth mos tube nm4 is connected with the drain of the ninth mos tube pm, the fourth mos tube pm is connected with the drain of the ninth mos tube 8653, the drain of the ninth mos tube 8653 and the fourth mos tube 86 2, the source electrode of the fifth mos tube nm1 is connected with the drain electrode of the sixth mos tube nm2, the source electrode of the sixth mos tube nm2 is grounded, the grid electrode of the fourth mos tube pm2 and the grid electrode of the fifth mos tube nm1 are connected together to output oscillator clock pulse OSC _ CLK, and the source electrode of the fourth mos tube pm2 and the drain electrode of the fifth mos tube nm1 are connected together to be connected with the drain electrode of the first mos tube nm 0/the source electrode of the second mos tube pm 0; the grid electrode and the drain electrode of the sixth mos transistor nm2 are connected together and then connected with the grid electrode of the eighth mos transistor nm 4.

2. The oscillator circuit of claim 1, wherein the first mos transistor nm0 is an nmos transistor.

3. The oscillator circuit of any of claims 1 or 2, wherein the second mos transistor pm0 is a pmos transistor.

4. The oscillator circuit of claim 1, wherein the third mos transistor pm1, the fourth mos transistor pm2 are pmos transistors, and the fifth mos transistor nm1, the sixth mos transistor nm2 are nmos transistors.

5. The oscillator circuit of claim 1, wherein the seventh mos transistor nm3, the eighth mos transistor nm4 are nmos transistors, and the ninth mos transistor pm3 is a pmos transistor.

6. The oscillator circuit according to claim 1, wherein the number of the inverters is 5.

7. The oscillator circuit of claim 6, wherein a first mos transistor nm0 is disposed between the first inverter and the second inverter, a second mos transistor pm0 is disposed between the second inverter and the third inverter, a first mos transistor nm0 is disposed between the third inverter and the fourth inverter, and a second mos transistor pm0 is disposed between the fourth inverter and the fifth inverter.

8. A flash chip comprising the oscillator circuit of any one of claims 1 to 7.

Technical Field

The invention relates to the technical field of semiconductor integrated circuits, in particular to an oscillator circuit and a flash chip.

Background

A relatively common method of shutting down an oscillator when it is not in use is to directly turn off the current. However, when the oscillator is re-enabled, there is a settling process as shown in fig. 1, since current is re-flowed through the oscillator, during which time the frequency of the oscillator is not desirable.

In order to solve the above problem, an nmos transistor or a pmos transistor is generally connected between two oscillators connected in sequence, so that the clock pulse of the oscillator always keeps low level, but the current of the oscillator is not turned off, and when the enable signal returns to high level again, the whole oscillator circuit can rapidly oscillate to a stable state. However, the existing oscillator circuit structure is complicated in connection, and the area of a flash chip is increased invisibly, which brings about a problem in the area of the chip.

Therefore, the prior art still needs to be improved and developed.

Disclosure of Invention

The invention aims to provide an oscillator circuit and a flash chip, and aims to solve the problems that the existing oscillator circuit is complex in structure connection and the area of the flash chip is increased.

The technical scheme of the invention is as follows: an oscillator circuit comprises an odd number of inverters, wherein the number of the inverters is at least 3, the input end of the first inverter is connected with the output end of the last inverter, and the output end of the previous inverter is connected with the input end of the next inverter between the first inverter and the last inverter; the current input end of each phase inverter is connected with one end of a second current source I0, the other end of the second current source I0 is connected with one end of a first current source Itot, the other end of the second current source I0 is connected with a power supply voltage VCC, the other end of the first current source Itot is connected with the power supply voltage VCC, the current output end of each phase inverter is connected with one end of a third current source I1, the other end of the third current source I1 is grounded GND, and the output end of the last phase inverter outputs oscillator clock pulse OSC _ CLK; a mos tube is connected between every two adjacent inverters, a first mos tube nm0 is connected between the odd-numbered inverters and the even-numbered inverters, the drain electrode of the first mos tube nm0 is connected with the output end of the odd-numbered inverters, the source electrode of the first mos tube nm0 is grounded GND, the gate electrode of the first mos tube nm0 is connected with an enable signal enb, a second mos tube pm0 is connected between the even-numbered inverters and the odd-numbered inverters, the drain electrode of the second mos tube pm0 is connected with a power supply voltage VCC, the source electrode of the second mos tube pm0 is connected with the output end of the even-numbered inverters, the gate electrode of the second mos tube pm0 is connected with an enable signal en, and the enable signal enb is the opposite phase of the enable signal en;

the second current source I0 is a third mos tube pm1, the inverter comprises a fourth mos tube pm2 and a fifth mos tube nm1, the third current source I1 is a sixth mos tube nm2, the oscillator circuit further comprises a seventh mos tube nm3, an eighth mos tube nm4 and a ninth mos tube pm3, the drain and the gate of the seventh mos tube nm3 are connected together and then connected with the other end of the first current source Itot, the source of the seventh mos tube nm3 is grounded, the gate and the drain of the eighth mos tube nm4 are connected together and then connected with the gate of the seventh mos tube nm3, the source of the eighth mos tube 4 is grounded, the drain of the eighth mos tube nm4 is connected with the source of the ninth mos tube pm3, the drain of the ninth mos tube 3 is connected with the drain of the third mos tube 1, the drain of the third mos tube I59628 is connected together with the gate of the third mos tube pm, the drain of the ninth mos tube nm4 is connected with the drain of the ninth mos tube pm, the fourth mos tube pm is connected with the drain of the ninth mos tube 8653, the drain of the ninth mos tube 8653 and the fourth mos tube 86 2, the source electrode of the fifth mos tube nm1 is connected with the drain electrode of the sixth mos tube nm2, the source electrode of the sixth mos tube nm2 is grounded, the grid electrode of the fourth mos tube pm2 and the grid electrode of the fifth mos tube nm1 are connected together to output oscillator clock pulse OSC _ CLK, and the source electrode of the fourth mos tube pm2 and the drain electrode of the fifth mos tube nm1 are connected together to be connected with the drain electrode of the first mos tube nm 0/the source electrode of the second mos tube pm 0; the grid electrode and the drain electrode of the sixth mos transistor nm2 are connected together and then connected with the grid electrode of the eighth mos transistor nm 4.

The oscillator circuit, wherein the first mos transistor nm0 is an nmos transistor.

The oscillator circuit described above, wherein said second mos transistor pm0 is a pmos transistor.

In the oscillator circuit, the third mos tube pm1 and the fourth mos tube pm2 are pmos tubes, and the fifth mos tube nm1 and the sixth mos tube nm2 are nmos tubes.

The oscillator circuit, wherein the seventh mos transistor nm3 and the eighth mos transistor nm4 are nmos transistors, and the ninth mos transistor pm3 is a pmos transistor.

The oscillator circuit described above, wherein 5 inverters are provided.

The oscillator circuit is characterized in that a first mos transistor nm0 is arranged between a first inverter and a second inverter, a second mos transistor pm0 is arranged between the second inverter and a third inverter, a first mos transistor nm0 is arranged between the third inverter and a fourth inverter, and a second mos transistor pm0 is arranged between the fourth inverter and a fifth inverter.

A flash chip comprising an oscillator circuit as claimed in any preceding claim.

The invention has the beneficial effects that: according to the oscillator circuit and the flash chip, the oscillator circuit is simple in structural connection, when the enabling signal is 0, the first mos tube and the second mos tube are both conducted, the clock pulse of the oscillator is always kept at a low level, but the current of the oscillator is not turned off, so that the whole oscillator circuit can rapidly oscillate to a stable state when the enabling signal returns to a high level again; the area of the flash chip is reduced as much as possible, and the requirement of the oscillator circuit on quick oscillation stability is met.

Drawings

Fig. 1 is a signal waveform diagram of an enable en and an oscillator clock OSC _ CLK in the related art.

Fig. 2 is a schematic diagram of an oscillator circuit according to the present invention.

Fig. 3 is a signal waveform diagram of enable en and oscillator clock OSC _ CLK in the present invention.

FIG. 4 is a circuit diagram of an inverter according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

As shown in fig. 1, an oscillator circuit includes an odd number of inverters 1, the number of the inverters 1 is at least 3, an input terminal of a first inverter 1 is connected to an output terminal of a last inverter 1, and an output terminal of a previous inverter 1 is connected to an input terminal of a next inverter 1 between the first inverter 1 and the last inverter 1; the current input end of each inverter 1 is connected with one end of a second current source I0, the other end of the second current source I0 is connected with one end of a first current source Itot, the other end of the second current source I0 is connected with a power supply voltage VCC, the other end of the first current source Itot is connected with the power supply voltage VCC, the current output end of each inverter 1 is connected with one end of a third current source I1, the other end of the third current source I1 is grounded GND, and the output end of the last inverter 1 outputs oscillator clock pulse OSC _ CLK; a mos tube is connected between every two adjacent inverters 1, a first mos tube nm0 is connected between the odd inverters 1 and the even inverters 1, the drain electrode of the first mos tube nm0 is connected with the output end of the odd inverters 1, the source electrode of the first mos tube nm0 is grounded GND, the gate electrode of the first mos tube nm0 is connected with an enable signal enb, a second mos tube pm0 is connected between the even inverters 1 and the odd inverters 1, the drain electrode of the second mos tube pm0 is connected with a power supply voltage VCC, the source electrode of the second mos tube pm0 is connected with the output end of the even inverters 1, the gate electrode of the second mos tube pm0 is connected with an enable signal en, and the enable signal enb is the opposite phase of the enable signal en.

In certain embodiments, the first mos tube nm0 is an nmos tube and the second mos tube pm0 is a pmos tube.

In some embodiments, as shown in fig. 4, the second current source I0 is a third mos tube pm1, the inverter 1 includes a fourth mos tube pm2 and a fifth mos tube nm1, the third current source I1 is a sixth mos tube nm2, the oscillator circuit further includes a seventh mos tube nm3, an eighth mos tube nm4 and a ninth mos tube pm3, a drain and a gate of the seventh mos tube nm3 are connected together and then connected to the other end of the first current source Itot, a source of the seventh mos tube nm 63 3 is grounded, a gate and a drain of the eighth mos tube nm4 are connected together and then connected to the gate of the seventh mos tube nm3, a source of the eighth mos tube nm4 is grounded, a drain of the eighth mos tube nm4 is connected to the source of the ninth mos tube pm3, a drain of the ninth mos tube 3 is connected to the drain of the third mos tube 1, a drain of the third mos tube I5848 and a drain of the ninth mos tube are connected together and then connected to the source of the ninth mos tube pm 465, a source electrode of a fourth mos tube pm2 is connected with a drain electrode of a fifth mos tube nm1, a source electrode of a fifth mos tube nm1 is connected with a drain electrode of a sixth mos tube nm2, a source electrode of the sixth mos tube nm2 is grounded, a grid electrode of the fourth mos tube pm2 and a grid electrode of a fifth mos tube nm1 are connected together and then output an oscillator clock pulse OSC _ CLK, and a source electrode of the fourth mos tube pm2 and a drain electrode of the fifth mos tube nm1 are connected together and then are connected with a drain electrode of the first mos tube nm 0/a source electrode of the second mos tube pm 0; the grid electrode and the drain electrode of the sixth mos transistor nm2 are connected together and then connected with the grid electrode of the eighth mos transistor nm 4.

In certain embodiments, the third mos tube pm1, fourth mos tube pm2 are pmos tubes, and fifth mos tube nm1, sixth mos tube nm2 are nmos tubes.

In certain embodiments, the seventh mos tube nm3, eighth mos tube nm4 are nmos tubes, and ninth mos tube pm3 is a pmos tube.

Wherein, the inverter 1 can be provided with 3, 5, 7, etc. according to the requirement. In this embodiment, the number of the inverters 1 is 5, namely, a first inverter, a second inverter, a third inverter, a fourth inverter and a fifth inverter, a first mos transistor nm0 is arranged between the first inverter and the second inverter, a second mos transistor pm0 is arranged between the second inverter and the third inverter, a first mos transistor nm0 is arranged between the third inverter and the fourth inverter, and a second mos transistor pm0 is arranged between the fourth inverter and the fifth inverter.

The working principle of the oscillator circuit is as follows: when the enable signal en =1, the entire oscillator circuit normally operates; when the enable signal en =0, enb =1, the first mos transistor nm0 and the second mos transistor pm0 are both turned on, points a and c are respectively pulled down to GND, points b and d are respectively pulled up to the power supply voltage VCC, the oscillator clock pulse OSC _ CLK is always kept at a low level, but the current is not turned off; therefore, when the enable signal en returns to the high level again, the entire oscillator circuit can rapidly oscillate to a stable state, where the signal waveforms of the enable signal en and the oscillator clock pulse OSC _ CLK are as shown in fig. 3.

The technical scheme also protects a flash chip which comprises the oscillator circuit.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.