阅读说明：本技术 具有冷源极的金属氧化物半导体场效应晶体管 (Metal oxide semiconductor field effect transistor with cold source ) 是由 刘飞 王健 郭鸿 于 2019-06-06 设计创作，主要内容包括：提供一种金属氧化物半导体场效应晶体管(MOSFET)器件。所述器件包括：衬底；在所述衬底上的氧化物层；在所述氧化物层上的栅极；在所述衬底上的源极和漏极,其中所述源极和所述漏极掺杂有第一类型的掺杂剂；以及耦合到所述源极的冷源极,其中所述冷源极包括结,所述结在掺杂有第二类型的掺杂剂的半导体与从由金属和半金属组成的群组中选择的材料之间。(A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device is provided. The device comprises: a substrate; an oxide layer on the substrate; a gate electrode on the oxide layer; a source and a drain on the substrate, wherein the source and the drain are doped with a first type of dopant; and a cold source coupled to the source, wherein the cold source comprises a junction between a semiconductor doped with a second type of dopant and a material selected from the group consisting of a metal and a semi-metal.)

1. A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device, comprising:

a substrate;

an oxide layer on the substrate;

a gate electrode on the oxide layer;

a source and a drain on the substrate, wherein the source and the drain are doped with a first type of dopant; and

a cold source coupled to the source, wherein the cold source comprises a junction between a semiconductor doped with a second type of dopant and a material selected from the group consisting of a metal and a semi-metal.

2. The MOSFET device of claim 1, wherein the semiconductor of the cold source comprises a p-type semiconductor coupled to the metal to form the junction.

3. The MOSFET device of claim 1, wherein the semiconductor of the cold source comprises a pocket doped region.

4. The MOSFET device of claim 1, wherein the material is selected from the group consisting of aluminum, platinum, palladium, cobalt, ruthenium, silver, graphene, and two-dimensional layered metals.

5. The MOSFET device of claim 1, wherein the dopant of the first type comprises an n-type dopant and the dopant of the second type comprises a p-type dopant.

6. The MOSFET device of claim 1, wherein the dopant of the first type comprises a p-type dopant and the dopant of the second type comprises an n-type dopant.

7. The MOSFET device of claim 1, wherein the MOSFET device is configured to have a sub-threshold swing of less than 60 mV/decade at room temperature.

8. The MOSFET device of claim 7, wherein the MOSFET device is configured to have a subthreshold swing between 23 mV/decade and 60 mV/decade.

9. The MOSFET device of claim 1, wherein the heat sink is configured to provide an energy band gap in the source to suppress a thermal tail.

10. The MOSFET device of claim 9, wherein the cold source is configured to inject cold carriers having a distribution that does not actively extend into the hot tail.

11. A method of fabricating a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device, the method comprising:

providing a substrate;

providing an oxide layer on the substrate;

forming a gate on the oxide layer;

forming a source and a drain on the substrate, wherein the source and the drain are doped with a first type of dopant; and

forming a cold source coupled to the source, wherein the cold source comprises a junction between a semiconductor doped with a second type of dopant and a material selected from the group consisting of a metal and a semi-metal.

12. The method of claim 11, wherein the semiconductor of the cold source comprises a p-type semiconductor coupled to the metal to form the junction.

13. The method of claim 11, wherein the semiconductor of the cold source comprises a pocket dopant region.

14. The method of claim 11, wherein the material is selected from the group consisting of aluminum, platinum, palladium, cobalt, ruthenium, silver, graphene, and two-dimensional layered metals.

15. The method of claim 11, wherein the dopant of the first type comprises an n-type dopant and the dopant of the second type comprises a p-type dopant.

16. The method of claim 11, wherein the dopant of the first type comprises a p-type dopant and the dopant of the second type comprises an n-type dopant.

17. The method of claim 11, wherein the MOSFET device is configured to have a sub-threshold swing of less than 60 mV/decade at room temperature.

18. The method of claim 17, wherein the MOSFET device is configured to have a subthreshold swing between 23 mV/decade and 60 mV/decade.

19. The method of claim 11, wherein the heat sink is configured to provide an energy band gap in the source to suppress a thermal tail.

20. The method of claim 19, wherein the cold source is configured to inject cold carriers having a distribution that does not actively extend into the thermal tail.

21. A Metal Oxide Semiconductor Field Effect Transistor (MOSFET), comprising:

a source region and a drain region of a first conductivity type;

a body region of a second conductivity type opposite to the first conductivity type between the source region and the drain region;

a gate separated from a channel region of the body region by an insulating layer; and

a cold source coupled to the source region, wherein the cold source is configured to provide an energy band gap in the source region to suppress a hot tail.

22. The MOSFET of claim 21, wherein the heat sink electrode is configured to inject cold carriers having a distribution that does not actively extend into the thermal tail.

23. The MOSFET according to claim 22, wherein the heat sink electrode comprises a junction between a semiconductor of the second conductivity type and a metal.

Technical Field

The technology discussed below relates generally to Metal Oxide Semiconductor Field Effect Transistor (MOSFET) circuits and, more particularly, to MOSFET circuits with low subthreshold swing.

Background

The scaling down of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) following moore's law has enabled information technology to continue to evolve for the past few decades. By reducing the channel length of the transistor, the switching speed becomes faster, the device density becomes higher, and the circuit is more powerful and efficient. However, the exponential increase in electronic device performance cannot last forever as predicted by moore's law. Among the problems faced by present day transistor technology, power consumption is a significant issue due to scaling limitations of the supply voltage. For example, the device principles of MOSFETs dictate that the sub-threshold swing (SS) at room temperature be limited to 60 mV/decade. This is a physical limitation of existing MOSFET designs regardless of the channel material and/or device structure. Such physical limits prevent further reduction in the supply voltage and power dissipation of the MOSFET device.

Ongoing research into new current switches other than MOSFETs, such as tunneling FETs (tfets) and negative capacitance FETs (NC-FETs), indicates a need to find device principles that enable transistors to be turned on and off without the 60 mV/decade SS limit while having a large on-current similar to that of a MOSFET. Recently, sub-60 mV/decade switches have been experimentally implemented and theoretically studied with injection of Dirac-like electrons at the source of the FET by exploiting the density of states (DOS) at the source of the transistor. Furthermore, by injecting electrons from graphene into carbon nanotubes, high on-state currents of orders of magnitude higher than today's best TFETs and sub-60 mV/decade switches can be achieved.

Disclosure of Invention

The present application proposes a new Field Effect Transistor (FET) with a Cold Source (CS) by introducing a metal/semi-metal between the p-type and n-type semiconductors. By engineering the state density of injected carriers (DOS) from such a cold source, efficient energy filtering of energetic electrons is achieved, and steep slope switching as small as about 23 mV/decade is achievable in the resulting CS-FET.

In one aspect, the present application provides a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device comprising: a substrate; an oxide layer on the substrate; a gate electrode on the oxide layer; a source and a drain on the substrate, wherein the source and the drain are doped with a first type of dopant; and a cold source coupled to the source, wherein the cold source comprises a junction between a semiconductor doped with a second type of dopant and a material selected from the group consisting of a metal and a semi-metal.

In another aspect, the present application provides a method of fabricating a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device, the method comprising: providing a substrate; providing an oxide layer on the substrate; forming a gate on the oxide layer; forming a source and a drain on the substrate, wherein the source and the drain are doped with a first type of dopant; and forming a cold source coupled to the source, wherein the cold source comprises a junction between a semiconductor doped with a second type of dopant and a material selected from the group consisting of a metal and a semi-metal.

In another aspect, the present application provides a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) comprising: a source region and a drain region of a first conductivity type; a body region of a second conductivity type opposite to the first conductivity type between the source region and the drain region; a gate separated from a channel region of the body region by an insulating layer; and a cold source coupled to the source region, wherein the cold source is configured to provide an energy band gap in the source region to suppress a hot tail.

Drawings

FIG. 1a is a graph comparing the operating mechanisms of a conventional FET and a Heat sink electrode FET (CS-FET), according to one aspect of the present disclosure.

FIG. 1b is a diagram illustrating two types of cold source poles according to some aspects of the present disclosure.

Fig. 1c is a conceptual diagram illustrating a silicon cold source pole FET according to one aspect of the present disclosure.

Fig. 1d is a diagram showing the atomic structure and band structure of a silicon film.

Fig. 2a is a diagram illustrating various energy band structures according to some aspects of the present disclosure.

Fig. 2b is a graph illustrating various current-voltage curves for different transistors according to some aspects of the present disclosure.

Fig. 2c is a conceptual diagram illustrating a cold source of a cold source pole FET with and without pocket doping (pocket doping), according to some aspects of the present disclosure.

Fig. 2d is a diagram illustrating an energy band edge profile of a cold source FET according to some aspects of the present disclosure.

Fig. 3a is a graph showing local state density along the channel of a silicon cold-source FET with pocket doping at a first gate voltage.

Fig. 3b is a graph showing local state density along the channel of a silicon cold-source FET with pocket doping at a second gate voltage.

Fig. 4a is a graph showing the subthreshold swing limit of an exemplary cold source FET as a function of the source bandgap at room temperature.

Fig. 4b is a graph showing the temperature effect on device current as a function of voltage for an exemplary cold source FET.

Fig. 4c is a graph comparing the sub-threshold swings of different FETs at a first gate voltage.

Fig. 4d is a graph comparing the sub-threshold swings of different FETs at the second gate voltage.

Detailed Description

The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts. Although aspects and embodiments are described herein through the illustration of some examples, those of ordinary skill in the art will appreciate that additional implementations and use cases may be generated in many different arrangements and scenarios.

Aspects of the present disclosure provide a novel Field Effect Transistor (FET) with a Cold Source (CS) by introducing a metal/semi-metal between a p-type and an n-type semiconductor (e.g., silicon). By engineering the state density of injected carriers (DOS) from such a cold source, efficient energy filtering of energetic electrons is achieved, and steep slope switching as small as about 23 mV/decade is achievable in the resulting CS-FET. In some examples, at the drain voltage (V)_D) Can achieve 7.4 multiplied by 10 under the condition of 0.5V²High on-current (I) of μ A/μm_on). The CS-FETs of the present disclosure have more desirable device performance for low power applications than FETs and tunneling FETs (tfets). In some examples, the heat sink pole may be implemented in various FET structures (e.g., finfets and fully depleted silicon-on-insulator (FD-SOI) FETs).

In a conventional n-type FET, carriers are injected from metal contacts (metal contacts) into the n-type semiconductor in the source, as shown in the top portion of fig. 1 a. The sub-threshold swing (SS) cannot be less than 60 mV/decade at room temperature due to the Fermi distribution of the thermionic carriers over the potential barrier. Unlike conventional FETs, the CS-FET of the present disclosure is designed by introducing a band gap in the source to suppress the thermal tail, as shown in the lower part of fig. 1 a. The cold source is configured to inject "cold" carriers into the FET. The distribution of "cold" carriers does not actively extend into the thermalized fermi tail in the off-state, since the tail is already cut off by the upper band gap, and thus the off-state current is greatly reduced. While thermionic carriers can be transported directly from source to drain in the on-state, as is the case with conventional FETs. Thus, such "cold" carriers are not limited to 60 mV/decade SS.

In some aspects of the present disclosure, the cold source may be implemented by using a type-III heterojunction or by a junction composed of a p-type semiconductor, a metal/semi-metal, and an n-type semiconductor, as schematically illustrated in fig. 1 b. Figure 1c conceptually illustrates an exemplary silicon CS-FET. In this example, p-type silicon 1002 and metal 1004 are applied between n-type silicon 1006 in the source 1008 of the CS-FET and metal contacts (not shown). Thus, carriers from the metal contact are injected first into the Valence Band (VB) of p-type silicon 1002 and then through metal 1004 into the Conduction Band (CB) of n-type silicon 1006. The CS-FET is thus a combined system of a heat sink pole 1008 and a FET, as shown in fig. 1 c. The same concept can be applied to p-type CS-FETs. In other embodiments, all suitable metals or semi-metals may be used to form the cold source. For example, aluminum, platinum, palladium, cobalt, ruthenium, silver, graphene, and two-dimensional layered metals may be placed between p-type and n-type semiconductors to form cold sources. In some examples, the two-dimensional layered metal may be 1T phase MoTe₂And WTE₂。

In one example, the electronic structure of a 1.6nm thick silicon film can be calculated using Density Functional Theory (DFT) (using Vienna Ab initio simulation package (VASP) or the like). The Heyd-Scuseria-Ernzerhof (HSE) mixing function, which is known to better describe the band gap of semiconductors, can be used to deal with the exchange dependence. In one example, a 1.6nm thick silicon film with wafer orientation in the (100) direction has a direct energy band gap of 1.48 eV, as shown in FIG. 1 d. The calculated electron affinity of the silicon film is 3.87 eV and the band offset between silicon and aluminum (Al) is 0.33 eV as schematically shown in the inset of fig. 1 d. The Valence Band Maximum (VBM) is anisotropic and has a lighter hole effective mass in the Y-direction shown in fig. 1 d.

In one example, to simplify device simulation, a quad band k p Hamiltonian may be constructed from the DFT results. Fig. 2a shows four low energy bands well described by the k p hamiltonian. Metal (e.g., aluminum) is approximately described by a four-band model with no gaps. By solving the schrodinger equation and the poisson equation in a non-equilibrium green-function (NEGF) formal system in a self-consistent manner, a simulation of transport properties in the Y direction with a lighter effective mass can be performed.

Illustrative examples and results

The calculated transfer characteristics of the CS-FET and silicon FETs, TFETs with double gates and 3 nm hafnium oxide layers are compared in fig. 2 b. In these examples, these devices have a gate length of 15 nm and source and drain of 20 nm. For CS-FETs, 3 nm p-type silicon and 3 nm metal (e.g., aluminum) are applied in the source to form the cold source. By pinning the VBM of p-type silicon to E_VBM=0.2 eV and fixes the Conduction Band Minimum (CBM) of n-type silicon at E_CBM=0.2 eV, the doping concentration can be modulated: 1.9X 10 for n-type and p-type silicon, respectively¹⁹ cm ^-3And 1.9X 10²⁰ cm ^-3. At gate voltage (V)_G) Off-state current of 10 pA/μm was calibrated according to the International Technology Roadmap for Semiconductors (ITRS) for low power applications at = 0V, as shown in fig. 2 b. An exemplary silicon FET has good gate control in the subthreshold region, and SS can be as low as 60 mV/decade. The on-state current of the silicon FET is 4.8X 10²μ A/μm, which is still lower than the requirements of ITRS 2013 for low power applications, e.g., the requirements of ITRS 2013 for low power applications are at the gate length (L)_G) =15 nm and V_DAbout 5.6 × 10 at 0.78V²μ A/. mu.m. In contrast, the SS of a silicon-TFET is at about V_GCan reach 31 mV/deca under the condition of 0Vde, at V_GI under 0.5V_onIs 49 μ A/μm, which is larger than I of silicon FET_onIs small.

Silicon CS-FETs, on the other hand, have greatly improved switching properties, as shown in the example of fig. 2 b. In one example, SS is at-0.02V < V_GLess than 21 mV/decade under 0.08V. In one aspect of the present disclosure, to improve on-state current, 2 nm pocket doping (shown as regions 2002 and 2004 in fig. 2 c) may be applied in p-type and n-type silicon, as conceptually illustrated in fig. 2 c. In this example, the pocket doping is located near or adjacent to the metal. Fig. 2d shows that the tunneling length of the schottky contact is greatly reduced by using pocket doping. Thus, at V_GI at =0.5V_onBy pocket doping from 1.4X 10²The ratio of muA to mum increases to 7.4X 10²μ A/μm, which is greater than I of silicon FET_onAnd is 1.3 times the requirements of ITRS 2013. To understand the steep switch, V is compared in FIGS. 3a and 3b_GLocal state density (LDOS) of silicon CS-FETs with pocket doping at 0.02V and 0.12V. It can be seen that the top of the channel barrier is at V_GAnd the voltage is higher than the source VBM under the condition of-0.03V. Therefore, carriers have to tunnel through the barrier and the current consists of a direct tunneling current from the source VB to the drain CB, as shown in fig. 3 a. When the gate voltage is increased to 0.07V, the barrier top moves to a lower energy and becomes smaller than the source VBM. Thus, carriers can tunnel through the barrier and also be transported over the barrier from the source VB to the drain. The calculated current was found to be mainly contributed by electrons crossing the barrier (at around 93%). Since the top of the barrier is lower than the source VBM, the operating mechanism of the CS-FET in the on-state is the same as that of the MOSFET.

The current through a transistor can be described by the Landauer-B ü ttiker formula:

where q is the electron charge, h is the Planck constant, E is the energy, D (E) is the density of states of the transistor sourceT (E) is the transmission probability, and f_S/DIs the fermi function of the source/drain. For TFET, sub-60 mV/decade switching is achieved by modulating the transmission probability T (E). For CS-FETs, sub-60 mV/decade switching is achieved by introducing a gap in the source. That is, the switching process modulates the alignment between the source VBM and the top of the channel barrier. When the top of the potential barrier is below the source VBM, the tunneling current in the off-state is switched to thermionic current. The on-state current is determined by the "cold" source and can be as large as the on-state current in the MOSFET after optimizing the injected "cold" carriers. From equation (1) above, in the case of t (E) =1 (i.e., thermionic current over barrier), the SS limit as a function of the source bandgap can be calculated, and at bandgap E_G = 6 k_BThe SS limit at T may be as small as 1 mV/decade, as shown in FIG. 4 (a). I for a silicon CS-FET with pocket doping is shown in FIG. 4 (b)_D-V_GThe temperature of (c). Since the sub-60 mV/decade switch of a CS-FET can be achieved by modulating thermionic current, the current in the gate voltage region decreases with temperature at the sub-60 mV/decade switch.

FIGS. 4c and 4d compare SS to I for three FETs (silicon FET, CS-FET with pocket doping, and TFET)_on. SS and I_onCan pass through a voltage window V with a fixed voltage_DI of (A)_D-V_GAnd (4) curve plotting to obtain. In general, when I_onWhen increased, SS decreases (increases). For TFET, SS may break the 60 mV/decade thermal limit (as shown in FIG. 4 c), while I is 60 mV/decade for average SS_onIs about 1.7. mu.A/. mu.m. For silicon FETs, SS is higher than 60 mV/decade, but greater I can be achieved_on. For a CS-FET, FIG. 4c is shown at 1 × 10²μ A/. mu.m of_onThe average SS in the case of (2) is as small as 37 mV/decade. At SS =60 mV/decade, I_onTo about 7.1 × 10²μ A/. mu.m. Referring to FIG. 4d, when V_DI of CS-FET at SS =60 mV/decade when scaled to 0.3V_onAbout 2.0X 102. mu.A/. mu.m, this I_onMoving p-type silicon VBM to EVBM = 0.1V by using lower doping concentrationBut can be enhanced to 4.7 x 10²μ A/. mu.m. In I_on/ I _offRatio higher than 10⁷At E_VBMIn the case of = 0.1V, 3.2 × 10 is realized in a silicon CS-FET²μ A/. mu.m of_on。

The device described above uses only one semiconductor (e.g., silicon) as the channel material, without integrating two different semiconductors. In other aspects of the disclosure, both n-type and p-type devices may be achieved by varying the doping profile. The described CS-FET device is highly compatible with modern CMOS technology and introduces a junction of p-type silicon and metal in the source of a conventional n-type device.

Silicon FETs with "cold" sources using p-type semiconductors are described and studied by quantum transport calculations. It is demonstrated that SS as small as 23 mV/decade can be achieved in CS-FETs. In the proposed device, the transport channel is defined between the VBM of p-type silicon and the CBM of n-type silicon, and the off-state current is significantly suppressed. At the same time, a suitable metal is applied in the source to connect the p-type silicon and the n-type silicon, and in the on-state the carriers can be transported directly from the source to the drain without tunneling. Thus, in some examples, at V_DAt 0.5V, in the case of SS less than 60 mV/decade, I_onMay be greater than 10³μ A/. mu.m. Silicon CS-FETs may be used for low power applications. However, the principles of CS-FETs are general and applicable to other material systems.

Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object a physically touches object B, and object B touches object C, objects a and C may still be considered coupled to each other-even if they do not directly physically touch each other. For example, a first object may be coupled to a second object even though the first object is never in direct physical contact with the second object. The terms "circuit" and "circuitry" are used broadly and are intended to include both hardware implementations of electrical devices and conductors that when connected and configured enable the functions described in this disclosure to be performed, without limitation as to the type of electronic circuitry, and software implementations of information and instructions that when executed by a processor enable the functions described in this disclosure to be performed.

One or more of the components, steps, features and/or functions illustrated in figures 1 (a) -4 (d) may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps or functions. Additional elements, components, steps, and/or functions may also be added without departing from the novel features disclosed herein. The devices, means, and/or components shown in fig. 1 (a) -4 (d) may be configured to perform one or more of the methods, features, or steps described herein. The novel algorithms described herein may also be efficiently implemented in software and/or embedded in hardware.

It is understood that the specific order or hierarchy of steps in the methods disclosed is an illustration of exemplary processes. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the methods may be rearranged. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented unless specifically recited herein.

The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean "one and only one" (unless specifically so stated), but rather "one or more. The term "some" means one or more unless specifically stated otherwise. A phrase referring to "at least one of a list of items refers to any combination of those items, including a single member. By way of example, "at least one of a, b, or c" is intended to cover: a; b; c; a and b; a and c; b and c and a, b and c. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Furthermore, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the 35 u.s.c. § 112 (f) unless the element is explicitly recited using the phrase "means for …", or in the case of the method claims, the element is recited using the phrase "step for …".