阅读说明：本技术 显示装置及其制造方法 (Display device and method for manufacturing the same ) 是由 山口阳平 于 2019-07-09 设计创作，主要内容包括：用于控制图像显示的薄膜晶体管(TR)为底栅型,且具有栅电极(18)、覆盖栅电极(18)的绝缘膜(40)、位于绝缘膜(40)之上的氧化物半导体层(30)、与氧化物半导体层(30)的第1上表面区域(R1)接触的氧化剂层(42)、与氧化物半导体层(30)的第2上表面区域(R2)接触的还原剂层(44)、和位于绝缘膜(40)的上方的源电极及漏电极(20、24)。第2上表面区域(R2)在源电极与漏电极(20、24)之间的方向上与第1上表面区域(R1)的两侧中的各自分别邻接。氧化物半导体层(30)包含氧化剂层(42)紧下的半导体部(62)和还原剂层(44)紧下的导电部(64)。(A thin film Transistor (TR) for controlling image display is of a bottom gate type, and has a gate electrode (18), an insulating film (40) covering the gate electrode (18), an oxide semiconductor layer (30) located on the insulating film (40), an oxidizing agent layer (42) in contact with a 1 st upper surface region (R1) of the oxide semiconductor layer (30), a reducing agent layer (44) in contact with a 2 nd upper surface region (R2) of the oxide semiconductor layer (30), and source and drain electrodes (20, 24) located above the insulating film (40). The 2 nd upper surface region (R2) is adjacent to each of both sides of the 1 st upper surface region (R1) in a direction between the source and drain electrodes (20, 24). The oxide semiconductor layer (30) includes a semiconductor section (62) immediately below the oxidizing agent layer (42) and a conductive section (64) immediately below the reducing agent layer (44).)

1. A display device having a plurality of thin film transistors for controlling image display,

each of the plurality of thin film transistors is of a bottom gate type, and has:

a gate electrode;

a gate insulating film covering the gate electrode;

an oxide semiconductor layer over the gate insulating film;

silicon oxide in contact with a 1 st upper surface region of the oxide semiconductor layer;

silicon nitride in contact with the 2 nd upper surface region of the oxide semiconductor layer; and

a source electrode and a drain electrode located above the gate insulating film,

the 2 nd upper surface area is respectively adjacent to each of both sides of the 1 st upper surface area in a direction between the source electrode and the drain electrode,

the oxide semiconductor layer includes a semiconductor portion immediately below the silicon oxide and a conductive portion immediately below the silicon nitride.

2. The display device according to claim 1,

the silicon oxide is an oxidant layer, and the silicon oxide is a silicon oxide,

the silicon nitride is a reducing agent layer containing hydrogen.

3. The display device according to claim 1,

the oxide semiconductor layer has a pair of No. 3 upper surface regions sandwiching the No. 1 upper surface region and the No. 2 upper surface region,

the source electrode and the drain electrode are electrically connected to the pair of 3 rd upper surface regions, respectively.

4. The display device according to claim 3,

the source electrode and the drain electrode are respectively in contact with the pair of 3 rd upper surface regions and are placed on the pair of 3 rd upper surface regions.

5. The display device according to claim 4,

the source electrode and the drain electrode are formed of a metal,

the oxide semiconductor layer is reduced by the metal in the pair of 3 rd upper surface regions.

6. The display device according to claim 3,

the source electrode and the drain electrode are located so as not to overlap with the oxide semiconductor layer,

the display device further includes a pair of metal layers which are respectively placed in contact with the pair of 3 rd upper surface regions and placed on the pair of 3 rd upper surface regions, and which are respectively placed in contact with the source electrode and the drain electrode and placed on the source electrode and the drain electrode.

7. The display device according to claim 6,

the oxide semiconductor layer is reduced by the metal layer in the pair of 3 rd upper surface regions.

8. The display device according to any one of claims 1 to 7,

the 1 st upper surface region includes a plurality of 1 st upper surface regions separated from each other in the direction between the source electrode and the drain electrode,

a portion of the 2 nd upper surface region is located between the plurality of 1 st upper surface regions.

9. The display device according to any one of claims 1 to 7,

the silicon oxide is also placed on the source electrode and the drain electrode.

10. The display device according to claim 9,

the silicon nitride is also placed on the silicon oxide.

11. The display device according to any one of claims 1 to 7,

the gate electrode does not overlap with any of the source electrode and the drain electrode.

12. A method for manufacturing a display device, comprising the steps of:

forming a gate electrode;

forming a gate insulating film so as to cover the gate electrode;

forming an oxide semiconductor layer over the gate insulating film;

forming a source electrode and a drain electrode so as to avoid a 1 st upper surface region and a 2 nd upper surface region of the oxide semiconductor layer by film formation and etching over the oxide semiconductor layer;

forming an oxide layer in contact with the 1 st upper surface region of the oxide semiconductor layer, and oxidizing the oxide semiconductor layer in the 1 st upper surface region; and

forming a reducing agent layer so as to be in contact with the 2 nd upper surface region of the oxide semiconductor layer, and reducing the oxide semiconductor layer in the 2 nd upper surface region,

in the manufacturing method, the 2 nd upper surface region is adjacent to each of both sides of the 1 st upper surface region in a direction between the source electrode and the drain electrode, respectively.

13. The method for manufacturing a display device according to claim 12,

the etching is performed using a chlorine-based gas.

14. The method for manufacturing a display device according to claim 12,

the forming of the oxidant layer includes dry etching using a fluorine-based gas.

15. The method for manufacturing a display device according to claim 12,

in the step of forming the oxidizing agent layer, the oxidizing agent layer is formed so as to be further placed on the source electrode and the drain electrode.

16. The method for manufacturing a display device according to claim 15,

in the step of forming the reducing agent layer, the reducing agent layer is formed so as to be further placed on the oxidizing agent layer.

17. The method for manufacturing a display device according to any one of claims 12 to 16,

the source electrode and the drain electrode are formed so as to avoid overlapping with the oxide semiconductor layer,

forming the oxidizing agent layer and the reducing agent layer so as to avoid a pair of 3 rd upper surface regions, the pair of 3 rd upper surface regions sandwiching the 1 st upper surface region and the 2 nd upper surface region,

the method for manufacturing a display device further includes a step of forming a pair of metal layers so as to be placed on the pair of 3 rd upper surface regions in contact with the pair of 3 rd upper surface regions, respectively, and so as to be placed on the source electrode and the drain electrode in contact with the source electrode and the drain electrode, respectively.

Technical Field

The invention relates to a display device and a method of manufacturing the same.

Background

A Thin Film Transistor (TFT) using low-temperature polysilicon is used for an organic electroluminescent display and a high-definition liquid crystal display because of its high driving capability and high carrier mobility, but has a high off-current and is difficult to suppress leakage current. Therefore, in recent years, TFTs using an oxide semiconductor have been developed (patent documents 1 and 2).

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open publication No. 2016 + 100521

Patent document 2: japanese patent laid-open publication No. 2012-104639

Disclosure of Invention

Problems to be solved by the invention

In a bottom gate TFT, a metal film is etched over a semiconductor layer to form a source electrode and a drain electrode. Since the etching selectivity of metal to semiconductor is small, chlorine gas, which is used in a large amount in etching metal, causes unnecessary etching of the semiconductor layer. In particular, the thickness of the semiconductor layer is highly uneven in the portions adjacent to the source electrode and the drain electrode. The oxide semiconductor TFT has a low off-current, but has a low carrier mobility, and thus, the characteristics are greatly affected by the uneven film thickness.

The purpose of the present invention is to suppress unevenness in the film thickness of an oxide semiconductor layer.

Means for solving the problems

A display device according to the present invention includes a plurality of thin film transistors for controlling image display, each of the plurality of thin film transistors being of a bottom gate type and including: a gate electrode, a gate insulating film covering the gate electrode, an oxide semiconductor layer located over the gate insulating film, silicon oxide in contact with a 1 st upper surface region of the oxide semiconductor layer, silicon nitride in contact with a 2 nd upper surface region of the oxide semiconductor layer, and a source electrode and a drain electrode located above the gate insulating film, the 2 nd upper surface region being adjacent to each of both sides of the 1 st upper surface region in a direction between the source electrode and the drain electrode, respectively, the oxide semiconductor layer including a semiconductor portion immediately below the silicon oxide and a conductive portion immediately below the silicon nitride.

According to the present invention, the 2 nd upper surface area in contact with the reducing agent layer is respectively adjacent to each of both sides of the 1 st upper surface area in contact with the oxidizing agent layer. The semiconductor portion formed by oxidizing the 1 st upper surface region is not adjacent to the source electrode and the drain electrode. Therefore, the film thickness of the oxide semiconductor layer is prevented from being non-uniform in the portion adjacent to the 1 st upper surface region.

The method for manufacturing a display device according to the present invention includes the steps of: forming a gate electrode; forming a gate insulating film so as to cover the gate electrode; forming an oxide semiconductor layer over the gate insulating film; forming a source electrode and a drain electrode so as to avoid a 1 st upper surface region and a 2 nd upper surface region of the oxide semiconductor layer by film formation and etching over the oxide semiconductor layer; forming an oxide layer in contact with the 1 st upper surface region of the oxide semiconductor layer, and oxidizing the oxide semiconductor layer in the 1 st upper surface region; and forming a reducing agent layer so as to be in contact with the 2 nd upper surface region of the oxide semiconductor layer, and reducing the oxide semiconductor layer in the 2 nd upper surface region, in the manufacturing method, the 2 nd upper surface region is adjacent to each of both sides of the 1 st upper surface region in a direction between the source electrode and the drain electrode.

According to the present invention, the 2 nd upper surface area in contact with the reducing agent layer is respectively adjacent to each of both sides of the 1 st upper surface area in contact with the oxidizing agent layer. The 1 st upper surface area for oxidation by the oxidant layer is not adjacent to the source and drain electrodes. Therefore, in the portion adjacent to the 1 st upper surface region, the film thickness of the oxide semiconductor layer can be suppressed from being non-uniform due to etching.

Drawings

Fig. 1 is a plan view of a display device according to embodiment 1 of the present invention.

Fig. 2 is a circuit diagram of the display device.

Fig. 3 is a plan view showing the configuration of elements together with a pixel.

Fig. 4 is a schematic view showing a cross section of the display device shown in fig. 1.

Fig. 5 is a detailed sectional view of the thin film transistor.

Fig. 6 is a detailed top view of the thin film transistor.

Fig. 7 is a detailed cross-sectional view showing a thin film transistor of a display device according to a modification of embodiment 1.

Fig. 8 is a detailed cross-sectional view showing a thin film transistor of the display device of embodiment 2.

Fig. 9 is a detailed top view of the thin film transistor.

Fig. 10 is a detailed cross-sectional view showing a thin film transistor of the display device of embodiment 3.

Fig. 11 is a sectional view of the display device of embodiment 4.

Fig. 12 is a diagram showing an overall circuit of the display device.

Fig. 13 is a diagram showing a circuit configuration of the pixel shown in fig. 12.

Detailed Description

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be carried out in various ways without departing from the scope of the gist thereof, and the present invention is not to be construed as being limited to the description of the embodiments illustrated below.

In the drawings, the width, thickness, shape, and the like of each part are schematically shown as compared with the actual form in order to make the description more clear, but the present invention is not limited to the explanation. In the present specification and the drawings, the same reference numerals are given to elements having the same functions as those described with respect to the conventional drawings, and redundant description thereof may be omitted.

In the detailed description of the present invention, "at … …" and "at … …" when specifying the positional relationship between a certain component and another component include not only the case where the component is located immediately above or immediately below the certain component but also the case where another component is present therebetween unless otherwise specified.

[ embodiment 1 ]

Fig. 1 is a plan view of a display device according to embodiment 1 of the present invention. Since the display device is actually used while being bent, fig. 1 is an expanded view of the display device before being bent. The display device includes a display DP. The display DP has flexibility and is bent in a bending corresponding area BA located outside a display area DA where an image is displayed. An integrated circuit chip CP for driving an element for displaying an image is mounted on the display DP. A flexible printed board FP is connected to the display DP outside the display area DA. The display device is, for example, an organic electroluminescence display device. In the display area DA, for example, pixels (sub-pixels) of a plurality of colors consisting of red, green, and blue are combined to display a full-color image.

Fig. 2 is a circuit diagram of the display device. The circuit includes a plurality of scanning lines GL connected to the scanning circuit GD and a plurality of signal lines DL connected to the signal driving circuit SD. In the integrated circuit chip CP shown in fig. 1, a signal driving circuit SD is arranged. A region surrounded by 2 adjacent scanning lines GL and 2 adjacent signal lines DL is 1 pixel PX. The pixel PX includes a thin film transistor TR as a driving transistor, a switching element SW, and a holding capacitance Cs. When a gate voltage is applied to the scanning line GL, the switching element SW is turned ON (turned ON), and a video signal is supplied from the signal line DL to accumulate charges in the retention capacitor Cs. By accumulating the electric charge in the retention capacity Cs, the thin film transistor TR is turned ON, and a current flows from the power supply line PWL to the light emitting element OD. The light emitting element OD emits light by this current.

Fig. 3 is a plan view showing the configuration of elements together with a pixel. A part of the scanning line GL shown in fig. 2 is a gate electrode 10 of a switching element SW (e.g., a thin film transistor). A part of the signal line DL shown in fig. 2 is one source/drain electrode 12 (one of a source electrode and a drain electrode) of the switching element SW. The semiconductor layer 14 of the switching element SW is made of polysilicon as a main material. In addition, although the thin film transistor using low temperature polysilicon has high electron mobility, it has high off current and is difficult to suppress leakage current.

The other source/drain electrode 16 (the other of the source electrode and the drain electrode) of the switching element SW is connected to a gate electrode 18 of the thin film transistor TR. A part of the power supply line PWL is one source/drain electrode 20 (one of the source electrode and the drain electrode) of the thin film transistor TR.

The gate electrode 18 of the thin film transistor TR is connected to the 1 st capacitor electrode 22. The other source/drain electrode 24 (the other of the source electrode and the drain electrode) of the thin film transistor TR is connected to the 2 nd capacitor electrode 26. The 1 st capacitor electrode 22 and the 2 nd capacitor electrode 26 are opposed to each other, and constitute a holding capacitor Cs. The 2 nd capacitance electrode 26 is connected to the pixel electrode 28. The thin film transistor TR has an oxide semiconductor layer 30.

Fig. 4 is a schematic view showing a cross section of the display device shown in fig. 1. The substrate 32 is formed of polyimide. In addition, other resin materials may be used as long as the base material has sufficient flexibility to form a sheet-like display or a flexible display. A reinforcing film may be attached to the back surface of the substrate 32 via a pressure-sensitive adhesive.

An undercoat layer 34 is laminated on the substrate 32. The undercoat layer 34 includes a silicon oxide film 34a and a silicon oxide film 34 b. The lower silicon oxide film 34a is provided to improve adhesion to the substrate 32, and the upper silicon oxide film 34b is provided as a barrier film for preventing hydrogen atoms from diffusing into the semiconductor layer 14 of the switching element SW.

An additional film 36 for suppressing a characteristic change due to light entering from the back surface of the channel or imparting a back gate effect is disposed below the switching element SW. Here, after the silicon oxide film 34a is formed, the additional film 36 is formed in an island shape corresponding to the portion where the switching element SW is formed, and then the additional film 36 is enclosed in the base coat layer 34 by laminating the silicon oxide film 34b, but the present invention is not limited thereto, and the additional film 36 may be formed on the substrate 32 and then the base coat layer 34 may be formed.

The switching element SW is formed on the undercoat layer 34. In the case of a polysilicon thin film transistor, only the Nch transistor is shown here, but the Pch transistor may be formed at the same time. The semiconductor layer 14 of the switching element SW has a structure in which a low-concentration impurity region is provided between a channel region and a source/drain region. As the gate insulating film 38, a silicon oxide film is used here.

An insulating film 40 (a silicon oxide film and a silicon nitride film) is stacked on the gate electrode 10. Source/drain electrodes 12 and 16 are formed so as to penetrate insulating film 40. Here, a three-layer structure of Ti, Al, and Ti is used. The switching element SW is of a top gate type and has a gate electrode 10 above a semiconductor layer 14.

The gate electrode 18 of the thin film transistor TR is located at the same layer as the gate electrode 10 of the switching element SW. The insulating film 40 is an interlayer insulating film covering the gate electrode 10 of the switching element SW, and is also a gate insulating film of the thin film transistor TR. Above the gate electrode 18, an oxide semiconductor layer 30 is present. The oxide semiconductor layer 30 is formed over the insulating film 40. A pair of source/drain electrodes 20, 24 (source and drain electrodes) is also formed on the insulating film 40. The pair of source/drain electrodes 20 and 24 are also placed on the end portions of the oxide semiconductor layer 30.

The thin film transistor TR has the oxide semiconductor layer 30 as a channel region, and thus can reduce current fluctuation. The thin film transistor TR is located at a layer position above the switching element SW. Therefore, the thin film transistor TR is formed after the switching element SW, and thus is not affected by heat when the semiconductor layer 14 formed of low temperature polysilicon is formed. Details of the thin film transistor TR will be described later (see fig. 5).

The 1 st capacitance electrode 22 is also formed on the insulating film 40. An oxidizing agent layer 42 and a reducing agent layer 44 (described later in detail) are stacked so as to cover the thin film transistor TR and the 1 st capacitor electrode 22. The 2 nd capacitor electrode 26 is formed on the oxidizing agent layer 42 and the reducing agent layer 44. The oxidizing agent layer 42 and the reducing agent layer 44 serve as dielectrics of the holding capacitance Cs shown in fig. 2.

A planarization organic film 46 is provided so as to cover the reducing agent layer 44 and the 2 nd capacitor electrode 26. The flattening organic film 46 is made of a resin such as a photosensitive acrylic resin because it has superior surface flatness compared to an inorganic insulating material formed by CVD (Chemical Vapor Deposition) or the like.

The pixel electrode 28 is stacked on the planarization organic film 46. The pixel electrode 28 is a reflective electrode and has a three-layer structure of an indium zinc oxide film, an Ag film, and an indium zinc oxide film. Here, instead of the indium zinc oxide film, an indium tin oxide film may be used.

An insulating organic film 48 called a bank (rib) and serving as a partition wall of an adjacent pixel region is formed so as to be placed on the planarized organic film 46 and on the periphery of the pixel electrode 28. As the insulating organic film 48, a photosensitive acrylic resin or the like is used as in the case of the planarizing organic film 46. The insulating organic film 48 is opened so that the surface of the pixel electrode 28 is exposed as a light-emitting region, and preferably, the opening end thereof has a smooth tapered shape. If the opening end has a steep shape, the organic electroluminescent layer 50 formed thereon may be poorly covered.

An organic electroluminescent layer 50 formed of an organic material is stacked on the pixel electrode 28. The organic electroluminescent layer 50 may be a single layer, but may have a structure in which a hole transport layer, a light emitting layer, and an electron transport layer are stacked in this order from the pixel electrode 28 side. These layers may be formed by vapor deposition, by coating after solvent dispersion, selectively formed for the pixel electrode 28 (each sub-pixel), or formed to cover the entire surface of the display area DA. In the case of full-surface formation, white light is obtained in all the sub-pixels, and a desired color wavelength portion is extracted by a color filter (not shown).

An opposite electrode 52 is provided on the organic electroluminescent layer 50. Here, since the top emission structure is formed, the counter electrode 52 is transparent. For example, the Mg layer and the Ag layer are formed as thin films to such an extent that the outgoing light from the organic electroluminescent layer 50 can be transmitted. In the order of forming the organic electroluminescent layer 50, the pixel electrode 28 serves as an anode, and the counter electrode 52 serves as a cathode. The light-emitting element OD is constituted by the plurality of pixel electrodes 28, the counter electrode 52, and the organic electroluminescent layer 50 present between the central portion of each of the plurality of pixel electrodes 28 and the counter electrode 52.

A sealing layer 54 is formed on the counter electrode 52. One of the functions of the sealing layer 54 is to prevent moisture from entering the organic electroluminescent layer 50 formed in advance, and high gas barrier properties are required. The sealing layer 54 has a laminated structure of a sealing organic film 54b and a pair of sealing inorganic films 54a and 54c (e.g., silicon nitride films) sandwiching the sealing organic film 54b from above and below. The pair of sealing inorganic films 54a and 54c are overlapped with each other in contact with the periphery of the sealing organic film 54 b. For the purpose of improving the adhesion, a silicon oxide film or an amorphous silicon layer is provided between the sealing inorganic films 54a and 54c and the sealing organic film 54 b. A reinforcing organic film 56 is laminated on the sealing layer 54. A polarizing plate 60 is attached to the reinforcing organic film 56 through an adhesive layer 58. The polarizing plate 60 is, for example, a circular polarizing plate.

Fig. 5 is a detailed sectional view of the thin film transistor TR. Fig. 6 is a detailed plan view of the thin film transistor TR.

The display device has a plurality of thin film transistors TR for controlling image display. Each of the plurality of thin film transistors TR is of a bottom gate type. The thin film transistor TR has a gate electrode 18. The thin film transistor TR has an insulating film 40 covering the gate electrode 18. The thin film transistor TR has a pair of source/drain electrodes 20 and 24 (source and drain electrodes) located above the insulating film 40.

The thin film transistor TR has an oxide semiconductor layer 30 on an insulating film 40. The oxide semiconductor layer 30 is formed of, for example, indium/gallium/zinc/oxygen (IGZO; indium gallium zinc oxide). Such a thin film transistor TR has a characteristic of low off current.

The oxide semiconductor layer 30 has a 1 st upper surface region R1. The 1 st upper surface area R1 of the oxide semiconductor layer 30 is in contact with the oxidizer layer 42. The oxidant layer 42 has silicon oxide. The oxide semiconductor layer 30 includes a semiconductor portion 62 formed by oxidation from the 1 st upper surface region R1 from the oxidizing agent layer 42. The semiconductor portion 62 is oxidized to reduce electrons and exhibit semiconductivity, thereby enabling the transistor to operate. The oxidizing agent layer 42 is also placed on the pair of source/drain electrodes 20 and 24 (source and drain electrodes).

The oxide semiconductor layer 30 has a 2 nd upper surface area R2. The 2 nd upper surface region R2 is adjacent to each of both sides of the 1 st upper surface region R1 in the direction between the pair of source/drain electrodes 20, 24 (source and drain electrodes). The 2 nd upper surface region R2 of the oxide semiconductor layer 30 is in contact with the reducing agent layer 44. The reducing agent layer 44 has silicon nitride containing hydrogen. Hydrogen may be contained depending on film formation conditions, or silicon nitride may be originally contained. Hydrogen initiates a reduction reaction that draws oxygen out by bonding with oxygen. The oxide semiconductor layer 30 includes a conductive portion 64 which is reduced from the 2 nd upper surface region R2 by the reducing agent layer 44. The conductive portion 64 is reduced to remove oxygen, thereby increasing electrons as carriers to be a conductor. A reducing agent layer 44 is also disposed on the oxidizing agent layer 42.

The oxide semiconductor layer 30 has a pair of 3 rd upper surface regions R3 sandwiching the 1 st upper surface region R1 and the 2 nd upper surface region R2. The pair of source/drain electrodes 20 and 24 are placed in contact with the pair of 3 rd upper surface regions R3, respectively, and are electrically connected to the pair of 3 rd upper surface regions R3. The pair of source/drain electrodes 20, 24 is formed of metal. The oxide semiconductor layer 30 is reduced by the metal in the pair of No. 3 upper surface regions R3 to realize conductivity.

In the oxide semiconductor layer 30, the semiconductor portion 62 has a higher oxygen concentration and a lower hydrogen concentration than the conductive portion 64. Further, the conductive portion 64 has higher conductivity than the semiconductor portion 62. In addition, current is not substantially supplied to the oxide semiconductor layer 30 immediately below the 3 rd upper surface region R3, and conduction is mainly performed by the source/drain electrodes 20 and 24.

According to the present embodiment, 2 nd upper surface region R2 in contact with reducing agent layer 44 is adjacent to each of both sides of 1 st upper surface region R1 in contact with oxidizing agent layer 42. The semiconductor portion 62 oxidized from the 1 st upper surface region R1 is not adjacent to the pair of source/drain electrodes 20 and 24. Therefore, in the portion adjacent to the 1 st upper surface region R1, the variation in film thickness of the oxide semiconductor layer 30 is suppressed.

[ method for manufacturing display device ]

In the method of manufacturing the display device, as shown in fig. 5, the gate electrode 18 is formed. An insulating film 40 is formed so as to cover the gate electrode 18. An oxide semiconductor layer 30 is formed over the insulating film 40.

Through the formation of a metal film on the oxide semiconductor layer 30 and the etching thereof, the pair of source/drain electrodes 20 and 24 are formed so as to avoid the 1 st upper surface region R1 and the 2 nd upper surface region R2. The pair of source/drain electrodes 20 and 24 are formed of a metal, and are etched using a chlorine-based gas. When a chlorine-based gas is used, the etching rate of the metal is close to that of the semiconductor (oxide semiconductor). In addition, the semiconductor tends to have uneven film thickness in a portion adjacent to the etching mask. However, the 2 nd upper surface area R2 is adjacent to each of both sides of the 1 st upper surface area R1 in the direction between the pair of source/drain electrodes 20, 24, respectively. Therefore, the pair of source/drain electrodes 20 and 24 which become the etching mask of the oxide semiconductor layer 30 is separated from the 1 st upper surface region R1.

The oxidizer layer 42 is formed to be in contact with the 1 st upper surface region R1 and the 2 nd upper surface region R2 of the oxide semiconductor layer 30. The formation of the oxidizing agent layer 42 includes dry etching using a fluorine-based gas. When a fluorine-based gas is used, a high etching selectivity can be obtained because the etching rate of metal is different from that of a semiconductor (oxide semiconductor).

In the 1 st upper surface region R1 and the 2 nd upper surface region R2, the oxide semiconductor layer 30 is oxidized by the oxidizing agent layer 42. This results in the formation of a semiconductor portion 62 which exhibits semiconductivity by reducing electrons due to oxidation. The oxidizing agent layer 42 is also formed so as to be placed on the pair of source/drain electrodes 20 and 24.

The reducing agent layer 44 is formed in contact with the 2 nd upper surface region R2 of the oxide semiconductor layer 30. The reducing agent layer 44 is also formed to be placed on the oxidizing agent layer 42. In the 2 nd upper surface region R2, the oxide semiconductor layer 30 is reduced by the reducing agent layer 44.

According to the present embodiment, the 1 st upper surface region R1 for oxidation by the oxidant layer 42 is not adjacent to the pair of source/drain electrodes 20, 24. Therefore, in the portion adjacent to the 1 st upper surface region R1, the unevenness in the film thickness of the oxide semiconductor layer 30 due to etching is suppressed. In the semiconductor section 62, the film thickness is uniform, and thus the characteristics as a semiconductor are stable. Even if the film thickness of the conductive portion 64 is not uniform, the conductive portion is a portion formed into a conductor, and thus the characteristics of the thin film transistor TR are not significantly adversely affected.

[ modification of embodiment 1 ]

Fig. 7 is a detailed cross-sectional view showing a thin film transistor TR of a display device according to a modification of embodiment 1. In this example, the gate electrode 118 does not overlap the source/drain electrodes 120 and 124 (source and drain electrodes). This can reduce or eliminate the capacitance formed between the gate electrode 118 and the source/drain electrodes 120 and 124. The other contents correspond to those described in embodiment 1.

[ 2 nd embodiment ]

Fig. 8 is a detailed cross-sectional view showing the thin film transistor TR of the display device of embodiment 2. Fig. 9 is a detailed plan view of the thin film transistor TR.

In this embodiment mode, the pair of source/drain electrodes 220 and 224 (source and drain electrodes) is located so as not to overlap with the oxide semiconductor layer 230. That is, the source/drain electrodes 220 and 224 are not disposed on the oxide semiconductor layer 230. Therefore, the end portions of the source/drain electrodes 220, 224 do not exist over the oxide semiconductor layer 230. Instead, the pair of metal layers 266, 268 are respectively in contact with the pair of 3 rd upper surface regions R3 and are placed on the pair of 3 rd upper surface regions R3. The pair of metal layers 266 and 268 are in contact with the pair of source/drain electrodes 220 and 224, respectively, and are placed on the pair of source/drain electrodes 220 and 224. The oxide semiconductor layer 230 is reduced by the metal layers 266 and 268 in the pair of No. 3 upper surface regions R3 to realize conductivity.

In the method for manufacturing a display device of this embodiment mode, the pair of source/drain electrodes 220 and 224 is formed so as to avoid overlapping with the oxide semiconductor layer 230. That is, when the source/drain electrodes 220 and 224 are formed by etching the metal film, an etching mask, not shown, is disposed so as to cover the oxide semiconductor layer 230. Thereby, the oxide semiconductor layer 230 is not etched. In particular, when the end portion of the etching mask is placed on the oxide semiconductor layer 230, the film thickness is not uniform in the adjacent portion, but this can be avoided in this embodiment.

The oxidizing agent layer 242 and the reducing agent layer 244 are formed so as to avoid the pair of 3 rd upper surface regions R3 (which sandwich the 1 st upper surface region R1 and the 2 nd upper surface region R2). The pair of metal layers 266 and 268 are formed so as to be placed on the pair of 3 rd upper surface regions R3 in contact with the pair of 3 rd upper surface regions R3, respectively, and to be placed on the pair of source/drain electrodes 220 and 224 in contact with the pair of source/drain electrodes 220 and 224, respectively. The other contents correspond to those described in embodiment 1. Note that, when the pair of metal layers 266 and 268 and the 2 nd capacitor electrode 26 shown in fig. 4 are formed in the same layer, the formation can be performed without increasing the processing cost.

[ embodiment 3 ]

Fig. 10 is a detailed cross-sectional view showing the thin film transistor TR of the display device of embodiment 3.

In the present embodiment, there are a plurality of 1 st upper surface regions R1 separated from each other in the direction between the pair of source/drain electrodes 320, 324. An oxidant layer 342 is provided over each of the plurality of 1 st upper surface regions R1 so that the oxide semiconductor layer 330 is oxidized. Thus, the oxide semiconductor layer 330 includes a plurality of semiconductor portions 362 with a space therebetween. The semiconductor portion 362 exhibits semiconductivity by reducing electrons due to oxidation, and thus can operate as a transistor.

There is a portion of the 2 nd upper surface region R2 between the plurality of 1 st upper surface regions R1. Between the 1 st upper surface region R1 adjacent to each other, the reducing agent layer 344 is placed in the 2 nd upper surface region R2, whereby the oxide semiconductor layer 330 is reduced. Thus, the oxide semiconductor layer 330 includes the conductive portion 364 which is reduced from the 2 nd upper surface region R2 by the reducing agent layer 344. The conductive portion 364 is reduced to remove oxygen, thereby increasing electrons as carriers to be a conductor. The other contents correspond to those described in embodiment 1.

[ 4 th embodiment ]

Fig. 11 is a sectional view of the display device of embodiment 4. The display device is a liquid crystal display device.

The display device has a glass substrate 470. A primer layer 434 is formed over the glass substrate 470, and a thin film transistor TR is present on the primer layer 434. A pixel electrode 428 is connected to one source/drain electrode 420 or 424 (one of the source and drain electrodes) of the thin film transistor TR. A transverse electric field method is applied to drive the liquid crystal, and a common electrode 472 is disposed below the pixel electrode 428. With an insulating film 474 therebetween. A slit not shown is formed in the pixel electrode 428. The 1 st alignment film 476 is stacked so as to cover the plurality of pixel electrodes 428.

The display device has an opposite glass substrate 478. On the opposite glass substrate 478, a black matrix 480 and a color filter layer 482 are provided, and the lower side is covered with an overcoat layer (overcoat) 484. The 2 nd alignment film 486 is laminated so as to cover the overcoat layer 484. In the illustrated example, the black matrix 480 is disposed between the counter glass substrate 478 and the color filter layer 482, but may be disposed between the color filter layer 482 and the overcoat layer 484 or between the overcoat layer 484 and the 2 nd alignment film 486. A liquid crystal layer 488 exists between the 1 st alignment film 476 and the 2 nd alignment film 486. The cell gap (cell gap) is maintained by a plurality of spacers, not shown.

The display device has a backlight module 490 on the opposite side of the display surface on which an image is displayed. The backlight module 490 includes Light sources such as LEDs (Light Emitting diodes), a Light guide plate, an optical film, a diffuser plate, a reflector plate, and a frame. The point light source is converted into a surface light source through the light guide plate.

Fig. 12 is a diagram showing an overall circuit of the display device. The display device includes a display area DA for displaying an image and a peripheral area PA outside the display area DA. For example, the peripheral area PA has a frame-like shape surrounding the display area DA. The display device includes a plurality of pixels PX in a display area DA. The plurality of pixels PX are arranged in a matrix along the 1 st direction X and the 2 nd direction Y. In the present embodiment, 1 full-color pixel is constituted by 3 pixels PX adjacent to each other in the 1 st direction X.

The display device includes a plurality of scanning lines GL and a plurality of signal lines DL. The scanning lines GL extend in the 1 st direction X and are arranged at intervals in the 2 nd direction Y. The signal lines DL extend in the 2 nd direction Y and are arranged at intervals in the 1 st direction X. The scanning lines GL and the signal lines DL do not necessarily have to extend linearly, and a part thereof may be bent. The scanning line GL is connected to the scanning circuit GD. The signal line DL is connected to the signal driving circuit SD.

Fig. 13 is a diagram showing a circuit configuration of the pixel PX shown in fig. 12. The pixel PX includes a thin-film transistor TR disposed near a position where the scanning line GL and the signal line DL intersect. The thin film transistor TR is electrically connected to the scanning line GL and the signal line DL. The scanning line GL is connected to the thin film transistor TR of each pixel PX arranged in the 1 st direction X shown in fig. 12. The signal line DL is connected to the thin film transistor TR in each pixel PX arranged in the 2 nd direction Y shown in fig. 12.

The pixel electrode 428 is disposed in a region surrounded by the scanning line GL and the signal line DL. The thin film transistor TR is electrically connected to the pixel electrode 428. The pixel electrode 428 is opposite to the common electrode 472, and the liquid crystal layer 488 is driven by an electric field generated between the pixel electrode 428 and the common electrode 472. The common electrode 472 is connected to the common drive circuit CD shown in fig. 12 and is arranged over a plurality of pixels PX. Both ends of the holding capacitance Cs are electrically connected to the common electrode 472 and the pixel electrode 428.

The present invention is not limited to the above embodiments, and various modifications are possible. For example, the structure described in the embodiment can be replaced with a substantially similar structure, a structure that exhibits the same operational effects, or a structure that achieves the same object.