阅读说明：本技术 集成电路、集成电路系统的构造及形成阵列的方法 (Integrated circuit, structure of integrated circuit system and method for forming array ) 是由 G·卢加尼 K·B·坎贝尔 M·J·迪奇诺 A·W·弗雷兹 A·科甘 K·R·谢伊 于 2019-04-03 设计创作，主要内容包括：一种形成阵列的方法,其包括使用两种不同成分遮蔽材料形成具有彼此基本上相同的大小且彼此基本上相同的形状的间隔重复第一特征的图案。具有相较于所述第一特征的大小或形状不同的大小或不同的形状中的至少一者的图案中断第二特征在所述第一特征图案内且中断所述第一特征的图案。将所述第一特征的所述图案与所述图案中断第二特征平移到所述第一特征及所述图案中断第二特征下方的下衬底材料中。在所述平移期间或在所述平移之后中的至少一者移除所述下衬底材料上方的所述第一特征及所述图案中断第二特征的材料。在所述移除之后,使用所述下衬底材料中的所述图案中断第二特征作为估计所述两种不同成分遮蔽材料中的哪一者用于在所述下衬底材料上方的所述材料中的分析区中的所述第一特征之间留出第一空间或所述两种不同成分遮蔽材料中的哪一者用于在所述分析区中的所述第一特征之间留出与所述第一空间交替的第二空间的参考位置。揭示独立于方法的结构。(A method of forming an array comprising forming a pattern of spaced repeating first features having substantially the same size as each other and substantially the same shape as each other using two different compositions of masking material. A pattern having at least one of a different size or a different shape than a size or a shape of the first feature interrupts a pattern of second features within the pattern of first features and interrupts the first features. Translating the pattern of the first feature and the pattern break second feature into a lower substrate material below the first feature and the pattern break second feature. Removing material of the first feature and the pattern disrupting second feature over the underlying substrate material at least one of during or after the translating. After the removing, using the pattern interrupted second features in the underlying substrate material as a reference location to estimate which of the two different composition masking materials is used to leave first spaces between the first features in an analysis region in the material above the underlying substrate material or which of the two different composition masking materials is used to leave second spaces alternating with the first spaces between the first features in the analysis region. A method independent structure is disclosed.)

1. A method of forming an array, comprising:

forming a pattern of repeating first features with intervals of substantially the same size and substantially the same shape as each other, pattern discontinuities of at least one of different size or different shape as compared to the size or shape of the first features, and within and disrupting the pattern of the first features, using two different composition masking materials;

translating the pattern of the first feature and the pattern break second feature into a lower substrate material below the first feature and the pattern break second feature;

removing material of the first feature and the pattern disruption second feature over the underlying substrate material at least one of during or after the translating; and

after the removing, using the pattern interrupted second features in the underlying substrate material as a reference location to estimate which of the two different composition masking materials is used to leave first spaces between the first features in an analysis region in the material above the underlying substrate material or which of the two different composition masking materials is used to leave second spaces alternating with the first spaces between the first features in the analysis region.

2. The method of claim 1, wherein one of the two different compositions comprises a photoresist.

3. The method of claim 2, wherein the other of the two different compositions is devoid of photoresist.

4. The method of claim 1 wherein one of the two different compositions is deposited atop the other, and further comprising etching the one anisotropically from atop the other maskless.

5. The method of claim 1, wherein the first feature comprises longitudinally elongated and parallel lines.

6. The method of claim 5, wherein two laterally immediately adjacent ones of the lines have a longitudinal gap extending completely laterally across an individual one of the two laterally immediately adjacent lines and completely laterally between the two laterally immediately adjacent lines, the pattern interruption second feature comprising the longitudinal gap.

7. The method of claim 5 wherein two laterally adjacent ones of the lines have a longitudinal gap extending completely laterally across the respective ones of the two laterally adjacent lines and completely laterally between the two laterally adjacent lines, a lower substrate material bridge extending laterally between and interconnecting longitudinal ends of the two laterally adjacent lines at opposite longitudinal ends of the longitudinal gap, the pattern interruption second feature comprising the lower substrate material bridge.

8. The method of claim 1, wherein the first feature in the underlying substrate material comprises an opening in the underlying substrate material individually having a surrounding horizontal perimeter of the underlying substrate material.

9. The method of claim 8, wherein the pattern interrupted second features comprise openings in the underlying substrate material having a maximum straight-line horizontal extent greater than a maximum straight-line horizontal extent of individual ones of the openings of the first features.

10. The method of claim 1, wherein the translating comprises etching into the underlying substrate material.

11. A method of forming an array comprising a pattern, comprising:

forming longitudinally elongated and laterally spaced parallel mask lines comprising a photoimageable material, said mask lines comprising:

(a) the method comprises the following steps A mask bridge comprising the photoimageable material extending laterally between and interconnecting two laterally immediately adjacent ones of the mask lines, or

(b) The method comprises the following steps A longitudinal mask gap extending completely laterally across one of the mask lines;

forming sidewall masses of a different composition than a composition of the photoimageable material along opposing sidewalls of individual ones of the mask lines and along opposing sidewalls of the (a) or (b), immediately adjacent ones of the sidewall masses laterally between immediately adjacent ones of the individual mask lines having a first space therebetween;

removing the mask lines from between the sidewall blocks to form second spaces laterally alternating with the first spaces between the sidewall blocks; and

after removing the mask lines, using the sidewall blocks as a mask when etching into a lower substrate material below the sidewall blocks to form longitudinally elongated and parallel target lines having a third space laterally therebetween, two laterally adjacent ones of the target lines having a longitudinal target gap laterally across and laterally between respective ones of the two laterally adjacent target lines at least in part due to the (a) or (b) extending laterally completely across and laterally between the two laterally adjacent target lines, a lower substrate material bridge extending laterally between and interconnecting longitudinal ends of the two laterally adjacent target lines at opposite longitudinal ends of the longitudinal target gap.

12. The method of claim 11, wherein the mask line comprises (a).

13. The method of claim 11, wherein the mask line comprises (b).

14. The method of claim 11, comprising forming an electrically conductive material in the longitudinal target gap and along opposing sidewalls of the bridge of lower substrate material.

15. The method of claim 14, comprising:

stopping the etching; and

the target line, the longitudinal gap, and the lower substrate material bridge are translated deeper into the lower substrate material by a subsequent etch prior to forming the conductive material.

16. The method of claim 14, wherein the conductive material formed along the opposing sidewalls of the bridge of lower substrate material is formed to be dummy in a finished construction.

17. The method of claim 11, wherein:

the array comprises an analysis region laterally remote from the longitudinal target gap and the bridge of underlying substrate material, and the method further comprises:

removing the mask; and

after removing the mask, using one of the longitudinal target gaps or the underlying substrate material bridges as a reference location to estimate which of the third spaces in the analysis region originate from the first space or which of the third spaces originate from the second space.

18. The method of claim 17, wherein:

the array is formed on a substrate comprising a plurality of integrated circuit dies separated by dicing street regions, the analysis region being within at least one of the die regions, the longitudinal target gap and the bridge of lower substrate material being in the dicing street region; and is

The method further comprises:

cutting through the dicing street region to singulate the die region into individual integrated circuit dies.

19. The method of claim 17, wherein:

the array is formed on a substrate comprising a plurality of integrated circuit dies separated by dicing street regions, the analysis region is within at least one of the die regions, the longitudinal target gap and the lower substrate material bridge are in at least one of the die regions; and is

The method further comprises:

cutting through the dicing street region to singulate the die region into individual integrated circuit dies.

20. The method of claim 19, wherein the analysis region, the longitudinal target gap, and the lower substrate material bridge are in the same die region.

21. The method of claim 19, wherein the analysis region, the longitudinal target gap, and the lower substrate material bridge are in two different ones of the die regions.

22. The method of claim 11, comprising:

removing the mask including the sidewall blocks;

after removing the mask comprising the sidewall blocks, forming longitudinally elongated and laterally spaced parallel shading lines comprising photoimaging material over the target line, the shading lines being angled with respect to the target line, the shading lines comprising:

(c) the method comprises the following steps A shading bridge comprising the photoimageable material extending laterally between and interconnecting two laterally immediately adjacent ones of the shading lines, or

(d) The method comprises the following steps A longitudinal shield gap extending completely laterally across one of the shield lines;

forming side masses along opposing sidewalls of individual ones of the obscuration lines and along opposing sidewalls of the (c) or (d) having a composition different from that of the photoimaging material obscuration lines, immediately adjacent ones of the side masses laterally between immediately adjacent ones of the individual obscuration lines having a fourth space therebetween;

removing the masking lines from between the side blocks to form fifth spaces between the side blocks alternating laterally with the fourth spaces; and

after removing the masking lines, using the side blocks as a mask when etching into the underlying material to form longitudinally elongated and parallel calibration lines having a sixth space therebetween laterally, two laterally adjacent ones of the target lines having a longitudinal calibration gap therebetween laterally across respective ones of the two laterally adjacent calibration lines and laterally therebetween at least in part due to the (c) or (d) extending laterally completely, an interconnecting bridge extending laterally between and interconnecting longitudinal ends of the two laterally adjacent calibration lines at opposite longitudinal ends of the longitudinal calibration gap.

23. The method of claim 22, wherein:

the calibration line is in an analysis zone spaced from the longitudinal calibration gap and the interconnecting bridge, and the method further comprises:

removing the mask including the side blocks; and

after removing the mask comprising the side pieces, using one of the longitudinal target gap or the interconnecting bridge as a reference position for estimating which of the sixth spaces in the analysis zone originate from the fourth space or which of the sixth spaces originate from the fifth space.

24. The method of claim 22, wherein the etching into the lower sub-material using the side blocks as a mask forms at least one of the calibration lines in and laterally across the longitudinal target gap.

25. The method of claim 24, wherein the etching into the lower sub-material using the side blocks as a mask forms multiple of the calibration line in and laterally across the longitudinal target gap.

26. The method of claim 22, wherein the target line protrudes vertically relative to the calibration line.

27. The method of claim 26, wherein the calibration line and the target line comprise the same material.

28. The method of claim 22, wherein the forming in the lower substrate material using the side blocks as a mask when etching the lower sub-material forms openings individually having a surrounding horizontal perimeter of the lower substrate material.

29. The method of claim 28, wherein the etching into the target line uses the side blocks as a mask when etching the lower sub-material.

30. The method of claim 28, wherein the etching the lower sub-material forms at least one of the calibration lines in and laterally across the longitudinal target gap.

31. The method of claim 30, wherein the etching to the lower sub-material forms a plurality of the calibration lines in and laterally across the longitudinal target gap.

32. The method of claim 28, comprising:

the conductive material is formed in the following locations:

(e) the method comprises the following steps In the longitudinal target gap;

(f) the method comprises the following steps Along opposing sidewalls of the bridge of lower substrate material;

(g) the method comprises the following steps In the longitudinal indexing gap;

(h) the method comprises the following steps Along opposing sidewalls of the interconnect bridge; and

(j) the method comprises the following steps In the opening; and is

(e) The conductive material in (f), (g), and (h) is formed to be dummy in the finished construction.

33. The method of claim 32, comprising:

eliminating all of the conductive material in (e), (f), (g), and (h) owners; and

not eliminating all of the conductive material in (j) owners.

34. An integrated circuit, comprising:

an array of circuit operating features; and

at least one circuit-inoperable, electrically-conductive construct comprising:

two laterally spaced and parallel longitudinally elongated conductive lines, a longitudinal gap extending completely laterally across and between the two laterally spaced conductive lines, a conductive bridge extending laterally between longitudinal ends of the two laterally spaced conductive lines and interconnecting the longitudinal ends at opposite longitudinal ends of the longitudinal target gap.

35. An architecture for an integrated circuit system, comprising:

an array of first features of substantially the same size and substantially the same shape comprising conductive material and horizontally spaced from each other in horizontal rows and individually comprising surrounding horizontal perimeters of the conductive material; and

a second feature among the first array of features, the second feature comprising:

a bridge of non-conductive material extending completely between and across two immediately adjacent ones of the horizontal rows; and

conductor material all along opposite longitudinal sides of the bridge, the conductor material on each of the opposite longitudinal sides of the bridge having a maximum rectilinear horizontal extent greater than a maximum rectilinear horizontal extent of the conductive material of an individual one of the first features.

36. The construction of claim 35 wherein the bridge of non-conductive material extends completely between and across three immediately adjacent ones of the horizontal rows.

37. The construction of claim 35 comprising a plurality of the bridges.

Technical Field

Embodiments disclosed herein relate to integrated circuits, construction of integrated circuit systems, and methods of forming arrays.

Background

Memory is one type of integrated circuit system and is used in computer systems to store data. The memory may be fabricated as one or more arrays of individual memory cells. Memory cells can be written to or read from using a digit line (which can also be referred to as a bit line, a data line, or a sense line) and an access line (which can also be referred to as a word line). The digit lines can conductively interconnect memory cells along columns of the array, and the access lines can conductively interconnect memory cells along rows of the array. Each memory cell is uniquely addressed by a combination of a digit line and an access line.

The memory cells may be volatile, semi-volatile, or nonvolatile. The non-volatile memory cells may store data for extended periods of time in the absence of a power source. Non-volatile memory conventionally refers specifically to memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, the memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the state is considered to be either "0" or "1". In other systems, at least some individual memory cells may be configured to store information at more than two levels or states.

Capacitors are one type of electronic component that can be used in memory cells. The capacitor has two electrical conductors separated by an electrically insulating material. Energy may be stored electrostatically within this material as an electric field. That stored field will be volatile or non-volatile depending on the composition of the insulator material. For example, comprising SiO only₂The capacitor insulator material of (a) will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor having a ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by programmable materials having two stable polarization states and thereby may comprise capacitors and/or memory cells. The polarization state of the ferroelectric material can be changed by applying a suitable programming voltage and maintained (at least for a period of time) after the programming voltage is removed. Each polarization state has a different charge storage capacitance from the others, and it is ideally available for writing (i.e., storing) and reading the memory state without reversing the polarization state until it is needed. Less desirable, in some memories having ferroelectric capacitors, the act of reading the memory state may reverse polarization. Thus, after the polarization state is determined, a re-write of the memory cell is performed to place the memory cell in a pre-read state immediately after its determination. Regardless, memory cells incorporating ferroelectric capacitors are ideally non-volatile due to the bi-stable nature of the ferroelectric material forming part of the capacitor. Other programmable materials may be used as capacitor insulators toMaking the capacitor non-volatile.

The continual reduction in feature size places ever higher demands on the techniques used to form those features. One well-known technique is photolithography, which is commonly used to pattern features, such as conductive lines or capacitor electrodes, on a substrate. The concept of pitch can be used to describe the size of these features. For a typical repeating pattern of a memory or other array, pitch is defined as the distance between the same point in two adjacent features. Adjacent features are typically separated by a material such as an insulator. Thus, pitch can be viewed as the sum of the width of a feature and the width of the space or material separating that feature from the immediately adjacent features. Due to optical factors such as lens limitations and light or radiation wavelengths, lithography techniques have a minimum pitch below which a particular lithography technique cannot reliably form features. This minimum pitch is typically referred to by a variable or feature size F that defines half of the minimum pitch. This variable is commonly referred to as "resolution". The minimum spacing 2F sets a theoretical limit for feature size reduction.

Pitch multiplication (e.g., pitch doubling is a form of pitch multiplication) is one method for extending the capabilities of a photolithographic technique beyond its minimum pitch to achieve pitches less than 2F. Two pitch doubling techniques are illustrated and described in U.S. patent No. 5,328,810 to Lowrey et al and U.S. patent No. 7,115,525 to alabachev (Abatchev), the disclosures of which are incorporated herein by reference in their entirety. Such techniques can successfully reduce the potential lithographic pitch. Pitch multiplication may be by other or greater than "doubling," including by non-integer values.

It is an object of the present invention to address problems associated with or caused by pitch multiplication and lithography, but the present invention is not limited thereto.

Drawings

Fig. 1 is a diagrammatic top plan view of a portion of a substrate in process in accordance with one or more embodiments of the invention and is a diagrammatic top plan view of a portion of a substrate in accordance with one or more embodiments of the invention.

FIG. 2 is a diagrammatic, cross-sectional view of a portion of a substrate in process in accordance with an embodiment of the invention and is taken along line 2-2 in FIG. 3.

Fig. 3 is a view taken along line 3-3 in fig. 2.

Fig. 4 is a view of the fig. 2 substrate at a processing step subsequent to that shown by fig. 2 and taken along line 4-4 in fig. 5.

Fig. 5 is a view taken along line 5-5 in fig. 4.

Fig. 6 is a view of the fig. 5 substrate at a processing step subsequent to that shown by fig. 5.

Fig. 7 is a view of the fig. 6 substrate at a processing step subsequent to that shown by fig. 6 and taken along line 7-7 in fig. 8.

Fig. 8 is a view taken along line 8-8 in fig. 7.

Fig. 9 is a view of the fig. 7 substrate at a processing step subsequent to that shown by fig. 7 and taken along line 9-9 in fig. 10.

Fig. 10 is a view taken along line 10-10 in fig. 9.

Fig. 11 is a view of the fig. 9 substrate at a processing step subsequent to that shown by fig. 9 and taken along line 11-11 in fig. 12.

Fig. 12 is a view taken along line 12-12 in fig. 11.

FIG. 13 is a diagrammatic, cross-sectional view of a portion of a substrate in process in accordance with an embodiment of the invention and is taken along line 13-13 in FIG. 14.

Fig. 14 is a view taken along line 14-14 in fig. 13.

Fig. 15 is a view of the fig. 13 substrate at a processing step subsequent to that shown by fig. 13 and taken along line 15-15 in fig. 16.

Fig. 16 is a view taken through line 16-16 in fig. 15.

Fig. 17 is a view of the fig. 15 substrate at a processing step subsequent to that shown by fig. 15 and taken along line 17-17 in fig. 18.

Fig. 18 is a view taken along line 18-18 in fig. 17.

Fig. 19 is a view of the fig. 17 substrate at a processing step subsequent to that shown by fig. 17 and taken along line 19-19 in fig. 20.

Fig. 20 is a view taken along line 20-20 in fig. 19.

Fig. 21 is a view of the fig. 11 substrate at a processing step subsequent to that shown by fig. 11 and taken along line 21-21 in fig. 22.

Fig. 22 is a view taken along line 22-22 in fig. 21.

Fig. 23 is a view of the fig. 21 substrate at a processing step subsequent to that shown by fig. 21 and taken along line 23-23 in fig. 24.

Fig. 24 is a view taken through line 24-24 in fig. 23.

Fig. 25 is a view of the fig. 11 substrate at a processing step subsequent to that shown by fig. 11 and taken along line 25-25 in fig. 26.

Fig. 26 is a view taken along line 26-26 in fig. 25.

Fig. 27 is a view of the fig. 26 substrate at a processing step subsequent to that shown by fig. 26.

Fig. 28 is a view of the fig. 27 substrate at a processing step subsequent to that shown by fig. 27 and taken along line 28-28 in fig. 29.

Fig. 29 is a view taken along line 29-29 in fig. 28.

Fig. 30 is a view of the fig. 28 substrate at a processing step subsequent to that shown by fig. 28 and taken along line 30-30 in fig. 31.

Fig. 31 is a view taken along line 31-31 in fig. 30.

Fig. 32 is a view of the fig. 30 substrate at a processing step subsequent to that shown by fig. 30 and taken along line 32-32 in fig. 33.

Fig. 33 is a view taken through line 33-33 in fig. 32.

FIG. 34 is a diagrammatic, cross-sectional view of a portion of a substrate in process in accordance with an embodiment of the invention.

Fig. 35 is a view of the fig. 34 substrate at a processing step subsequent to that shown by fig. 34 and taken along line 35-35 in fig. 36.

Fig. 36 is a view taken along line 36-36 in fig. 35.

Fig. 37 is a view of the fig. 32 substrate at a processing step subsequent to that shown by fig. 32 and taken along line 37-37 in fig. 38.

Fig. 38 is a view taken along line 38-38 in fig. 37.

Fig. 39 is a view of the fig. 37 substrate at a processing step subsequent to that shown by fig. 37 and taken along line 39-39 in fig. 40.

Fig. 39A and 39B are enlarged portions of fig. 39 depicted in fig. 39.

Fig. 40 is a view taken along line 40-40 in fig. 39.

Detailed Description

Example embodiments according to the present invention are described with reference to fig. 1 to 40. Fig. 1 shows a portion of a substrate construction 10 that may be, for example, a portion of a much larger substrate, such as a semiconductor wafer. Embodiments of the invention are initially described in a method of forming an array that may be formed on a substrate 10, in one example shown in fig. 1, substrate 10 includes a plurality of integrated circuit die regions 5 (e.g., integrated circuit chips in a manufacturing process) separated by dicing street regions 7.

Fig. 2 and 3 show a substrate construction 10 in process according to an example method embodiment of the present invention, including a base substrate 11 having any one or more of conductive/conductor/conductive (i.e., electrically conductive herein), semi-conductive/semiconductor/semi-conductive, or insulative/insulator/insulative (i.e., electrically insulative herein). Various materials have been formed vertically over base substrate 11. The material may be beside, vertically inside, or vertically outside the material depicted in fig. 2 and 3. For example, other portions or all of the fabrication components of the integrated circuit system may be provided at a location above, around, or within the base substrate 11. Control and/or other peripheral circuitry for operating components within an array, such as array 12, may also be fabricated, and may or may not be entirely or partially within the array or sub-array. Further, multiple sub-arrays may also be fabricated and operated independently of one another, in tandem, or otherwise. In this document, "sub-array" may also be considered an array. Array 12 may be only a small portion of an individual die region 5.

The array 12 is shown to include a reference region 14 and an analysis region 16 laterally remote from the reference region 14. In one embodiment, the reference region 14 may be within the scribe lane region 7, and in another embodiment may be within the die region 5. The substrate construction 10 may include a plurality of reference regions 14 and/or a plurality of analysis regions 16. In one embodiment, the analysis region 16 may be within the scribe lane region 7, and in another embodiment may be within the die region 5. Analysis region 16 and reference region 14 may be in the same or different die regions 5 when each is in die region 5. Similarly, analysis region 16 and reference region 14, when each in scribe lane region 7, may be in the same or different scribe lane regions 7 between immediately adjacent die regions 5.

Longitudinally elongated and laterally spaced parallel mask lines 15A to 15H (collectively 15), comprising a photoimageable material 17 (e.g., a material capable of being photopatterned such as photoresist, polyimide, or a photoimageable material developed in the future), have been formed over an underlying substrate material 18. For purposes of illustration and clarity of the drawing, only 8 mask lines 15A-15H are shown. However, at least individual die regions 5 will likely have thousands, millions, etc. of such mask lines 15 therein. Hundreds, thousands, millions, etc. of such mask lines may also be within scribe line region 7, such as when reference region 14 is within scribe line region 7. Mask lines 15 may be formed, by way of example, by photolithographic patterning and etching of photoimageable material 17, and may be patterned at the lowest resolution of such patterning at the time of manufacture. Individual mask lines 15 may be considered as having opposing sidewalls 25. The lower substrate material 18 may comprise a plurality of the same or different composition materials (three layers 19, 21 and 22 are shown), and may comprise an outer hard mask layer, an anti-reflective coating, etc. and some of which may be sacrificial or some of which may still remain at least partially in the finished construction (e.g., at least prior to dicing by cutting through the dicing street region 7 to singulate the die region 5 into individual integrated circuit dies).

In some embodiments, the mask line 15 includes (a): a mask bridge comprising a photoimageable material extending laterally between and interconnecting two laterally immediately adjacent ones of the mask lines, or (b): a longitudinal mask gap extending completely laterally across one of the mask lines. Fig. 2 and 3 show an example embodiment comprising (a), in particular with mask bridge 20 comprising and interconnecting two laterally immediately adjacent mask lines 15F and 15G extending laterally within reference region 14. Mask bridge 20 may be considered to have opposing sidewalls 26.

Referring to fig. 4 and 5, and in one embodiment, photoimageable material 17 has been laterally trimmed, thereby laterally trimming mask lines 15A-15H and mask bridge 20. This may occur, for example, by an isotropic etch that will also likely reduce the vertical thickness (not shown) of the photoimageable material 17.

Referring to fig. 6, a material 28 having a composition different from that of the photoimageable material 17 (e.g., an oxide such as silicon dioxide) has been formed as shown. This can be considered a spacer layer or a spacer forming layer, e.g., as used in a process that some may consider to be a pitch multiplication process.

Fig. 7 and 8 show example subsequent processing in which the material 28 has been patterned (e.g., by maskless anisotropic etching of the material 28) to largely remove the material 28 from over horizontal surfaces, thereby forming sidewall blocks 30 of different composition than the photoimageable material 17 along opposing sidewalls 25 of individual mask lines 15 and along opposing sidewalls 26 of the mask bridges 20. Immediately adjacent sidewall blocks 30 laterally between immediately adjacent individual mask lines 15 may be considered to have a first space a therebetween. The spaces a may not necessarily have the same size as each other.

Referring to fig. 9 and 10, mask lines 15 (not shown) have been removed from between the sidewall blocks 30 (e.g., by selective etching and/or ashing of the photoimageable material 17[ not shown ]) to form second spaces B laterally alternating with the first spaces a between the sidewall blocks 30. The use of "first" and "second" with respect to spaces a and B is for ease of distinguishing one from the other, and either may be formed before or as the other is formed. The second spaces B may not necessarily have the same size as each other. Mask bridge 20 (not shown) has also been removed. The remaining sidewall blocks 30 may be considered to collectively comprise a mask 31.

Referring to fig. 11 and 12, a mask 31 (not shown) comprising sidewall blocks 30 (not shown) has been used as a mask when etching into the underlying substrate material 18 therebelow to form longitudinally elongated and parallel target lines 34A-34Q (collectively 34) having third spaces C laterally therebetween. This may occur, for example, by selectively etching material 19 (e.g., sacrificial hard masking material) relative to the material of sidewall blocks 30 (not shown). Mask 31 (not shown) has been removed during and/or after this etch. Regardless, this results, at least in part, from the mask bridge 20 shown in fig. 7 and 8, in two laterally immediately adjacent ones (e.g., 34M and 34N) of the target lines having longitudinal target gaps 35, the longitudinal target gaps 35 extending completely laterally across and between the two laterally immediately adjacent target lines 34M and 34N. Further, a bridge 36 (FIG. 11) of underlying substrate material extends laterally between the longitudinal ends 38 of the two laterally immediately adjacent target lines 34M and 34N and interconnects the longitudinal ends 38 at opposite longitudinal ends 37 of the longitudinal target gap 35. Thus, in one embodiment, the analysis zone 16 is laterally remote from the longitudinal target gap 35 and the underlying substrate material bridge 36. In one embodiment, where the analysis region, the longitudinal target gap, and the bridge of underlying substrate material are each in the die region 5, here in the same die region. In another embodiment, where the analysis region, the longitudinal target gap, and the bridge of underlying substrate material are each in the die region 5, this is in two different ones of the die regions.

An alternative example method embodiment in accordance with aspects of the present invention is described next with respect to substrate construction 10a with reference to fig. 13-20. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "a" or with different numerals. Referring to fig. 13 and 14, longitudinally elongated and laterally spaced parallel mask lines 15A through 15G (collectively 15) comprising photoimageable material 17 have been formed over underlying substrate material 18. Fig. 13 and 14 show example processing similar to that shown and described above with respect to fig. 4 and 5, as may occur after lateral trimming of mask line 15. However, substrate construction 10a is not shown to include a mask bridge (although it may have one mask bridge elsewhere), but rather is shown to include a longitudinal mask gap 40 extending completely laterally across one of the mask lines, such as mask line 15F.

Fig. 15-18 show example subsequent processing similar to that described above with respect to fig. 6-10, where first spaces a and second spaces B have been formed, however, where the a and B spaces in fig. 17 and 18 are ultimately reversed in position as compared to fig. 9 and 10. Regardless, and in one embodiment shown, the same basic construction can be produced in fig. 17 and 18 as compared to fig. 9 and 10.

Fig. 19 and 20 show subsequent processing similar to that described above with respect to fig. 11 and 12, and are shown as having the same basic construction as one another (e.g., fig. 19, 20 were created, at least in part, by using the longitudinal mask gap 40 and fig. 11, 12 were created, at least in part, by using the mask bridge 20).

In any case, it is considered that after the mask 31 (fig. 9, 10 or 17, 18) has been removed (fig. 11, 12 or fig. 19, 20), one might ask (e.g., not know) which of the third spaces C is caused by the first space a and which is caused by the second space B. For ease of depiction, the first space a and the second space B in the figures are shown as individually having the same lateral dimensions. In addition, the a and B spaces are shown as being identical to each other (as are the vertically protruding features 34 comprising material 19 on top of material 21 in fig. 11, 12, 19 and 20). However, if this is desirable, this may not necessarily occur, as such lateral dimensions depend in part on the patterning of the mask line 15 (including any lateral trimming thereof) and the deposited thickness of the material 28 of the sidewall bulk 30. Variations in one or more of these may result in the lateral dimensions of spaces a and B being different from each other, which may be highly undesirable and heretofore very difficult or impossible to determine what caused after mask 31 has been removed. However, the provision of the longitudinal target gap 35 and/or the underlying substrate material bridge 36 enables the use of one or both of these as reference positions (e.g., as starting positions or points) for estimating which of the third spaces C in the analysis region 16 originates from the first space a and/or which of the third spaces C in the analysis region 16 originates from the second space B. For example, the inherent knowledge of whether the mask bridge 20 or the longitudinal mask gap 40 was initially formed in the reference region 14 enables a determination of which of the spaces a or B at the longitudinal target gap or the lower substrate material bridge was generated by the first space a or by the second space B, which can be used as a starting position/starting point when counting or advancing from the reference region 14 towards the analysis region 16, even after removal of the mask 31, enabling a determination of which of the third spaces C resulted from the first space a and/or from the second space B. Using this information, for example, one skilled in the art can determine the cause of different sized spatial/vertical protruding features and can modify subsequent processing of the same or different substrate constructions.

Regardless, and in one embodiment in which the substrate construction 10 shown in fig. 1 is fabricated, an embodiment of the present invention includes cutting through the scribe lane region 7 at some point in time (e.g., now or later) to singulate the die region 5 into individual integrated circuit dies.

Referring to fig. 21 and 22, there is shown an example processing of the substrate construction 10 after the processing shown by fig. 11 and 12, respectively. In one embodiment and as shown, a conductive material 42 (e.g., a metallic material or a conductively-doped semiconductor material) has been formed in the longitudinal target gap 35 and along sidewalls of the bridge of lower substrate material 36. In one such embodiment and as shown, the etching depicted by fig. 11 and 12 has stopped (i.e., terminated), and the target line 34, the longitudinal target gap 35, and the lower substrate material bridge 36 have subsequently been translated (e.g., by etching) deeper into the lower substrate material 18 (e.g., deeper into the material 21) prior to forming the conductive material 42. Regardless, the conductive material 42 can be formed, for example, by depositing the material 42 followed by maskless anisotropic etching of the material 42 to largely remove the material 42 from over horizontal surfaces. In one embodiment, the conductive material 42 formed along the sidewalls of the bridge of lower substrate material 36 includes a conductive bridge 47 that is dummy in the finished construction.

Fig. 23 and 24 show example subsequent processing in which target line 34 (not shown) has been removed, for example, by selectively etching target line 34 with respect to materials 42 and 22. Additional or other processing may occur.

Other and/or subsequent processing may occur, such as in the embodiments described with reference to fig. 25-33 and 37-40. Referring to fig. 25 and 26, subsequent processing is shown as may occur immediately following the processing shown by fig. 11, 12 or fig. 19, 20 with respect to substrate 10 or 10a, by way of example only in the above-described embodiments, substrate 10 or 10a is the same basic construction and is therefore referred to as substrate construction 10 in fig. 25-33 and 37-40. Longitudinally elongated and laterally spaced parallel shaded lines 50A to 50D (collectively 50) comprising photoimageable material 51 (e.g., a material capable of being photopatterned, such as photoresist, polyimide, or future developed photoimageable/photoimageable materials, and which may have the same or different composition as photoimageable material 17) have been formed over target line 34 over lower sub-material 53 (which may comprise lower substrate material 18). The mask line 50 is angled relative to the target line 34 (i.e., except for a straight angle). The shading lines 50 and the target lines 34 are shown at 90 ° to each other, but other angles may of course be used. Example lower sub-material 53 is shown to include an example hard mask or underlayer material 56 (e.g., one or more of carbon, carbon dioxide, silicon nitride, an anti-reflective coating, etc.) that may be sacrificial.

In some embodiments, the shield line 50 includes (c): a shading bridge comprising photoimageable material extending laterally between and interconnecting two laterally immediately adjacent ones of the shading lines, or (d): a longitudinal shading gap extending completely laterally across one of the shading lines, similar to (a) (d) described above. Further, both the mask lines and the shield lines may comprise bridges, both may comprise longitudinal gaps, or one may comprise bridges and the other longitudinal gaps. Fig. 25 and 26 show an example embodiment comprising (C), specifically having a masking bridge 52 comprising photo-imaging material 51, the photo-imaging material 51 extending laterally between and interconnecting two laterally immediately adjacent masking lines 50B, 50C and may extend within a reference region 75 different from the reference region 14. Fig. 25 and 26 show a process similar to that shown in fig. 4 and 5 above or by fig. 4 and 5 above, in which the mask lines 50 and mask bridges 52 have been laterally trimmed as mask lines 15. Shield lines 50 and shield bridges 52 may be considered to include opposing sidewalls 54 and 55, respectively.

Referring to fig. 27, a material 57 having a composition different from that of the photoimageable material 51 (e.g., an oxide such as silicon dioxide) has been formed as shown. This can be considered a spacer layer or a spacer forming layer, e.g., as used in a process that some may consider to be a pitch multiplication process.

Fig. 28 and 29 depict example subsequent processing in which material 57 has been patterned (e.g., by maskless anisotropic etching of material 28) to largely remove material 57 from over horizontal surfaces, thereby forming side masses 59 of a different composition than photoimaging material 51 along opposing sidewalls 54 of individual masking lines 50 and along opposing sidewalls 55 of masking bridges 52 (or along (d): opposing sidewalls of longitudinal masking gaps, if used). Immediately adjacent side masses 59 laterally between immediately adjacent individual shading lines 50 may be considered to have a fourth space D therebetween. The fourth spaces D may not necessarily have the same size as each other.

Referring to fig. 30 and 31, the masking lines 50 (not shown) have been removed from between the side blocks 59 (e.g., by selective etching and/or ashing of the photoimaging material 51[ not shown ]) to form fifth spaces E between the side blocks 59 alternating laterally with the fourth spaces D. The use of "fourth" and "fifth" with respect to spaces D and E is for ease of distinguishing one from the other, and either may be formed before or when the other is formed. The fifth spaces E may not necessarily have the same size as each other. The masking bridge 52 (not shown) has also been removed. The remaining sidewall blocks 59 can be considered to collectively comprise the mask 58.

Referring to fig. 32 and 33, a mask 58 (not shown) comprising side blocks 59 (not shown) has been used to form longitudinally elongated and parallel calibration lines 60A-G (collectively 60) having sixth spaces G laterally therebetween when etching into the underlying material 53. Two laterally immediately adjacent calibrated lines (e.g., 60D, 60E) have a longitudinal calibrated gap 62 that spans between and is completely laterally between the respective two laterally immediately adjacent calibrated lines 60D, 60E due, at least in part, to (c) or (D) being completely laterally extended. The interconnecting bridge 64 extends transversely between the longitudinal ends 68 of the two transversely adjacent calibration lines 60D, 60E and interconnects the longitudinal ends 66 at opposite longitudinal ends 68 of the longitudinal calibration gap 62.

In one embodiment and as shown, calibration line 60 is in an analysis zone (e.g., 16), where this analysis zone is spaced away from longitudinal calibration gap 62 and interconnects bridges 64 (e.g., which are in reference zone 75). In one embodiment and as shown in fig. 32 and 33, the mask 58 (not shown) has been removed and one of the longitudinal indexing gaps 62 or interconnecting bridges 64 is used as a reference position to estimate which of the sixth spaces G in the analysis area originates from the fourth space D or which of the sixth spaces G originates from the fifth space E. In one embodiment and as shown, etching into the lower sub-material 53 using the side blocks 59 as masks 58 forms at least one of the calibration lines (e.g., 60D and/or 60E), and in one embodiment forms a plurality of the calibration lines (e.g., 60D and 60E) that are in the longitudinal target gap 35 (e.g., in the reference region 14) and laterally across the longitudinal target gap 35.

In one embodiment and as shown, openings 72, 72A, 72B, 72C, 72D, 72E, and 72H (collectively 72) are formed in lower substrate material 18 using side blocks 59 as mask 58 when etching lower sub-material 53, individually having a surrounding horizontal perimeter 74 of lower substrate material 18 (only a few shown in bold and with numerals 74 and associated leads for clarity of the drawing). Collectively, the openings 72 may have a variety of different sizes and/or shapes. In one embodiment and as shown, the openings 72A, 72B, 72C, 72D, 72E, and 72H individually have respective maximum rectilinear horizontal extents (e.g., the diagonal corners in the individual openings 72A, 72B, 72C, 72D, 72E, and 72H in fig. 32) that are greater than the maximum rectilinear horizontal extents of the individual openings 72 (e.g., the diagonal corners in the individual openings 72 in fig. 32).

In one such embodiment, this etching may be performed into target line 34 (not shown in fig. 32, 33), and in one embodiment, is performed with respect to calibration line 60 including example material 19, e.g., as shown and described with respect to substrate construction 10b with reference to fig. 34-36. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "b" or with different numerals. Referring to fig. 34, in contrast to the configuration of fig. 33, an alternative configuration 10B is shown. By way of example only, material 19 is shown as having been formed thicker than in the first-described embodiment, and formation of target line 35 from material 19 has not yet been performed by a complete etch through material 19.

Referring to fig. 35 and 36, a process largely analogous to that shown by fig. 32 and 33 has been conducted. The calibration line 60 comprises the lowermost portion of the material 19, wherein the target line 34 comprises the same material 19 and protrudes vertically (e.g. perpendicularly) with respect to the calibration line 60.

Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

Fig. 37 and 38 show subsequent processing. In particular, the pattern of fig. 32, 33 or fig. 35, 36 has been translated (e.g., by etching) deeper into underlying substrate material 18 into material 22, and material 19 (not shown) and material 21 (not shown) have been removed.

Subsequent processing described above or other processing may occur. For example, and with reference to fig. 39, 39A, 39B, and 40, conductive material 42 has been formed (e): in the longitudinal target gap 35; (f) the method comprises the following steps Along opposing sidewalls of the bridge 36 of lower substrate material; (g) the method comprises the following steps In the longitudinal indexing gap 62; (h) the method comprises the following steps Along opposing sidewalls of interconnect bridge 64; and (j): in the opening 72. (e) The conductive material 42 in (f), (g), and (h) may be formed to be dummy in the finished construction. In one such embodiment, all of the conductive material 42 in all (e), (f), (g), and (h) is eliminated (e.g., by etching or sawing through if within the scribe line regions). All of the conductive material 42 in all (j) is not eliminated (i.e., at least a portion of the conductive material 42 remains in at least some of the openings 72) and may be used at least in part as part of a conductive operating circuitry component, such as a capacitor electrode. The conductive material 42 is shown lining the opening 72 and not completely filling the opening 72. Alternatively, by way of example only, the conductive material 42 may completely fill the opening 72 (not shown).

Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

Embodiments of the present invention encompass a method of forming an array (e.g., 12). This includes using two different compositions of masking materials (e.g., 17, 28) to form a pattern of spaced repeating first features (e.g., 30) having substantially the same size and substantially the same shape as each other. A pattern having at least one of a different size or a different shape than the size or shape of the first features (e.g., any one or combination of the longitudinal gaps 29 and bridges 33 in fig. 9) interrupts second features within and interrupts the first pattern of features. The pattern of the first feature and the pattern break second feature is translated (e.g., by etching) into underlying substrate material (e.g., 18 in fig. 11 and 12) beneath the first feature and the pattern break second feature.

The first feature and the pattern interrupting second feature over the underlying substrate material are at least one of removed (e.g., by etching) during or after the translation. In one embodiment, the translating comprises etching into the underlying substrate material. After such removal, the pattern interruption second features (such as any one or combination of longitudinal gaps 35 and bridges 36 in fig. 11) in the lower substrate material are used as reference locations to estimate which of the two different composition masking materials is used to leave first spaces (such as one of a or B) between the first features in an analysis region in the material above the lower substrate material or which of the two different composition masking materials is used to leave second spaces alternating with the first spaces (such as the other of a or B) between the first features in the analysis region.

In one embodiment, one of the two different compositions comprises photoresist, and in one such embodiment, the other of the two different compositions lacks any photoresist. In one embodiment, one of the two different compositions is deposited atop the other, and the method further comprises etching the one anisotropically from atop the other maskless. In one embodiment, the first features comprise longitudinally elongated and parallel lines. In one such embodiment, two laterally immediately adjacent ones of the lines have a longitudinal gap extending completely laterally across and between the respective ones of the two laterally immediately adjacent lines, and the pattern interruption second feature comprises the longitudinal gap. In one embodiment, a lower substrate material bridge extends laterally between and interconnects longitudinal ends of the two laterally adjacent lines at opposite longitudinal ends of the longitudinal gap, wherein the pattern interruption second feature comprises the lower substrate material bridge.

In one embodiment, the first feature in the underlying substrate material includes an opening therein individually having a circumferential horizontal perimeter of the underlying substrate material. In one such embodiment, the pattern interrupting second features comprise openings in the underlying substrate material having a maximum rectilinear horizontal extent greater than a maximum rectilinear horizontal extent of individual ones of the openings of the first features.

Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

Embodiments of the invention include an integrated circuit and include a fabrication of an integrated circuit system that is independent of a method of manufacture. Nonetheless, this may include any of the attributes described above with respect to the method embodiments.

In one embodiment, an integrated circuit includes an array (e.g., 12) of circuit operating features (e.g., 34 x in region 16). This circuit also includes at least one circuit inoperable conductive construct comprising two laterally spaced and parallel longitudinally elongated conductive lines (e.g., 42 formed longitudinally along 34M, 34N). A longitudinal gap (e.g., 35) extends completely laterally across and between the two laterally spaced conductive lines. A conductive bridge (e.g., 47, and which may be dummy in the finished construction) extends laterally between and interconnects longitudinal ends (e.g., 49 in fig. 23) of the two laterally spaced conductive lines at opposite longitudinal ends (e.g., 76 in fig. 23) of the longitudinal target gap. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

In one embodiment, a construction of an integrated circuit system includes an array (e.g., 12) of first features of substantially the same size and substantially the same shape that include conductive material (e.g., 42 in the opening 72 as the first feature in FIGS. 39, 39A, 39B, and 40) and are horizontally spaced (i.e., in 3-dimensional space; e.g., horizontal or vertical 97 shown in 2-dimensional space in FIGS. 39, 39A, 40, and 40B) from one another and individually include a surrounding horizontal perimeter (e.g., 74) of conductive material. The second feature, such as 42 in any of the openings 72A, 72B, 72C, 72D, 72E, and 72H, is in the first array of features and comprises a bridge (such as 99 in fig. 39, 39A, 39B, and 40) of non-conductive material (such as 22 comprising silicon dioxide and/or silicon nitride) extending completely between two immediately adjacent ones of the horizontal rows (e.g., orthogonal thereto, as shown). The conductive material (e.g., 42 and which may be dummy in the finished circuitry construction) is all along the opposite longitudinal side of the bridge (e.g., 93 in fig. 39A and 39B). The conductive material on each of the opposing longitudinal sides of the bridge has a maximum straight-line horizontal extent (e.g., diagonal 89, because conductive material 42 spans all of the base of the respective opening 72A, 72B, 72C, 72D, 72E, and 72H) that is greater than the maximum straight-line horizontal extent (e.g., diagonal 87, because conductive material 42 spans all of the base of the respective opening 72) of the conductive material of the respective one of the first features. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

In this document, unless otherwise indicated, "vertical," "upper," "lower," "top," "bottom," "above," "below …," "upper," and "lower" are generally with reference to a vertical direction. "horizontal" refers to a general direction along the main substrate surface (i.e., within 10 degrees) and may be relative to the direction in which the substrate is processed during fabrication, and vertical is a direction substantially orthogonal to horizontal. References to "perfectly horizontal" are to an aspect along (i.e., no degree to) the main substrate surface, and may be relative to the direction in which the substrate is processed during fabrication. Further, "vertical" and "horizontal" as used herein are directions that are substantially perpendicular to each other and independent of the orientation of the substrate in three-dimensional space. In addition, "extending vertically" refers to a direction that makes an angle of at least 45 ° with the true horizontal. Furthermore, with regard to field effect transistors "vertically extending (extending), horizontally extending (extending) horizontal/vertical-extending" is a reference to the orientation of the transistor channel length along which current flows between the source/drain regions in operation. For a bipolar junction transistor, "vertically extending" and horizontally extending are with reference to the orientation of current along the length of the substrate along which current flows between the emitter and collector in operation.

Further, "directly above" and "directly below" require that two such regions/material elements at least to some extent laterally overlap (i.e., horizontally) with each other. Also, the use of "over" without "directly" merely requires that some portion of the area/material/component above the other be vertically outside the other (i.e., independent of whether there is any lateral overlap of two of the areas/materials/components). Similarly, the use of "under" without "direct" merely requires that some portion of the area/material/component under the other be vertically interior to the other (i.e., independent of whether there is any lateral overlap of two of the areas/materials/components).

Any of the materials, regions, and structures described herein may be homogeneous or non-homogeneous, and in any event, continuous or discontinuous over any material that is overlaid herein. Where one or more example ingredients are provided for any material, the material may comprise, consist essentially of, or consist of such one or more ingredients. Moreover, unless otherwise stated, each material may be formed using any suitable or yet to be developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

Additionally, "thickness" itself (without directional adjectives) is defined as the average straight-line distance perpendicularly from the nearest surface of an immediately adjacent material or area of different composition through a given material or area. In addition, the various materials or regions described herein can have a substantially constant thickness or have a variable thickness. If having a variable thickness, thickness refers to an average thickness, unless otherwise indicated, and such material or region will have some minimum thickness and some maximum thickness due to the thickness being variable. As used herein, "different compositions" only require that those portions of two such materials or regions that may be directly against each other be chemically and/or physically different, e.g., provided such materials or regions are non-homogeneous. If two such materials or regions are not directly against each other, then "different compositions" only require that those portions of the two such materials or regions that are closest to each other be chemically and/or physically different, provided that such materials or regions are non-homogeneous. In this document, a material, region or structure is "directly against" another when the materials, regions or structures are in at least some physical touch contact with each other. In contrast, "directly over …," "over …," "adjacent," "along," and "against" without "direct" encompass "directly against" as well as configurations in which intervening materials, regions, or structures do not cause the materials, regions, or structures to be in physical touching contact with one another.

Herein, region-material-components are "electrically coupled" to each other if in normal operation current is able to flow continuously from one to the other and such flow is primarily through the movement of the subatomic positive and/or negative charge when it is sufficiently generated. Another electronic component may be between and electrically coupled to the region-material-component. In contrast, when a region-material-component is referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

Additionally, a "metallic material" is any one or combination of an elemental metal, a mixture, or an alloy of two or more elemental metals and any conductive metal compound.

Herein, "selectivity" with respect to etching (etching/ablating), removing (removing/removing), and/or forming (reforming/formatting) is such an action that one such material does so relative to another such material based on a ratio of at least 2:1 by volume.

Unless otherwise indicated, use of "or" herein encompasses either and both.

In this context, "dummy" means that there is no current passing through it in the finished circuitry construction and it may be a circuit inoperable dead end that is not part of the current path of the circuit, even if extending to or from an electronic component.

Conclusion

In some embodiments, a method of forming an array includes forming a pattern of spaced repeating first features having substantially the same size as each other and substantially the same shape as each other using two different composition masking materials. A pattern having at least one of a different size or a different shape than a size or a shape of the first feature interrupts a second feature within the pattern of the first feature and interrupts the pattern of the first feature. Translating the pattern of the first feature and the pattern break second feature into a lower substrate material below the first feature and the pattern break second feature. Removing material of the first feature and the pattern disrupting second feature over the underlying substrate material at least one of during or after the translating. After the removing, using the pattern interrupted second features in the underlying substrate material as a reference location to estimate which of the two different composition masking materials is used to leave first spaces between the first features in an analysis region in the material above the underlying substrate material or which of the two different composition masking materials is used to leave second spaces alternating with the first spaces between the first features in the analysis region.

In some embodiments, a method of forming an array comprising a pattern, comprising: longitudinally elongated and laterally spaced parallel mask lines are formed comprising a photoimageable material. The mask line includes (a): a mask bridge comprising the photoimageable material extending laterally between and interconnecting two laterally immediately adjacent ones of the mask lines, or (b): a longitudinal mask gap extending completely laterally across one of the mask lines. Sidewall blocks having a composition different from that of the photoimageable material are formed along opposing sidewalls of individual ones of the mask lines and along opposing sidewalls of either (a) or (b). Immediately adjacent ones of the sidewall masses laterally between immediately adjacent ones of the individual mask lines have a first opening therebetween. Removing the mask lines from between the sidewall blocks to form second spaces between the sidewall blocks alternating laterally with the first spaces. After removing the mask lines, using the sidewall blocks as a mask when etching into a lower substrate material below the sidewall blocks to form longitudinally elongated and parallel target lines having a third space laterally therebetween, two laterally adjacent ones of the target lines having a longitudinal target gap laterally across and laterally between respective ones of the two laterally adjacent target lines at least in part due to the (a) or (b) extending laterally completely across and laterally between the two laterally adjacent target lines, a lower substrate material bridge extending laterally between and interconnecting longitudinal ends of the two laterally adjacent target lines at opposite longitudinal ends of the longitudinal target gap.

In some embodiments, an integrated circuit includes an array of circuit-operating features and at least one circuit-inoperable conductive construct comprising two laterally-spaced and parallel longitudinally-elongated conductive lines. A longitudinal gap extends completely laterally across and between the two laterally spaced conductive lines. A conductive bridge extends laterally between and interconnects the longitudinal ends of the two laterally spaced conductive lines at opposite longitudinal ends of the longitudinal indexing gap.

In some embodiments, a construction of an integrated circuit system includes an array of first features of substantially the same size and substantially the same shape that include conductive material and are horizontally spaced from each other in horizontal rows and individually include surrounding horizontal perimeters of the conductive material. The second feature is in the array of the first features. The second feature comprises a bridge of non-conductive material extending completely between and across two immediately adjacent ones of the horizontal rows. The conductor material is all along opposite longitudinal sides of the bridge. The conductor material on each of the opposing longitudinal sides of the bridge has a maximum rectilinear horizontal extent that is greater than a maximum rectilinear horizontal extent of the conductive material of an individual of the first features.