阅读说明：本技术 宽能隙半导体基板、宽能隙半导体基板之制造装置及宽能隙半导体基板之制造方法 (Wide-gap semiconductor substrate, apparatus for manufacturing wide-gap semiconductor substrate, and method for manufacturing wide-gap semiconductor substrate ) 是由 山本孝 于 2018-12-13 设计创作，主要内容包括：本发明提供一种半导体基板之制造方法,可在将机械强度维持地较强的状态下形成功率损失低的原件。蚀刻方法是使用电浆化之蚀刻气体来进行蚀刻处理,以仅将配设于处理室(11)内之基台(15)上所载置之宽能隙半导体基板(W)中形成元件之区域加以薄板化,包含以下步骤：将蚀刻气体供给至前述处理室(11)内,并将该蚀刻气体电浆化；对前述基台(15)施予偏压电位,仅将前述宽能隙半导体基板(W)中形成元件之区域进行蚀刻而使其薄板化。(The present invention provides a method for manufacturing a semiconductor substrate, which can form an original with low power loss while maintaining a high mechanical strength. The etching method is to use the etching gas of plasma to perform etching treatment to thin the region for forming the device in the wide-gap semiconductor substrate (W) placed on the base table (15) in the processing chamber (11), and comprises the following steps: supplying an etching gas into the processing chamber (11) and making the etching gas into a plasma; applying a bias potential to the base (15) and etching only the region of the wide-gap semiconductor substrate (W) where the device is to be formed to make it thin.)

1. A wide energy gap semiconductor substrate on which elements are formed, comprising:

a 1 st substrate region, which is an inner region having a 1 st thickness; and

a 2 nd substrate region disposed so as to surround the outer periphery of the 1 st substrate region, having a 2 nd thickness thicker than the 1 st thickness,

the element is formed in the 1 st substrate region, the 1 st thickness is 10 μm to 50 μm, and the 2 nd thickness is 100 μm to 350 μm.

2. The wide bandgap semiconductor substrate of claim 1, wherein said 1 st substrate region is formed by dry etching.

3. The wide gap semiconductor substrate according to claim 1 or 2, wherein the wide gap semiconductor substrate is composed of silicon carbide (4H-SiC, 6H-SiC, 3C-SiC), gallium nitride (GaN), gallium oxide (GaO) or diamond (C).

4. An apparatus for manufacturing a wide gap semiconductor substrate, which performs an etching process using an etching gas using a plasma to thin only a region where a device is to be formed in a wide gap semiconductor substrate placed on a stage disposed in a processing chamber, wherein:

the manufacturing apparatus has an outer periphery covering mechanism having a covering member for covering only the peripheral edge portion of the wide gap semiconductor substrate placed on the base when the wide gap semiconductor substrate is subjected to etching treatment, so that only the region where the device is formed, which is not covered by the covering member, is subjected to etching treatment and thinned.

5. The apparatus for manufacturing a wide gap semiconductor substrate according to claim 4, wherein said outer periphery covering mechanism further has a support member disposed in said processing chamber for supporting said covering member,

the support member supports the covering member so as to cover only the peripheral edge portion with a gap formed between the support member and the wide-gap semiconductor substrate.

6. The apparatus for manufacturing a wide gap semiconductor substrate according to claim 5, wherein the supporting member supports the covering member with a gap of 0.5mm or more and 3mm or less formed between the supporting member and the wide gap semiconductor substrate.

7. The apparatus for manufacturing a wide gap semiconductor substrate according to claim 4, wherein said outer periphery covering mechanism further has a support member provided in said processing chamber for supporting said covering member,

when the wide gap semiconductor substrate is raised by the base, the covering member is brought into contact with the peripheral edge of the wide gap semiconductor substrate and is raised upward, and only the peripheral edge of the wide gap semiconductor substrate placed on the base is covered and is not etched.

8. The apparatus for manufacturing a wide gap semiconductor substrate according to any one of claims 4 to 7, wherein the covering member is made of quartz, alumina or yttria, or a material in which a metal coating is applied to one of them.

9. The apparatus for manufacturing a wide gap semiconductor substrate according to any one of claims 4 to 8, further comprising a depth monitor for detecting an etching depth of the wide gap semiconductor substrate, the depth monitor comprising:

a depth sensor including a pair of etched surfaces of the wide bandgap semiconductor substrate and a light source for irradiating the cover member with light; and

a processing portion for calculating the etching depth based on the reflected light reflected from the etched surface and the covering member, respectively.

10. The apparatus for manufacturing a wide gap semiconductor substrate according to any one of claims 4 to 9, wherein the wide gap semiconductor substrate is composed of silicon carbide (4H-SiC, 6H-SiC, 3C-SiC), gallium nitride (GaN), gallium oxide (GaO) or diamond (C).

11. A method for manufacturing a wide gap semiconductor substrate, in which an etching process is performed using an etching gas using a plasma to thin only a region where a device is to be formed in the wide gap semiconductor substrate placed on a stage disposed in a processing chamber, comprises the steps of:

placing a wide gap semiconductor substrate on a stage in the processing chamber, and covering only a peripheral portion of the wide gap semiconductor substrate where no element is formed by a covering member;

supplying an etching gas into the processing chamber and making the etching gas into a plasma;

applying a bias potential to the base, and etching only the region of the wide-gap semiconductor substrate where the device is formed to reduce the thickness of the substrate.

12. The method for manufacturing a wide gap semiconductor substrate according to claim 11, wherein a gap is formed between the wide gap semiconductor substrate and the covering member.

13. The method for manufacturing a wide gap semiconductor substrate according to claim 12, wherein a gap of 0.5mm or more and 3mm or less is formed between the wide gap semiconductor substrate and the covering member.

14. The method for manufacturing a wide gap semiconductor substrate according to any one of claims 11 to 13, wherein the covering member is made of quartz, alumina or yttria, or a material in which one of them is coated with a metal coating.

15. The method for manufacturing a wide gap semiconductor substrate according to any one of claims 11 to 14, wherein an etching treatment is performed so that the thickness of the wide gap semiconductor substrate is 50 μm or less.

16. The method for manufacturing a wide gap semiconductor substrate according to any one of claims 11 to 15, wherein the etching gas contains a fluorine-based gas.

17. The method for manufacturing a wide gap semiconductor substrate according to any one of claims 11 to 16, wherein a bias potential is applied by supplying a high frequency power of 500W or more to the base,

and the pressure in the processing chamber is set to be less than 30 Pa.

18. The method for manufacturing a wide gap semiconductor substrate according to any one of claims 11 to 17, wherein the wide gap semiconductor substrate is composed of silicon carbide (4H-SiC, 6H-SiC, 3C-SiC), gallium nitride (GaN), gallium oxide (GaO) or diamond (C).

Technical Field

The present invention relates to a wide-gap semiconductor substrate with a device formed on the surface, a manufacturing apparatus of the wide-gap semiconductor substrate, and a manufacturing method of the wide-gap semiconductor substrate.

Background

In recent years, with the progress of miniaturization, thinning, weight reduction, low loss (high efficiency), and high function (high performance) of electronic devices, thin semiconductor devices manufactured using a silicon substrate having a reduced thickness have been developed. Particularly, in the case of a vertical power device, the thinner the silicon substrate (wafer) is, the lower the loss is, and therefore, it is preferable to manufacture the silicon substrate having the minimum thickness and the necessary withstand voltage performance. Therefore, in order to manufacture a thin power device, the back surface opposite to the surface on which the organic energy layer is formed is polished, and the silicon substrate is thinned to a desired thickness. However, there are problems that cracking or chipping occurs due to substrate warpage occurring when thinning a silicon substrate, and cracking or the like occurs when transporting the thinned silicon substrate. As disclosed in patent document 1 (japanese patent No. 6004100), there is a technique of thinning the back surface of a silicon substrate by polishing only the inner region, while leaving the outer peripheral portion of the back surface of the silicon substrate without polishing. Thus, cracking or warping of the silicon substrate can be reduced.

On the other hand, the power element is also required to have a lower on-resistance or a higher withstand voltage. In order to meet this demand, attention is paid to the use of a silicon carbide substrate instead of a conventional silicon substrate. Silicon carbide has a smaller crystal lattice constant (stronger bonding between atoms) and a larger energy band gap (2.2eV or more) than that of silicon (1.12eV) as compared with silicon (hereinafter referred to as a wide energy gap). Furthermore, the absolute electric breakdown field strength (unit V/cm) of the silicon carbide substrate is higher than that of the silicon substrate by a factor of about 10. In other words, when manufacturing an equivalent pressure-resistant product (element), the thickness of 1/10 can be made as compared with the case where the silicon substrate is used. For example, if the withstand voltage of the silicon carbide substrate is 100V/μm and the thickness of the substrate is 15 μm, the silicon carbide substrate can be used for devices which can withstand a withstand voltage of 1500V or less (1200V). On the other hand, a substrate having a thickness of about 150 μm is required to obtain the same level of withstand voltage. Therefore, when a device having a required withstand voltage is manufactured using a silicon carbide substrate, the thickness thereof is preferably 1/10 as compared with that of a silicon substrate. The device is manufactured by laminating an functional layer on the front surface of a silicon carbide substrate, forming a region defined by a plurality of planned dividing lines in the functional layer, polishing the back surface of the silicon carbide substrate by a polishing device to reduce the thickness to a predetermined thickness, and then cutting the silicon carbide substrate along the planned dividing lines by a dicing device, a laser processing device, or the like to divide the silicon carbide substrate into individual device wafers. Then, each of the divided wafers may be used as a power element.

[ Prior art documents ]

Patent document

Patent document 1: japanese patent publication No. 6004100

Disclosure of Invention

[ problems to be solved by the invention ]

For example, patent document 1 discloses a wafer thinning technique in which the entire wafer is thinned by a polishing apparatus in a state where the wafer is reinforced by a support substrate bonded to the wafer. However, as described in patent document 1, when a polishing apparatus is used, if the wafer is extremely thinned (for example, 50 μm or less depending on the material of the wafer), there is a problem that the wafer is cracked or warped. Further, when the wafer is a wide bandgap semiconductor substrate made of silicon carbide or the like, since the wafer has a hardness higher than that of a silicon substrate, if the back surface of the wafer is polished by a polishing wheel having a polishing stone, the polishing stone is worn by about 4 to 5 times the polishing amount, which is very uneconomical. For example, when polishing a silicon substrate 100 μm, the polishing stone will wear 0.1 μm, whereas when polishing a silicon carbide substrate 100 μm, the polishing stone will wear 400-500 μm, which is 4000-5000 times as much as the silicon substrate.

In the above patent document 1, when the wafer is made of silicon carbide (SiC), since the SiC wafer cannot be dissolved, it has been proposed to thin the wafer by CMP. However, when polishing a SiC wafer by CMP, the polishing rate is slow and is not practical. In addition, in both polishing and CMP, it is difficult to reduce the thickness of the recess in the small rectangular region and discharge polishing debris from the recess, and there is also a problem that the deformation must be removed.

On the other hand, in the power device, it is required to reduce the on-resistance or increase the withstand voltage, and the wafer is required to be thinner.

In view of the above circumstances, an object of the present invention is to provide a wide-gap semiconductor substrate, a manufacturing apparatus thereof, and a manufacturing method thereof, which can form an element with low power loss while maintaining high mechanical strength.

[ means for solving the problems ]

To achieve the above object, the present invention relates to a wide bandgap semiconductor substrate (hereinafter referred to as "semiconductor substrate") on which devices are formed, comprising: a 1 st substrate region, which is an inner region having a 1 st thickness; and a 2 nd substrate region, which is a region disposed to surround the outer periphery of the 1 st substrate region and has a 2 nd thickness thicker than the 1 st thickness; the element is formed in the 1 st substrate region, the 1 st thickness is 10 μm to 50 μm, and the 2 nd thickness is 100 μm to 350 μm.

In the semiconductor substrate, since a 1 st substrate region (thin plate portion) having a thickness of 10 μm to 50 μm is formed in an inner region and a 2 nd substrate region (thick plate portion) having a thickness of 100 μm to 350 μm is formed along an outer periphery of the thin plate portion, cracking or warping of the semiconductor substrate can be effectively prevented. Furthermore, the device formed on the thin plate part can reduce the on-resistance.

Therefore, it is possible to form an element with low power loss while maintaining the mechanical strength of the semiconductor substrate at a high level.

In the semiconductor substrate, the 1 st substrate region is preferably formed by dry etching.

According to the semiconductor substrate, since the 1 st substrate region is formed by dry etching, it is not necessary to polish the back surface of the semiconductor substrate with an expensive grinding stone which is easily worn.

Therefore, compared with the case of using the grinding stone which needs to be exchanged every time of abrasion to process, the manufacturing cost can be greatly reduced.

In the semiconductor substrate, the semiconductor substrate is preferably made of silicon carbide (4H-SiC, 6H-SiC, 3C-SiC), gallium nitride (GaN), gallium oxide (GaO) or diamond (C).

According to the semiconductor substrate, since the semiconductor substrate has a larger energy band gap (2.2eV or more) than that of silicon (1.12eV), the on-resistance of the element formed in the thin plate portion can be further reduced, and the power loss of the element can be further reduced.

The semiconductor substrate can be manufactured more favorably by a manufacturing apparatus having the following configuration. The manufacturing apparatus performs an etching process using an etching gas of plasma to thin only a region where a device is to be formed in a semiconductor substrate placed on a base placed in a processing chamber, and has an outer periphery covering mechanism having a covering member capable of covering only a peripheral portion of the semiconductor substrate placed on the base when the semiconductor substrate is subjected to the etching process, and thinning only a region where the device is to be formed, which is not covered by the covering member, by the etching process.

According to this manufacturing apparatus, since the outer periphery covering means is provided, when the semiconductor substrate is subjected to the etching process, only the peripheral portion of the semiconductor substrate placed on the base is covered with the covering member so as not to be etched, and therefore the covering member can serve as a mask, and only the peripheral portion of the semiconductor substrate is not etched, and only the region where the device is to be formed is etched. Therefore, the inner region of the device can be easily thinned. Further, by thinning the inner region, the semiconductor substrate can be effectively prevented from cracking or warping. Furthermore, the device formed on the thin plate part can reduce the on-resistance.

The outer peripheral cover means may further include a support member provided in the processing chamber for supporting the cover member, and the support member may be configured to support the cover member with a gap formed between the support member and the semiconductor substrate, and the gap may be set to 0.5mm or more and 3mm or less.

In the manufacturing apparatus, the outer peripheral cover means may further include a support member provided in the processing chamber for supporting the cover member, and the cover member may be configured to abut against the peripheral edge portion of the semiconductor substrate and be lifted upward when the semiconductor substrate is lifted by the base, and cover only the peripheral edge portion of the semiconductor substrate placed on the base so as not to be etched.

Further, the manufacturing apparatus preferably further comprises a depth monitor for detecting an etching depth of the semiconductor substrate, the depth monitor comprising: a depth sensor including a pair of etched surfaces of the semiconductor substrate and a light source for irradiating the cover member with light; and a processing section for calculating the etching depth based on the reflected light reflected from the etched surface and the covering member, respectively.

According to this manufacturing apparatus, since the etching end point can be identified based on the etching rate and the etching time, the etching process can be started without a pre-step of calculating the etching rate (setting the execution condition) by measuring the etching amount in advance, and thus the manufacturing time can be greatly reduced.

In the manufacturing apparatus, the semiconductor substrate is preferably made of silicon carbide (4H-SiC, 6H-SiC, 3C-SiC), gallium nitride (GaN), gallium oxide (GaO), or diamond (C).

Therefore, since the semiconductor substrate formed of these materials has a larger band gap (2.2eV or more) than that of silicon (1.12eV), the on-resistance of the element formed in the thin plate portion can be further reduced, and the power loss of the element can be further reduced.

Further, the semiconductor substrate can be preferably manufactured by a manufacturing method including the following steps. That is, the manufacturing method is to perform etching treatment by using etching gas of plasma for thinning only a region where a device is to be formed in a semiconductor substrate placed on a pedestal disposed in a processing chamber, and includes the steps of:

placing a semiconductor substrate on a stage in the processing chamber, and covering only a peripheral portion of the semiconductor substrate where no element is formed by a covering member;

supplying an etching gas into the processing chamber and making the etching gas into a plasma;

applying a bias potential to the base, and etching only the region of the semiconductor substrate where the device is formed to reduce the thickness of the substrate.

According to this manufacturing method, when the semiconductor substrate is subjected to the etching treatment, only the peripheral portion of the semiconductor substrate placed on the base is covered and not etched, so that only the peripheral portion of the semiconductor substrate can be prevented from being etched. Therefore, a semiconductor substrate can be manufactured in which the thin plate portion is formed in the inner region and the thick plate portion is formed along the outer periphery of the thin plate portion. Also, with the semiconductor substrate thus constructed, the semiconductor substrate can be effectively prevented from cracking or warping. Furthermore, by forming the element on the thin plate portion, an element with low on-resistance can be manufactured.

In the manufacturing method, a gap is preferably provided between the semiconductor substrate and the cover member. When a semiconductor substrate is etched in a state where a bias potential is applied to a base, if a covering member comes into contact with the semiconductor substrate, the covering member is also biased by the material of the covering member, and the covering member is sputtered by ions in plasma, and the resultant is attached to the surface of the thin plate portion which is the inner region of the semiconductor substrate, thereby deteriorating the surface accuracy. Therefore, by providing a gap between the semiconductor substrate and the covering member, the covering member can be prevented from generating a bias potential, thereby preventing the surface accuracy of the surface of the thin plate portion from being deteriorated due to sputtering of the covering member.

The gap between the semiconductor substrate and the cover member is preferably 0.5mm to 3 mm. This is because when the gap is less than 0.5mm, the generation of a bias potential in the covering member cannot be effectively prevented, and when the gap is 3mm or more, the etching seed crystal intrudes between the semiconductor substrate and the covering member, so that the region (2 nd substrate region) covered with the covering member of the semiconductor substrate is etched, and the inner peripheral edge portion (shoulder portion) of the 2 nd substrate region (thick plate portion) is etched, etc., resulting in deterioration of the shape of the obtained semiconductor substrate.

Further, the covering member is preferably made of quartz, alumina or yttria, or a material in which one of them is coated with a metal coating. In the case of alumina, the above sputtering is likely to occur, and therefore, the surface accuracy of the surface of the thin plate portion is deteriorated, but there is an advantage that the covering member can be manufactured at low cost. Further, in the case of yttrium, there is a disadvantage that the production cost of the covering member is high, but there is an advantage that even if the above-mentioned sputtering occurs, the generated product is easily lost, and therefore the surface accuracy of the surface of the thin plate portion is not easily deteriorated. Further, in the case of quartz, there are advantages that the production cost of the covering member is relatively inexpensive compared to yttrium, and even if the above sputtering occurs, the generated product disappears and the surface accuracy of the thin plate portion surface hardly deteriorates. Further, although the quartz is etched by the etching seed, the load can be reduced by etching the covering member, and the thin plate portion can be etched to a uniform thickness.

In the manufacturing method, the thickness of the semiconductor substrate is preferably etched to be 50 μm or less.

According to the manufacturing method, the thickness of the semiconductor substrate in the region where the device is formed can be set to 50 μm or less, so that the on-resistance of the device formed in the thinned region can be further reduced, and the power loss of the device can be further reduced.

In the manufacturing method, the etching gas preferably contains a fluorine-based gas.

According to the manufacturing method, it is preferable that a high frequency power of 500W or more is supplied to the base to apply a bias potential, and the pressure in the processing chamber is 30Pa or less.

According to this manufacturing method, high-frequency power of 500W or more is supplied to the base and a bias potential is applied, so that even a semiconductor substrate having strong bonding between atoms can be etched at high speed. Further, since the pressure in the processing chamber is 30Pa or less, the plasma can be stabilized and the in-plane uniformity of the etching amount can be improved.

In this production method, the wide-gap semiconductor substrate is preferably made of silicon carbide (4H-SiC, 6H-SiC, 3C-SiC), gallium nitride (GaN), gallium oxide (GaO) or diamond (C).

According to this manufacturing method, since the semiconductor substrate formed of these materials has a larger band gap (2.2eV or more) than that of silicon (1.12eV), the on-resistance of the element formed in the thin plate portion can be further reduced, and the power loss of the element can be further reduced.

[ Effect of the invention ]

As described above, according to the wide gap semiconductor substrate of the present invention, since the element can be formed in the thin plate portion formed inside and the thick plate portion is provided along the outer periphery of the thin plate portion, the element with low power loss can be formed while maintaining high mechanical strength of the wide gap semiconductor substrate.

Further, according to the apparatus for manufacturing a wide gap semiconductor substrate of the present invention, only the peripheral portion of the wide gap semiconductor substrate can be covered and not etched, so that only the peripheral portion of the wide gap semiconductor substrate is not etched. Therefore, only the inner side of the formed element can be easily thinned.

Further, according to the method for manufacturing a wide gap semiconductor substrate of the present invention, when the wide gap semiconductor substrate is etched, only the peripheral portion of the wide gap semiconductor substrate can be covered without being etched. Therefore, only the inner side of the formed element can be easily thinned.

Drawings

FIG. 1(a) is a vertical sectional view of a semiconductor substrate according to embodiment 1 of the present invention, and FIG. 1(b) is a plan view of the semiconductor substrate.

FIG. 2 is a sectional view showing a schematic configuration of an etching apparatus (manufacturing apparatus) used for manufacturing the semiconductor substrate shown in FIG. 1(a) and FIG. 1 (b).

FIG. 3(a), FIG. 3(b), and FIG. 3(c) are vertical sectional views showing the steps of the method for manufacturing the semiconductor substrate shown in FIG. 1(a) and FIG. 1 (b).

FIGS. 4(a) and 4(b) are vertical sectional views showing steps of the method for manufacturing the semiconductor substrate of FIGS. 1(a) and 1 (b).

FIG. 5 is a sectional view showing a schematic configuration of an etching apparatus (manufacturing apparatus) according to embodiment 2 of the present invention.

FIG. 6 is a view for explaining a manufacturing method and a manufacturing apparatus according to another embodiment of the present invention.

FIG. 7 is a plan view showing a wide bandgap semiconductor substrate according to another embodiment of the present invention.

FIG. 8 is a plan view showing a covering member for manufacturing the wide gap semiconductor substrate shown in FIG. 7.

Detailed Description

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1

Fig. 1(a) is a vertical sectional view of a semiconductor substrate 70 according to embodiment 1 of the present invention, and fig. 1(b) is a plan view of the semiconductor substrate 70. The semiconductor substrate 70 is a wide-gap semiconductor substrate made of silicon carbide (4H-SiC) having high withstand voltage performance. The electronic device manufactured by using the semiconductor substrate 70 has a small power loss, and can be used as a power semiconductor device for inverter equipment, a power module for home appliances, or an electric vehicle, which has high performance and power saving.

Further, since silicon carbide has a higher Young's modulus than silicon and a high temperature drop even at a high temperature, silicon carbide is used as an MEMS (Micro-Electro Mechanical Systems) device having both a circuit element and a fine Mechanical element, and has been used in acceleration sensors, printer heads, pressure sensors, DMD (digital Micro mirror device), and the like, and the market scale is expanding.

As shown in fig. 1a and 1 b, the semiconductor substrate 70 of this example is constituted by a thin plate portion (1 st substrate region) 70a having a circular shape in plan view as an inner region and a thick plate portion (2 nd substrate region) 70b as an outer annular region, the thin plate portion 70a having a thickness T1(10 μm to 50 μm), and the thick plate portion 70b having a thickness T2 (> T1) formed along the outer periphery of the thin plate portion 70 a. In other words, the semiconductor substrate 70 has a circular recess 70c in plan view in a region corresponding to the inner thin plate portion 70 a. The thick plate portion 70b is formed to surround the outer periphery of the thin plate portion 70a concentrically with the thin plate portion 70 a. Here, the area of the recess 70c is arbitrary and can be determined according to the mechanical strength required for the semiconductor substrate 70.

As shown in fig. 1a, an angle θ between a surface Pc (inner circumferential surface of the thick plate portion 70 b) connecting the planar surface Pa of the thin plate portion 70a and the planar surface Pb of the thick plate portion 70b and the surface Pa is substantially perpendicular.

As shown in fig. 1a, an element 50 having a size of several mm square is formed on a surface (i.e., a back surface, a lower surface in fig. 1 a) opposite to the surface Pa of the thin plate portion 70a, and the element 50 includes a vertical power element (an Insulated Gate Bipolar Transistor (IGBT), a MOS field effect transistor (MOSFET), a diode, or the like).

On the other hand, the thick plate portion 70b in the outer region ensures the mechanical strength of the semiconductor substrate 70, and serves to prevent the semiconductor substrate 70 from cracking or warping during the transportation of the semiconductor substrate 70 or during the heat treatment step. For example, the thickness T2 of the thick plate part 70b is 100 μm to 350 μm. By making the range, the semiconductor substrate 70 can be effectively prevented from cracking or warping. In contrast, the thin plate portion 70a has a thickness T1 of 10 μm to 50 μm. By making the range, the on-resistance of the element 50 formed on the surface of the thin plate portion 70a can be reduced while maintaining the high mechanical strength. Therefore, an element with low power loss can be manufactured while maintaining high mechanical strength.

In this example, the planar shape of the recess 70c is made circular, but the present invention is not limited to this. For example, the planar shape of the recess 70c may be rectangular, rounded quadrangle (quadrangle with rounded corners), polygonal, or the like, and the planar shape of the recess 70c includes all shapes suitable for the shape of the device to be formed. In this case, the same effect as in this example can be obtained. In the present embodiment, the angle θ is made substantially right (90 degrees), but the present invention is not limited to this, and the angle θ may be acute or obtuse. In this case, the same effect as in this example can be obtained. In the present example, the description is given of the case where there are 1 recesses, but a plurality of recesses may be formed.

Next, an etching apparatus 1 will be described with reference to fig. 2, wherein the etching apparatus 1 is a manufacturing apparatus for manufacturing the semiconductor substrate 70 of the present example. Fig. 2 is a sectional view showing a schematic configuration of an etching apparatus 1 used for manufacturing the semiconductor substrate 70 shown in fig. 1(a) and 1 (b).

As shown in fig. 2, the etching apparatus 1 includes a process chamber 11 having a closed space, a base 15 which is arranged in the process chamber 11 so as to be movable up and down and on which a wafer W to be etched is placed, an elevating column (elevating means) which elevates and lowers the base 15, an exhaust means 20 which reduces the pressure in the process chamber 11, a gas supply means (process gas supply unit) 25 which supplies a process gas into the process chamber 11, a plasma generation means 30 which makes the process gas supplied into the process chamber 11 into a plasma, a high-frequency power source (base power supply unit) 35 which supplies a high-frequency power to the base 15, and an outer peripheral cover mechanism 40 which covers the peripheral edge (non-etched portion) of the wafer W. The etching apparatus 1 performs an etching process using a plasma-formed etching gas, and thins only a region where devices are to be formed in a wafer W placed on a base 15 disposed in a processing chamber 11. Here, the outer periphery covering mechanism 40 serves to cover only the peripheral edge of the wafer W placed on the base 15 and prevent the wafer W from being etched when the wafer W is etched.

The processing chamber 11 is composed of a lower processing chamber 12 and an upper processing chamber 13 having internal spaces communicating with each other, and the upper processing chamber 13 can be formed smaller than the lower processing chamber 12. The base 15 is composed of an upper member 16 on which the wafer W can be placed and a lower member 17 to which a lift column 18 can be connected, and is disposed in the lower processing chamber 12.

The outer peripheral cover means 40 includes a cover member 41 and a support member 42, the cover member 41 is disposed in the lower processing chamber 12 and has a ring shape (doughnut shape) in plan view, and when the base 15 is raised, only the peripheral edge portion of the wafer W placed on the base 15 is covered and serves as a mask for etching, and the support member 42 is annularly provided on the inner wall of the lower processing chamber 12 and supports the cover member 41. The support member 42 is configured to support the outer circumferential peripheral edge portion of the cover member 41. In the present embodiment, the support member 42 is configured to support the covering member 41 over the entire peripheral edge of the outer peripheral edge portion of the covering member 41, but is not limited thereto, and may be configured to support the covering member 41 by providing a member protruding inward at a number of positions (e.g., four points) on the inner wall of the lower treatment chamber 12, for example. In this example, the base 15 on which the wafer W is placed is configured to be moved up and down, but the present invention is not limited thereto, and the base 15 may be configured to be fixed and the cover member 41 may be moved up and down. In the present embodiment, the outer periphery covering means 40 is configured such that the planar shape of the recess 70c is etched to be circular, but the present invention is not limited thereto. For example, the outer periphery covering mechanism 40 may be configured such that the planar shape of the recess 70c is etched into a rectangular shape, a rounded quadrangle (a quadrangle with rounded corners), a polygonal shape, or the like, other than a circular shape. Thus, the recess 70c having an arbitrary shape can be formed according to the shape of the cover member 41, and there is no problem of polishing dust during polishing or the like.

In this example, the cover member 41 is made of a ceramic material such as alumina in view of etching selectivity between the cover member 41 and the wafer W, but the present invention is not limited thereto, and may be made of a material having a low dielectric constant such as quartz, yttrium, or a material obtained by coating alumina, quartz, or yttrium with a metal such as a nickel coating.

In the case of alumina, there is a disadvantage that sputtering is likely to occur at the time of etching treatment as described later, and therefore, the surface accuracy of the surface Pa of the thin plate portion 70a is deteriorated, but there is an advantage that the cover member 41 can be manufactured at low cost. In the case of yttrium, the production cost of the cover member 41 is disadvantageously high, but the sputtering is advantageous in that the product generated is easily lost, and the surface accuracy of the surface Pa of the thin plate portion 70a is not easily deteriorated. Further, in the case of quartz, there are advantages that the manufacturing cost of the covering member 41 is inexpensive compared to yttrium, and even if the above sputtering occurs, the generated product disappears and the surface accuracy of the surface Pa of the thin plate portion 70a is hardly deteriorated. Further, although quartz is etched by the etching seed, the load can be reduced by etching the covering member 41, and the thin plate portion 70a can be etched to a uniform thickness.

Next, the operation of the outer periphery covering mechanism 40 will be described.

First, in a state where the base 15 is lowered by the raising/lowering column 18, the peripheral edge portion of the cover member 41 is supported by the support member 42. At this time, the wafer W before the etching process is placed on the base 15. Then, when the base 15 and the wafer W placed thereon are lifted up by the lift pins 18 to perform etching treatment, and the cover member 41 abuts on the upper surface of the peripheral edge portion of the wafer W, the cover member 41 is lifted upward as the wafer W is lifted up. At this time, only the peripheral edge of the wafer W placed on the base 15 is covered with the covering member 41, and the covering member 41 functions as a mask during the etching process.

After the etching process is completed, the base 15 is lowered by the lift pins 18, and the cover member 41 is supported by the support member 42. In this state, the processed wafer W (semiconductor substrate 70) is carried out of the etching apparatus 1 from the inside of the etching apparatus 1, and the wafer W to be processed next is carried into the etching apparatus 1 and placed on the base 15.

By using the outer peripheral covering mechanism 40, the outer peripheral portion of the upper surface of the wafer W can be left without etching about 3mm, and only the inner region can be etched to make the inner region thinner. With this configuration, cracking or warping of the wafer W (semiconductor substrate 70) after the etching process can be reduced.

In the present embodiment, the wafer W is placed on the upper member 16, but the present invention is not limited thereto. For example, an electrostatic chuck in which an electrode plate is sandwiched by a pair of insulating layers may be used to supply an appropriate voltage to the electrode plate, thereby holding the wafer W by suction on the electrostatic chuck. In this case, the same effects as those of the present embodiment can be obtained.

The exhaust device 20 has an exhaust pipe 21 connected to a side surface of the lower chamber 12, and exhausts the gas in the chamber 11 through the exhaust pipe 21 to make the inside of the chamber 11 have a predetermined pressure.

The gas supply device 25 includes a gas supply unit 26 capable of supplying an SF6 gas as a fluorine-based gas, a gas supply unit 27 capable of supplying an O2 gas as an oxygen-based gas, and a supply pipe 29 having one end connected to the upper surface of the upper chamber 13 and the other end branched to be connected to the gas supply units 26 and 27, respectively. SF6 gas and O2 gas can be supplied from the gas supply units 26 and 27 into the processing chamber 11 through the supply pipe 29 as the processing gases.

The plasma generator 30 is a device for generating so-called Inductively Coupled Plasma (ICP), and is composed of a spiral (annular) coil 31 disposed in the upper chamber 13 and a high-frequency power supply (coil power supply unit) 32 capable of supplying high-frequency power to the coil 31, and by supplying high-frequency power to the coil 31 by the high-frequency power supply 32, the processing gas supplied into the upper chamber 13 can be made into plasma.

The high frequency power source 35 supplies high frequency power to the base 15, thereby generating a potential difference (bias potential) between the base 15 and the plasma and injecting ions generated by the plasma of the process gas onto the wafer W. Thus, the wafer W is etched. The Etching is dry Etching (anisotropic Etching or isotropic Etching) such as RIE (Reactive Ion Etching) using a reaction product gas.

Fig. 3 and 4 are vertical sectional views showing steps of a method for manufacturing the semiconductor substrate 70 shown in fig. 1(a) and 1 (b). Next, a method for manufacturing the semiconductor substrate 70 will be described with reference to these drawings.

First, a wafer W is manufactured in the following order. That is, as shown in fig. 3(a), a semiconductor substrate 70 having a plurality of elements 50 formed on one surface thereof is prepared. The semiconductor substrate 70 has a general disk shape (0.35 mm in thickness with a diameter of 76mm to 150 mm) and is made of silicon carbide.

Next, as shown in fig. 3(b), an adhesive 71 is applied to the entire surface on which the element 50 is formed by using a coater (not shown). For example, the spin coating method may be used to rotate the semiconductor substrate 70 at a high speed and spread the dropped adhesive 71 over the entire surface on which the elements 50 are formed by centrifugal force. Therefore, the adhesive 71 preferably has a moderate viscosity and can be dropped onto the semiconductor substrate 70 in a liquid state. For the adhesive 71, for example, a polyimide-based or acrylic adhesive can be used. Next, the carrier substrate 72 is bonded with the adhesive 71. The carrier substrate 72 protects the device 50. Even if the carrier substrate 72 is not attached, the element 50 may be protected by, for example, a protective coating material, and the carrier substrate 72 may not be attached.

With this configuration, the carrier substrate 72 can be attached while protecting the surface on which the element 50 is formed (see fig. 3 c). Also, after the semiconductor substrate 70 is thinned, the carrier substrate 72 can be easily peeled off.

Subsequently, the wafer W is carried into the processing chamber 11 in the etching apparatus 1 and placed on the base 15 (upper member 16) so that the surface of the semiconductor substrate 70 on which the element 50 is not formed is an upper surface. At this time, the base 15 is lowered, and the cover member 41 is supported by the support member 42. Next, as shown in fig. 3(c), the wafer W is lifted together with the base 15, and the cover member 41 is lifted upward by the outer peripheral edge of the wafer W. The outer peripheral portion of the upper surface of the wafer W is shielded by the cover member 41 to approximately 3 mm. When the wafer W is etched by the plasma in this state, only the outer peripheral portion of the upper surface of the wafer W is not etched, and only the inner region thereof is etched. In other words, the inner region of the wafer W can be thinned. Here, the inner diameter of the covering member 41 is preferably set so as to cover the outer peripheral portion of the upper surface of the semiconductor substrate 70 with a width of 1mm to 10mm in the radial direction, that is, so as to set the width of the thick plate portion (2 nd substrate region) 70b in the radial direction to 1mm to 10 mm. This is because the strength of the semiconductor substrate 70 is insufficient if the width of the thick plate portion 70b is less than 1mm, and the effective area in which the element can be formed is small if the width of the thick plate portion 70b is greater than 10 mm. Particularly, the effective area is greatly influenced by the shape, size and arrangement of each element and the shape of the recess 70c for forming the element. If the planar shape of the recess 70c is circular, the width of the thick plate portion 70b is preferably 5mm or less, but if the planar shape of the recess 70c is polygonal, the effective area of the element that can be formed may be insufficient even if 5mm or more.

Next, as shown in fig. 4(a), the upper surface of the semiconductor substrate 70 is etched using a plasma Etching technique such as RIE (Reactive Ion Etching) with the cover member 41 as a mask to form a concave portion 70 c. The etching process was carried out under conditions that SF6 gas as an etching gas was supplied into the processing chamber 11 at a flow rate of 400sccm and O2 gas as an etching additive gas was supplied into the processing chamber 11 at a flow rate of 600sccm, the coil supply power to the coil 31 was 2000W, the bias power to the base 15 was 700W, and the pressure in the processing chamber 11 was 12 Pa. The etching rate under this condition was about 6 μm/min. The O2 gas as the additive gas is expected to have an effect of improving the reactivity with carbon (C) of silicon carbide (SiC), thereby increasing the etching rate. While O2 gas is used as the etching additive gas, the etching may be performed using only SF6 gas, which is an etching gas, instead of O2 gas.

The power supplied to the coil is preferably 400 to 5000W, and more preferably 1500W or more particularly from the viewpoint of plasma stability. The bias power is preferably 50 to 1000W, and more preferably 500W or more, particularly from the viewpoint of plasma stability. The pressure in the chamber is preferably 0.5 to 50Pa, and more preferably 3 to 30Pa from the viewpoint of in-plane uniformity of the etching amount.

After the recess 70c having a predetermined depth is formed by etching the upper surface of the semiconductor substrate 71 in this manner, the series of etching steps is terminated, and the wafer W is carried out from the processing chamber 11. Thereafter, a back electrode is formed by a sputtering apparatus or the like.

According to the method for making a thin plate, the conventional polishing process is not required. Therefore, it is not necessary to perform a stress relieving treatment such as CMP for removing polishing distortion such as a grinding layer generated during polishing, and the manufacturing time and manufacturing cost can be reduced. Furthermore, even when the recess of the small rectangular region is thinned, the shape of the covering can be easily changed.

In this example, a mechanism for covering the non-etching portion is provided on the etching apparatus 1 side, but the present invention is not limited to this. For example, the mechanism for covering the non-etched portion may be mounted on the wafer W.

Next, as shown in fig. 4(b), after the carrier substrate 72 is peeled off from the adhesive 71, the adhesive 71 is removed.

According to the semiconductor substrate 70 of the present embodiment thus manufactured, the thickness of the outer peripheral portion (the 2 nd substrate region) of the semiconductor substrate 70 can be made thick, and the thickness of only the inner region (the 1 st substrate region) where the elements are formed can be made thin, so that cracking or warping of the semiconductor substrate 70 can be reduced. Since the semiconductor substrate 70 on which the element 50 is formed is made of silicon carbide and has a thickness as low as possible (10 μm or more and 50 μm or less) that can withstand a high withstand voltage, the loss can be further reduced as compared with an element made of silicon.

Further, according to the method for manufacturing the semiconductor substrate 70 of this embodiment, the semiconductor substrate 70 made of silicon carbide having high hardness can be thinned by plasma etching without relying on mechanical polishing, so that the semiconductor substrate has high withstand voltage performance and the thickness is minimized (10 μm to 50 μm). Therefore, expensive grinding stones for grinding are not required, and thus the manufacturing cost can be greatly reduced.

Embodiment 2

Next, embodiment 2 of the present invention will be described with reference to fig. 5. FIG. 5 is a sectional view showing a schematic configuration of an etching apparatus 1A according to embodiment 2. Compared with the etching apparatus 1 shown in fig. 2, the etching apparatus 1A is different from the etching apparatus 1 in the structure of the depth monitor 43 having a spectroscopic type, so that the etching depth of the wafer W can be measured (monitored) in real time. Therefore, in fig. 5, the same structural parts as those of the etching apparatus 1 shown in fig. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted below.

The depth monitor 43 has a depth sensor 44 and a processing unit 45. The depth sensor 44 includes a light source (not shown) for emitting multi-wavelength light for irradiating the etching surface of the wafer W and the cover member 41 with white light, a light receiving unit (not shown) for receiving reflected light from the wafer W and the cover member 41, and a spectrophotometer (not shown), and acquires a depth signal varying depending on the etching depth and outputs the depth signal to the processing unit 45.

The depth sensor 44 is installed on the upper surface of the upper chamber 13, and is disposed opposite to the wafer W and the surface of the cover member 41. In the etching process of the wafer W, the wafer W and the cover member 41 are irradiated with white light from the light source, and the light receiving part receives reflected light from the wafer W and the cover member 41. The spectrophotometer can measure the intensity of the reflected light at each wavelength within a predetermined wavelength range, and send the obtained light intensity data to the processing section 45. The light intensity data is a depth signal reflecting the etching depth, and varies depending on the etching depth. The processing unit 45 generates a spectrum indicating the light intensity for each wavelength from the light intensity data, and calculates the etching depth from the spectrum based on the phase difference between the reflected light reflected from the etched surface of the wafer W and the covering member 41.

Here, the reflected light reflected by the wafer W and the reflected light reflected by the cover member 41 interfere with each other. Since the interference pattern of the optical wave changes depending on the depth of the wafer W, the etching depth can be calculated from the change.

According to the manufacturing method of the semiconductor substrate 70 using the etching apparatus 1A of the present embodiment, the same effects as those of the manufacturing method using the etching apparatus 1 of embodiment 1 can be obtained. In addition, since the etching apparatus 1A of the present embodiment can further monitor the etching depth in real time and identify the etching end point based on the etching rate and the etching time, the etching process can be started without a pre-step of calculating the etching rate by measuring the etching amount in advance. Therefore, the manufacturing time can be significantly reduced compared to the etching apparatus 1 of embodiment 1.

While the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments.

For example, in the above example, the semiconductor substrate 70 is silicon carbide having a crystal structure of 4H-SiC, but the material of the semiconductor substrate 70 is not limited to this silicon carbide, and for example, silicon carbide (6H-SiC, 3C-SiC), gallium nitride (GaN), gallium oxide (GaO), diamond (C), or the like having a crystal structure other than 4H-SiC may be used. In this case, the same effects as those of the present embodiment can be obtained.

In the above example, the semiconductor substrate of the present invention was manufactured using the etching apparatuses 1 and 1A, but the manufacturing method of the present invention may be performed using an etching apparatus having another structure. In the above example, after the element 50 is formed on the semiconductor substrate 70, the inner region (the 1 st substrate region) of the semiconductor substrate 70 where the element 50 is formed is thinned. For example, after thinning the inner region (the 1 st substrate region) of the semiconductor substrate 70, the element 50 may be formed in the thinned region (thin plate portion).

Further, even when a chlorine-based gas such as Cl2 gas, BCl3 gas, CCl4 gas, SiCl4 gas, or the like is used instead of the fluorine-based gas (SF6 gas) used as the etching gas in the above example, the same effects as those of the above-described manufacturing method can be obtained.

In the above example, the description has been made of an example in which the etching apparatus 1 or 1A is provided with the covering means that can cover only the peripheral portion of the semiconductor substrate 70 without etching the same, but the present invention is not limited to this. For example, a case in which the wafer W can be placed may be used, and a lid may be provided on the case side to cover the outer peripheral edge portion of the semiconductor substrate 70 so as not to be etched, or an etching mask such as a resist mask, an oxide film mask, or a metal mask may be formed on the outer peripheral edge portion of the semiconductor substrate 70 so as not to be etched.

Further, in the above example, the etching treatment is performed in a state where the cover member 41 is placed on the semiconductor substrate 70, but the manufacturing apparatus (etching apparatus) and the manufacturing method of the present invention are not limited to this configuration, and as shown in fig. 6, the etching apparatuses 1 and 1A may be configured such that the cover member 41 is supported by the support member 42, and when the base 15 reaches the rising end, a gap g is generated between the upper surface of the semiconductor substrate 70 and the lower surface of the cover member 41, and the manufacturing method may be configured such that the etching treatment is performed in a state where the gap g is formed between the upper surface of the semiconductor substrate 70 and the lower surface of the cover member 41.

When the semiconductor substrate 70 is etched in a state where a bias potential is applied to the base 15, when the cover member 41 comes into contact with the semiconductor substrate 70, the cover member 41 is also biased by a material (for example, alumina) of the cover member 41, and the cover member 41 is sputtered by ions in the plasma, and the resultant is attached to the surface of the thin plate portion 70a (concave portion 70c) which is the inner region of the semiconductor substrate 70, thereby deteriorating the surface accuracy. Therefore, by providing the gap g between the semiconductor substrate 70 and the cover member 41, the cover member 41 can be prevented from generating a bias potential, and thus the deterioration of the surface accuracy of the upper surface of the thin plate portion 70a due to sputtering of the cover member 41 can be prevented.

The gap g between the semiconductor substrate 70 and the cover member 41 is preferably 0.5mm to 3 mm. This is because when the gap is less than 0.5mm, the generation of the bias potential in the covering member 41 cannot be effectively prevented, and when the gap is 3mm or more, the etching seed crystal intrudes between the semiconductor substrate 70 and the covering member 41, so that the region (2 nd substrate region) covered with the covering member 41 of the semiconductor substrate 70 is etched, and the inner peripheral edge portion (shoulder portion) of the 2 nd substrate region (thick plate portion) is etched, and the shape of the obtained semiconductor substrate 70 is deteriorated.

The semiconductor substrate 70 may have 1 or more protruding portions protruding inward in the radial direction in the 2 nd substrate region (thick plate portion). Fig. 7 shows a semiconductor substrate having the protruding portion. The semiconductor substrate 70 'shown in fig. 7 has 3 protruding portions H, and the 3 protruding portions H are arranged at equal intervals in the circumferential direction of the 2 nd substrate region 70' b. For example, in the step of peeling the carrier substrate 72 or the step of removing the adhesive 71, when the thin plate portion 70 'a is supported by the support pin when the semiconductor substrate 70' is supported from the side of the concave portion 70 'c, the thickness of the thin plate portion 70' a is extremely thin, and therefore the support portion may be penetrated by the support pin. Therefore, by forming the protruding portion H protruding inward on the thick plate portion (2 nd substrate region) 70' b, the protruding portion H having a large thickness can be supported by the support pin. Thus, the area of the thin plate portion 70 'a can be enlarged as much as possible to increase the number of elements to be obtained, and the problem that the semiconductor substrate 70' is penetrated by the support pin can be prevented. The number of the protrusions H is not particularly limited, but it is preferable that 3 or more protrusions H are formed and arranged at equal intervals in the circumferential direction of the 2 nd substrate region 70 'b from the viewpoint of stably supporting the semiconductor substrate 70'.

In order to form the protrusions H, the cover member 41 of the etching apparatuses 1 and 1A also needs to have 1 or more (preferably 3 or more) protrusions protruding inward in the radial direction, and when a plurality of protrusions are provided, they are preferably arranged at equal intervals in the circumferential direction. For the sake of safety, the covering member having the above-described protrusion is shown in fig. 8. In fig. 8, reference numeral 41 'denotes a cover member, and reference numeral H' denotes a protrusion.

It is to be reiterated that the above embodiments are merely illustrative, and various modifications can be made to the specific aspects of the present invention without departing from the scope thereof.

List of reference numerals:

1. 1A etching device

11 treatment chamber

15 base station

20 air exhausting device

25 gas supply device

26. 27 gas supply part

30 plasma generating device

31 coil

32. 35 high frequency power supply

41 cover member

42 support member

43 depth monitor

44 depth sensor

45 treatment section

50 element

70 (wide energy gap) semiconductor substrate

70a thin plate part (1 st substrate area)

70b thick plate part (No. 2 base plate area)

70c recess

71 adhesive

72 carrier substrate

W wafer