阅读说明：本技术 一种周期变化范围限制及过采样结合的同步信号抗干扰方法 (Synchronous signal anti-interference method combining periodic variation range limitation and oversampling ) 是由 赵先元 乐绪鑫 王瑞清 马小高 刘钰琦 刘荆飞 于 2020-10-28 设计创作，主要内容包括：本发明提供一种周期变化范围限制及过采样结合的同步信号抗干扰方法,包括以下具体步骤：S1.设置同步信号上升沿触发定时器中断；S2.在同步中断中记录中断时刻,并计算当前时刻与上一次同步中断的时间差,如果时间差小于同步信号周期的90％则认为当前中断源于外部干扰,不记录中断时刻,不计算周期；S3.如果时间差大于同步信号周期的90％,则记录中断时刻和时间差,启动定时采样,读取连续3次同步信号对应的引脚电平；S4.如果连续3次得到的同步信号对应的引脚电平全部是高电平则确认同步信号上升沿有效,以此同步信号上升沿时刻作为全控整流桥控制角α对应的延时起点。本发明增强全控整流桥控制器对于同步信号的抗干扰能力。(The invention provides a synchronous signal anti-interference method combining cycle variation range limitation and oversampling, which comprises the following steps: s1, setting a rising edge of a synchronous signal to trigger a timer to interrupt; s2, recording interruption time in synchronous interruption, calculating the time difference between the current time and the last synchronous interruption, and if the time difference is less than 90% of the synchronous signal period, determining that the current interruption is caused by external interference, not recording the interruption time, and not calculating the period; s3, if the time difference is larger than 90% of the period of the synchronous signal, recording the interruption time and the time difference, starting timing sampling, and reading the pin level corresponding to the synchronous signal for 3 times continuously; and S4, if all pin levels corresponding to the synchronous signals obtained for 3 times are high levels, determining that the rising edge of the synchronous signals is effective, and taking the rising edge moment of the synchronous signals as a delay starting point corresponding to the control angle alpha of the fully-controlled rectifier bridge. The invention enhances the anti-interference capability of the full-control rectifier bridge controller on the synchronous signals.)

1. A synchronization signal anti-interference method combining cycle variation range limitation and oversampling is characterized by comprising the following specific steps:

s1, firstly, connecting the synchronous signal after isolation and shaping into a timer of a rectifier bridge controller CPU, and setting the rising edge of the synchronous signal to trigger the timer to interrupt;

s2, recording interruption time in synchronous interruption, calculating the time difference between the current time and the last synchronous interruption, and if the time difference is less than 90% of the period of the synchronous signal, considering that the current interruption is caused by external interference, not recording the interruption time, not calculating the period, and not starting oversampling interruption to further verify the synchronous signal;

s3, if the time difference is larger than 90% of the period of the synchronous signal, recording the interruption time and the time difference, starting timing sampling, reading pin levels corresponding to the synchronous signals for 3 times continuously, and verifying the synchronous signals in the second stage;

and S4, if all pin levels corresponding to the synchronous signals obtained for 3 times are high levels, determining that the rising edge of the synchronous signals is effective, and taking the rising edge moment of the synchronous signals as a delay starting point corresponding to the control angle alpha of the fully-controlled rectifier bridge.

2. The method of claim 1, wherein in step S2, any interrupt signal occurring in the time difference between the interrupt time and the last sync interrupt is considered as an interference, and the peak interference in the high level phase of the sync signal is completely shielded to implement the filtering of the sync range limitation.

3. The method of claim 1, wherein the sampling period of the timing sampling in step S3 is 40 μ S, and the oversampling time is 120 μ S.

Technical Field

The invention belongs to the field of power conversion, and particularly relates to a synchronous signal anti-interference method combining cycle variation range limitation and oversampling.

Background

As shown in FIG. 1, the relationship between the input voltage and the output voltage of the three-phase fully-controlled rectifier bridge can be expressed as

U_out＝1.35U_incosα

Where α is the rectifier bridge control angle and Uin is the effective value of the input anode voltage.

The three-phase rectifier bridge control needs a synchronous signal to determine the starting time of each period, and the rising edge time of the trigger pulse is ensured to be matched with the control angle alpha.

After amplitude reduction and isolation of the input anode voltage synchronous transformer, the input anode voltage synchronous transformer is generally shaped into a square wave signal through a synchronous shaping circuit to serve as a synchronous signal accessed by a CPU (central processing unit) of the controller. The phase relationship between the anode voltage, the synchronization signal and the trigger pulse obtained by using the zero-crossing point of the rising edge of the input voltage of the fully-controlled rectifier bridge corresponding to the discontinuity point (rising edge) of the synchronization signal as the starting point of the period is shown in fig. 2.

The time difference of two adjacent rising edges of the synchronous signal 2 is the period T of the sine wave, the time difference between the trigger pulse and the rising edge of the synchronous signal in the period is dT, and the controller ensures that the trigger pulse is matched with the control angle alpha by setting the delay dT of the trigger pulse. dT and bridge control angle can be expressed as

dT＝T×α/360

The synchronization signal is typically a square wave signal with a duty cycle of about 50%, as shown in fig. 3 a. The spike interference in series occurs randomly, and may occur in a high level portion, such as the first spike interference in fig. 3b, or in a low level portion, such as the second spike interference in fig. 3 b.

The synchronous signal is generally accessed to a timer of a CPU of a full-control rectifier bridge controller, the rising edge of the synchronous signal is used for triggering interruption, dT delay interruption corresponding to a trigger angle alpha is set in the synchronous interruption, and then trigger pulses in the period are sequentially output. If the dT delay interrupt is initiated using a rising edge generated by a glitch spike, the delay in the time of the output trigger pulse relative to the anode voltage zero crossing will not match the trigger angle α set by the controller, resulting in an uncontrolled output.

The current synchronization signal is generally subjected to interference and burr elimination by hardware of an isolation shaping circuit, and interference signal fault-tolerant shielding is not performed in a synchronization interrupt response program. However, in practical engineering applications, the interference of the synchronization signal cannot be filtered out by hardware for some special reasons, for example, the interference of a strong current circuit is directly coupled to a weak current signal circuit, and randomly occurring peak interference is generated in the synchronization square wave, which requires an anti-interference measure to be enhanced in software.

Disclosure of Invention

The present invention is directed to solve the above problems and provide a synchronization signal anti-interference method combining the limitation of the period variation range and oversampling, wherein the peak interference occurring at the high level stage of the synchronization square wave is shielded by the limitation of the period variation range, and the level of the synchronization signal is sampled for a plurality of times at the rising edge occurring at the low level stage of the synchronization square wave to shield the peak interference.

The technical scheme of the invention is as follows:

a synchronization signal anti-interference method combining cycle variation range limitation and oversampling comprises the following specific steps:

s1, firstly, connecting the synchronous signal after isolation and shaping into a timer of a rectifier bridge controller CPU, and setting the rising edge of the synchronous signal to trigger the timer to interrupt;

s2, recording interruption time in synchronous interruption, calculating the time difference between the current time and the last synchronous interruption, and if the time difference is less than 90% of the period of the synchronous signal, considering that the current interruption is caused by external interference, not recording the interruption time, not calculating the period, and not starting oversampling interruption to further verify the synchronous signal;

s3, if the time difference is larger than 90% of the period of the synchronous signal, recording the interruption time and the time difference, starting timing sampling, reading pin levels corresponding to the synchronous signals for 3 times continuously, and verifying the synchronous signals in the second stage;

and S4, if all pin levels corresponding to the synchronous signals obtained for 3 times are high levels, determining that the rising edge of the synchronous signals is effective, and taking the rising edge moment of the synchronous signals as a delay starting point corresponding to the control angle alpha of the fully-controlled rectifier bridge.

In step S2, any interrupt signal occurring in the time difference between the interrupt time and the last sync interrupt is considered as interference, so that the spike interference at the high level stage of the sync signal is completely shielded to realize the sync range limitation filtering.

The sampling period of the timing sampling in the step S3 is 40 μ S, and the oversampling time is 120 μ S.

Compared with the prior art, the invention has the beneficial effects that: the peak interference occurring at the high level stage of the synchronous square wave is shielded through the limitation of the periodic variation range, the level of the synchronous signal is sampled for multiple times at the rising edge occurring at the low level stage of the synchronous square wave to shield the peak interference, and the anti-interference capability of the full-control bridge rectifier controller on the synchronous signal is enhanced.

Drawings

Fig. 1 is a schematic structural diagram of a fully controlled rectifier bridge of the present invention.

Fig. 2 is a theoretical phase relationship of the input voltage, the synchronization signal and the trigger pulse.

Fig. 3a is a diagram of a normal synchronization signal.

Fig. 3b is a diagram of a disturbed synchronization signal.

FIG. 4 is a flow chart of the present invention for synchronizing interrupts.

FIG. 5 is a diagram of the refractory areas resulting from the cycle range limitation of the present invention.

Fig. 6 is a graph of the oversampling result anomalous masking spike interference of the present invention.

Fig. 7 is a flow chart of an oversampling implementation of the present invention.

Fig. 8 is a flow chart of a method of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 8, a synchronization signal anti-interference method combining cycle variation range limitation and oversampling includes the following steps:

s1, connecting the synchronous signal after isolation and shaping into a timer of a rectifier bridge controller CPU, and setting a rising edge of the synchronous signal to trigger the timer to interrupt;

s2, recording interruption time in synchronous interruption, calculating the time difference between the current time and the last synchronous interruption, and if the time difference is less than 90% of the period of the synchronous signal, considering that the current interruption is caused by external interference, not recording the interruption time, not calculating the period, and not starting oversampling interruption to further verify the synchronous signal;

s3, if the time difference is larger than 90% of the period of the synchronous signal, recording the interruption time and the time difference, starting timing sampling, reading pin levels corresponding to the synchronous signals for 3 times continuously, and verifying the synchronous signals in the second stage;

and S4, if all pin levels corresponding to the synchronous signals obtained for 3 times are high levels, determining that the rising edge of the synchronous signals is effective, and taking the rising edge moment of the synchronous signals as a delay starting point corresponding to the control angle alpha of the fully-controlled rectifier bridge.

As shown in fig. 4, the interrupt time is recorded in the sync interrupt, and the time difference between the current time and the last sync interrupt is calculated, if the time difference is less than 90% of the period, the current interrupt is considered to be caused by external interference, the interrupt time is not recorded, the period is not calculated, and oversampling interrupt is not started to further verify the sync signal. As shown in fig. 5, this corresponds to the opening of a refractory period after receiving a valid sync interrupt, during which any interrupt signal present is considered to be a disturbance.

If the time difference meets the requirement, recording the interruption time (used for the next calculation of the synchronous interruption time difference) and the time difference, and starting 40 mu s timed interruption to carry out the second stage verification on the synchronous signal.

Because the duty ratio of the synchronous square wave is about 50%, the time difference between the current synchronous interruption and the last synchronous interruption is greater than 90% of the period, as shown in fig. 5, the spike interference in the high level stage of the synchronous signal is completely shielded, so after the filtering of the synchronization range limitation, if the synchronous interruption is caused by interference, the spike interference in the low level stage of the synchronous signal, as shown in fig. 6, is certain to occur. If the spike interference width is less than 120 mus, then the low level signal of the sync input is captured by the 3-time oversampling interrupt, and the sync interrupt response such as periodic refresh, control angle delay interrupt setting, etc. is masked accordingly.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.