Delay chain circuit for simulating FIR filter and implementation method thereof
阅读说明：本技术 一种用于模拟fir滤波器的延迟链电路及其实现方法 (Delay chain circuit for simulating FIR filter and implementation method thereof ) 是由 秦大威 王丽芳 金锐 于 2020-11-03 设计创作，主要内容包括：本发明涉及模拟集成电路设计技术领域,提供了一种用于模拟FIR滤波器的延迟链电路及其实现方法。按照vs1、…、vsn-1顺序构成第一组输出子信号,且按照相应排列顺序分别与延迟链电路的n-1个输出端口相连,受所述开关控制信号ck0控制；按照vs2、…、vsn-1、vs0顺序构成第二组输出子信号,且按照相应排列顺序分别与延迟链电路的n-1个输出端口相连,受所述开关控制信号ck1控制；按照上述构成第一组输出子信号和第二组输出子信号的关系,完成剩余的n-2组输出子信号和相应开关的配组。本发明的电路相比于上述延迟链电路,提升了所获得的延迟副本的信号质量,显著缩小了集成电路芯片面积。(The invention relates to the technical field of analog integrated circuit design, and provides a delay chain circuit for an analog FIR filter and an implementation method thereof. Forming a first group of output sub-signals according to the sequence of vs1, … and vsn-1, respectively connecting the output sub-signals with n-1 output ports of the delay chain circuit according to the corresponding arrangement sequence, and controlling the output sub-signals by the switch control signal ck 0; a second group of output sub-signals are formed according to the sequence of vs2, …, vsn-1 and vs0, are respectively connected with n-1 output ports of the delay chain circuit according to the corresponding arrangement sequence and are controlled by the switch control signal ck 1; and completing the matching of the remaining n-2 groups of output sub-signals and corresponding switches according to the relationship between the first group of output sub-signals and the second group of output sub-signals. Compared with the delay chain circuit, the circuit of the invention improves the signal quality of the obtained delay copy and obviously reduces the area of an integrated circuit chip.)
1. A delay chain circuit for an analog FIR filter is characterized by comprising n sample-hold amplifying circuits, wherein the input ends of the n sample-hold amplifying circuits are connected with the same input signal Vin and are respectively controlled by a switch control signal ck 0-a switch control signal ckn-1, and n preset delay signals vs0, vs1, … and vsn-1 are formed at the output ends of the n sample-hold amplifying circuits, wherein n is a natural number greater than or equal to 2, specifically:
a first group of output sub-signals are formed according to the sequence of vs1, … and vsn-1 and are respectively connected with n-1 output ports of the delay chain circuit according to the corresponding arrangement sequence, and the connection and disconnection between the first group of output sub-signals and the output ports of the delay chain circuit are controlled by the switch control signal ck 0;
a second group of output sub-signals are formed according to the sequence of vs2, …, vsn-1 and vs0 and are respectively connected with n-1 output ports of the delay chain circuit according to the corresponding arrangement sequence, and the connection and disconnection between the second group of output sub-signals and the output ports of the delay chain circuit are controlled by the switch control signal ck 1;
completing the matching of the remaining n-2 groups of output sub-signals and corresponding switches according to the relationship between the first group of output sub-signals and the second group of output sub-signals; at each moment, only one control level in the switch control signals ck 0-ckn-1 is at a high level, the other n control levels are at low levels, and the high level circularly moves as a period according to the sequential switch control signals ck0, ck1,.. ckn-1;
the number of output ports of the delay chain circuit is n-1; when the control level of the switch is at a high level, the signal is conducted with the port; when the control level is at a low level, the signal is disconnected from the port.
2. The delay chain circuit for an analog FIR filter according to claim 1, wherein the number of the sample-hold amplification circuits is set according to the number of output ports of the delay chain circuit to be realized, wherein the number of the sample-hold amplification circuits is set to n when the number of the output ports of the delay chain circuit is n-1.
3. The delay chain circuit for an analog FIR filter according to claim 1, wherein said sample-and-hold amplification circuit comprises a sampling switch, a storage capacitor and an integrated amplification circuit, in particular:
the corresponding sampling switch is arranged between the input port of the integrated amplifying circuit and the signal input port of the corresponding sample-hold amplifying circuit and is used for completing the connection and disconnection between the signal input port of the sample-hold amplifying circuit and the input end of the integrated amplifying circuit under the driving of the first control signal;
the energy storage capacitor is arranged on the other side, opposite to the sampling switch, of the input end of the integrated amplification circuit, and a connection node of the energy storage capacitor is positioned between the sampling switch and the input end of the integrated amplification circuit and used for storing a voltage signal acquired from a signal input port of the sample-and-hold amplification circuit when the sampling switch is closed; when the sampling switch is switched off, the stored voltage signal is amplified by the output end of the integrated amplifying circuit;
the sampling switches in the sampling-holding amplification circuits are respectively controlled by the switch control signals ck 0-ckn-1.
4. Delay chain circuit for analog FIR filters according to claim 1, characterized in that at said n is 5, the respective n preset delay signals are in particular vs0, vs1, vs2, vs3 and vs4, the switch control signals are in particular ck0, ck1, ck2, ck3 and ck 4; the switch control signals ck0, ck1, ck2, ck3, and ck4 are respectively used for controlling the on and off of the corresponding sample-hold amplifying circuit and the input signal Vin, so that the remaining n-2 groups of output sub-signals and the corresponding switches are matched according to the relationship between the first group of output sub-signals and the second group of output sub-signals, which specifically includes:
forming a third group of output sub-signals according to the sequence of vs3, vs4, vs0 and vs1, and respectively connecting the output sub-signals with 4 output ports of the delay chain circuit according to the corresponding arrangement sequence, wherein the connection and disconnection between the third group of output sub-signals and the output ports of the delay chain circuit are controlled by the switch control signal ck 2;
forming a fourth group of output sub-signals according to the sequence of vs4, vs0, vs1 and vs2, and respectively connecting the fourth group of output sub-signals with 4 output ports of the delay chain circuit according to the corresponding arrangement sequence, wherein the fourth group of output sub-signals is controlled by the switch control signal ck3 to be connected and disconnected with the output ports of the delay chain circuit;
and a fifth group of output sub-signals are formed according to the sequence of vs0, vs1, vs2 and vs3 and are respectively connected with 4 output ports of the delay chain circuit according to the corresponding arrangement sequence, and the fifth group of output sub-signals are switched on and off with the output ports of the delay chain circuit and are controlled by the switch control signal ck 4.
5. The delay chain circuit for analog FIR filter according to claim 4, characterized in that the generating circuit of the switch control signal ck 0-ckn-1 is composed of five D flip-flops D0-D4, specifically:
the D trigger D0 is a D trigger with a SET end SET, the input end D is connected with a switch control signal ck4, the output end Q is used as a switch control signal ck0, and the SET end is connected with a reset signal reset; when reset is at a high level, the switch control signal ck0 at the output end of the D flip-flop D0 is at a high level, and when reset is at a low level, the D flip-flop D0 works normally;
the D trigger D1 is a D trigger with a clearing end CLR, the input end D is connected with a switch control signal ck0, the output end Q is used as a switch control signal ck1, and the clearing end is connected with a reset signal reset; when reset is at a high level, the switch control signal ck1 at the output end of the D flip-flop D1 is at a low level, and when reset is at a low level, the D flip-flop D0 works normally;
the D trigger D2 is a D trigger with a clearing end CLR, the input end D is connected with a switch control signal ck1, the output end Q is used as a switch control signal ck2, and the clearing end is connected with a reset signal reset; when reset is at a high level, the switch control signal ck2 at the output end of the D flip-flop D2 is at a low level, and when reset is at a low level, the D flip-flop D2 works normally;
the D trigger D3 is a D trigger with a clearing end CLR, the input end D is connected with a switch control signal ck2, the output end Q is used as a switch control signal ck3, and the clearing end is connected with a reset signal reset; when reset is at a high level, the switch control signal ck3 at the output end of the D flip-flop D3 is at a low level, and when reset is at a low level, the D flip-flop D3 works normally;
the D trigger D4 is a D trigger with a clearing end CLR, the input end D is connected with a switch control signal ck3, the output end Q is used as a switch control signal ck4, and the clearing end is connected with a reset signal reset; when reset is at high level, the switch control signal ck4 at the output terminal of the D flip-flop D4 is at low level, and when reset is at low level, the D flip-flop D4 operates normally.
6. The method for realizing the delay chain circuit of the analog FIR filter is characterized by comprising n sample-hold amplifying circuits, wherein the input ends of the n sample-hold amplifying circuits are connected with the same input signal Vin and are respectively controlled by a switch control signal ck 0-a switch control signal ckn-1, and n sample-hold amplifying circuits are formed at the output ends of the n sample-hold amplifying circuits; the output signals of the output ends of the n sampling holding amplifying circuits are vs0, vs1, … and vsn-1; forming a first group of output sub-signals according to the sequence of vs1, … and vsn-1, and respectively connecting the output sub-signals with n-1 output ports of the delay chain circuit according to the corresponding arrangement sequence, wherein the first group of output sub-signals is controlled by a switch control signal ck 0; a second group of output sub-signals are formed according to the sequence of vs2, …, vsn-1 and vs0 and are respectively connected with n-1 output ports of the delay chain circuit according to the corresponding arrangement sequence, and the second group of output sub-signals are controlled by a switch control signal ck 1; completing the matching of the remaining n-2 groups of output sub-signals and corresponding switches according to the relationship between the first group of output sub-signals and the second group of output sub-signals, wherein n is a natural number greater than or equal to 2, and the method comprises the following steps:
setting a first control signal of a preset cyclic sampling delay conduction time window for each of the sampling switch control signals ck 0-ckn-1, so that n preset delay signals vs0, vs1, … and vsn-1 are formed at the output ends of the n sampling holding amplification circuits;
in the first control signal, only one control level of the switch control signals ck 0-ckn-1 at each time is at a high level, the other n control levels are at low levels, and the high level cyclically moves as a period in the sequence of ck0, ck1,.. and ckn-1.
7. The method of claim 6, wherein when n is 5, the corresponding 5 preset delay signals are vs0, vs1, vs2, vs3 and vs4 respectively output from the integrated amplifier A10, the integrated amplifier A11, the integrated amplifier A12, the integrated amplifier A13 and the integrated amplifier A14; the first control signals ck0, ck1, ck2, ck3 and ck4 are respectively used for controlling the on and off of the sampling switch S10, the sampling switch S11, the sampling switch S12, the sampling switch S13 and the sampling switch S14, and specifically include:
the sampling switches S10, S11, S12, S13 and S14 are respectively arranged between the input ports of the integrated amplifying circuits A10, A11, A12, A13 and A14 and the signal input ports of the respectively affiliated sampling holding amplifying circuits;
the first control signals ck0, ck1, ck2, ck3 and ck4 control the sampling switches S10, S11, S12, S13 and S14 to be switched on and off, and the signal input ports of the sampling and holding amplification circuits are switched on and off with the input ends of the respective integrated amplification circuits, so that preset delay signals vs0, vs1, vs2, vs3 and vs4 are formed.
8. The method of claim 7, wherein the method specifically comprises:
at the time of t0, when the ck0 changes from low level to high level, the sampling switch S10 is turned on, and the energy storage capacitor C10 on the integrated amplifier a10 side samples the signal input port Vin; at time t1, ck0 is changed from high level to low level, a sampling switch S10 in front of an integrated amplifier a10 is turned off, sampling is finished, the voltage on C10 keeps a sampled voltage vt1 in a period when ck0 is low level, the gain of the integrated amplifier a10 is g10, and vs0 is g10 × vt 1;
at the time of t1, when the ck1 changes from low level to high level, the sampling switch S11 is turned on, and the energy storage capacitor C11 on the integrated amplifier a11 side samples the signal input port Vin; at time t2, ck1 is changed from high level to low level, a sampling switch S11 in front of an integrated amplifier a11 is turned off, sampling is finished, the voltage on C11 keeps a sampled voltage vt2 in a period when ck1 is low level, the gain of the integrated amplifier a11 is g11, and vs1 is g11 × vt 2;
at the time of t2, when the ck2 changes from low level to high level, the sampling switch S12 is turned on, and the energy storage capacitor C12 on the integrated amplifier a12 side samples the signal input port Vin; at time t3, ck2 is changed from high level to low level, a sampling switch S12 in front of the integrated amplifier a12 is turned off, sampling is finished, the voltage on C12 keeps a sampled voltage vt3 in a period when ck2 is low level, and the gain of the integrated amplifier a12 is g12, so that vs2 is g12 × vt 3;
at the time of t3, when the ck3 changes from low level to high level, the sampling switch S13 is turned on, and the energy storage capacitor C13 on the integrated amplifier a13 side samples the signal input port Vin; at time t4, ck3 is changed from high level to low level, a sampling switch S13 in front of the integrated amplifier a13 is turned off, sampling is finished, the voltage on C13 keeps a sampled voltage vt4 in a period when ck3 is low level, and the gain of the integrated amplifier a13 is g13, so that vs3 is g13 × vt 4;
at the time of t4, ck4 is changed from low level to high level, a sampling switch S14 in front of an integrated amplifier a14 is turned on, and an energy storage capacitor C14 on the integrated amplifier a14 side samples a signal input port Vin;
at time t4, the output switch of the fifth of the m sub-output ports owned by each sample-hold amplifier circuit is turned on, and the output port of each delay chain circuit is represented as: v0 ═ vs3 ═ vt4, v1 ═ vs2 ═ vt3, v2 ═ vs1 ═ vt0, v3 ═ vs0 ═ vt 1;
at time t5, ck4 changes from high level to low level, the sampling switch S14 is turned off, the sampling is finished, the voltage on C14 keeps the sampled voltage vt5 in the period when ck4 is low level, and the gain of a14 is g14, so that vs4 is g14 vt 5;
at time t5, ck0 changes from low level to high level, the output switch of the first of the m sub-output ports owned by each controlled sample-hold amplifying circuit is turned on, and the output ports of each delay chain circuit appear as: v0 ═ vs4 ═ vt5, v1 ═ vs3 ═ vt4, v2 ═ vs2 ═ vt3, v3 ═ vs1 ═ vt 2;
at the time t5, ck0 changes from low level to high level again, S10 is turned on again, and C10 samples the signal input port Vin again;
and circulating according to the change process at the time t0-t 5.
9. The method of claim 7, wherein the method specifically comprises:
the control end of the output switch S20 is ck0, the input end of the switch is vs1, and the output end of the switch is v 3;
the control end of the output switch S21 is ck0, the input end of the switch is vs2, and the output end of the switch is v 2;
the control end of the output switch S22 is ck0, the input end of the switch is vs3, and the output end of the switch is v 1;
the control end of the output switch S23 is ck0, the input end of the switch is vs4, and the output end of the switch is v 0;
the control end of the output switch S24 is ck1, the input end of the switch is vs2, and the output end of the switch is v 3;
the control end of the output switch S25 is ck1, the input end of the switch is vs3, and the output end of the switch is v 2;
the control end of the output switch S26 is ck1, the input end of the switch is vs4, and the output end of the switch is v 1;
the control end of the output switch S27 is ck1, the input end of the switch is vs0, and the output end of the switch is v 0;
the control end of the output switch S28 is ck2, the input end of the switch is vs3, and the output end of the switch is v 3;
the control end of the output switch S29 is ck2, the input end of the switch is vs4, and the output end of the switch is v 2;
the control end of the output switch S30 is ck2, the input end of the switch is vs0, and the output end of the switch is v 1;
the control end of the output switch S31 is ck2, the input end of the switch is vs1, and the output end of the switch is v 0;
the control end of the output switch S32 is ck3, the input end of the switch is vs4, and the output end of the switch is v 3;
the control end of the output switch S33 is ck3, the input end of the switch is vs0, and the output end of the switch is v 2;
the control end of the output switch S34 is ck3, the input end of the switch is vs1, and the output end of the switch is v 1;
the control end of the output switch S35 is ck3, the input end of the switch is vs2, and the output end of the switch is v 0;
the control end of the output switch S36 is ck4, the input end of the switch is vs0, and the output end of the switch is v 3;
the control end of the output switch S37 is ck4, the input end of the switch is vs1, and the output end of the switch is v 2;
the control end of the output switch S38 is ck4, the input end of the switch is vs2, and the output end of the switch is v 1;
the control end of the output switch S39 is ck4, the input end of the switch is vs3, and the output end of the switch is v 0.
10. The method of claim 9, wherein the method comprises:
when ck0 is high, the output switches S20, S21, S22 and S23 are closed; when ck0 is at low level, the output switches S20, S21, S22 and S23 are turned off;
when ck1 is high, the output switches S24, S25, S26 and S27 are closed; when ck1 is at low level, the output switches S24, S25, S26 and S27 are turned off;
when ck2 is high, the output switches S28, S29, S30 and S31 are closed; when ck2 is at low level, the output switches S28, S29, S30 and S31 are turned off;
when ck3 is high, the output switches S32, S33, S34 and S35 are closed; when ck3 is at low level, the output switches S32, S33, S34 and S35 are turned off;
when ck4 is high, the output switches S36, S37, S38 and S39 are closed; when ck4 is low, the output switches S36, S37, S38, and S39 are turned off.
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of analog integrated circuit design, in particular to a delay chain circuit for an analog FIR filter and an implementation method thereof.
[ background of the invention ]
Fir (finite Impulse response) filters, i.e., finite Impulse response filters, are widely used in the fields of communications, image processing, pattern recognition, and the like. In the signal transmission process, a transmission physical medium with limited bandwidth generally causes intersymbol interference and waveform distortion of a signal, so that a receiving party cannot identify the signal. FIR filters are a common technique for equalizing and recovering a received signal, and fig. 1 is a schematic diagram of an FIR filtering algorithm. The input signal passing through multiple stages Z-1The delay chain is transformed (as illustrated in fig. 1 by taking 4 stages of FIR as an example) to obtain delay copies v0 to v3 of the input signal, and the four stages of copies are multiplied by weighting coefficients w0 to w3 respectively and then summed to obtain an FIR filtered output signal. The detection circuit detects the output signal and calculates a weighting coefficient. Since the algorithm structure of the FIR is widely known and is not the focus of the present invention, it will not be described in detail.
FIR filters typically have both digital and analog circuit implementations.
The digital FIR filter circuit is realized by performing analog-to-digital conversion A/D on an analog input signal, calculating a digital result through a DSP designed according to an FIR algorithm shown in FIG. 1, and finally performing digital-to-analog conversion D/A to obtain a filtered analog output signal.
The analog FIR filter circuit is realized without A/D and D/A conversion, and directly performs FIR algorithm processing on the analog input signal. An analog FIR filter circuit implementation is shown in fig. 2. Z in FIR filter algorithm-1The delay chain is realized by adopting an analog sampling hold circuit, a multiplier in the algorithm is realized by adopting a variable gain amplifier VGA, and an adder is realized by adopting a current summing circuit.
An example of a four-stage delay chain circuit typically used in an analog FIR filter is shown in fig. 3. In the figure, a dotted line frame is a one-stage sample-and-hold circuit which is composed of two switches controlled by the inverted clock ck/ckb respectively, two sample-and-hold capacitors and two amplifiers with the gain of 1. The operation waveform of this delay chain circuit is schematically shown in fig. 4. The clock signal ck is at a high level, the switch S1 is turned on, and the capacitor C1 is charged by the signal input port; ck goes low, C1 holds the sampled voltage, and the a1 amplifier charges C2 through switch S2 to the same voltage as C1, which is a delayed copy v0 of the signal input port Vin for one clock cycle. The next ck high, C1 resamples, and C2 still holds the signal voltage sampled at the previous ck high. The first stage v0 is output to the next stage of sample hold circuit by an amplifier A2, and so on, four delay copies of v0, v1, v2 and v3 can be obtained, and a delay chain required in the FIR filter algorithm is realized.
In view of the above, overcoming the drawbacks of the prior art is an urgent problem in the art.
[ summary of the invention ]
The delay chain circuit in the prior art, which is similar to fig. 3, mainly has the following disadvantages in practical application:
theoretically, the gain of the amplifier in the sample-and-hold circuit must be 1, and in practice, there is a design error in the gain of each stage, which will accumulate step by step, resulting in distortion of the delayed replica signal, and thus resulting in performance degradation of the FIR filter. There is inevitably a certain deviation in the chip manufacturing process, which will also affect the consistency of the amplifier gain in the sample-and-hold circuit, and the gradual deviation is accumulated, which affects the signal quality of the delayed copy, resulting in the performance degradation of the FIR filter.
The amplifier and the sample-and-hold capacitor of the analog design occupy a large chip area, and if the number of stages of the FIR filter needs to be increased, two amplifiers and two capacitors need to be added for each stage.
The embodiment of the invention adopts the following technical scheme:
in a first aspect, the present invention provides a delay chain circuit for an analog FIR filter, including n sample-hold amplification circuits, where input terminals of the n sample-hold amplification circuits are connected to a same input signal Vin and are respectively controlled by a switch control signal ck 0-a switch control signal ckn-1, and n preset delay signals vs0, vs1, …, and vsn-1 are formed at output terminals of the n sample-hold amplification circuits, where n is a natural number greater than or equal to 2, specifically:
a first group of output sub-signals are formed according to the sequence of vs1, … and vsn-1 and are respectively connected with n-1 output ports of the delay chain circuit according to the corresponding arrangement sequence, and the connection and disconnection between the first group of output sub-signals and the output ports of the delay chain circuit are controlled by the switch control signal ck 0;
a second group of output sub-signals are formed according to the sequence of vs2, …, vsn-1 and vs0 and are respectively connected with n-1 output ports of the delay chain circuit according to the corresponding arrangement sequence, and the connection and disconnection between the second group of output sub-signals and the output ports of the delay chain circuit are controlled by the switch control signal ck 1;
completing the matching of the remaining n-2 groups of output sub-signals and corresponding switches according to the relationship between the first group of output sub-signals and the second group of output sub-signals; at each moment, only one control level in the switch control signals ck 0-ckn-1 is at a high level, the other n control levels are at low levels, and the high level circularly moves as a period according to the sequential switch control signals ck0, ck1,.. ckn-1;
the number of output ports of the delay chain circuit is n-1; when the control level of the switch is at a high level, the signal is conducted with the port; when the control level is at a low level, the signal is disconnected from the port.
Preferably, the number of the sample-hold amplification circuits is set according to the number of output ports of the delay chain circuit to be realized, wherein when the number of the output ports of the delay chain circuit is n-1, the number of the sample-hold amplification circuits is set to n.
Preferably, the sample-and-hold amplifying circuit includes a sampling switch, an energy storage capacitor, and an integrated amplifying circuit, specifically:
the corresponding sampling switch is arranged between the input port of the integrated amplifying circuit and the signal input port of the corresponding sample-hold amplifying circuit and is used for completing the connection and disconnection between the signal input port of the sample-hold amplifying circuit and the input end of the integrated amplifying circuit under the driving of the first control signal;
the energy storage capacitor is arranged on the other side, opposite to the sampling switch, of the input end of the integrated amplification circuit, and a connection node of the energy storage capacitor is positioned between the sampling switch and the input end of the integrated amplification circuit and used for storing a voltage signal acquired from a signal input port of the sample-and-hold amplification circuit when the sampling switch is closed; when the sampling switch is switched off, the stored voltage signal is amplified by the output end of the integrated amplifying circuit;
the sampling switches in the sampling-holding amplification circuits are respectively controlled by the switch control signals ck 0-ckn-1.
Preferably, when n is 5, the corresponding n preset delay signals are specifically vs0, vs1, vs2, vs3 and vs4, and the switch control signals are specifically ck0, ck1, ck2, ck3 and ck 4; the switch control signals ck0, ck1, ck2, ck3, and ck4 are respectively used for controlling the on and off of the corresponding sample-hold amplifying circuit and the input signal Vin, so that the remaining n-2 groups of output sub-signals and the corresponding switches are matched according to the relationship between the first group of output sub-signals and the second group of output sub-signals, which specifically includes:
forming a third group of output sub-signals according to the sequence of vs3, vs4, vs0 and vs1, and respectively connecting the output sub-signals with 4 output ports of the delay chain circuit according to the corresponding arrangement sequence, wherein the connection and disconnection between the third group of output sub-signals and the output ports of the delay chain circuit are controlled by the switch control signal ck 2;
forming a fourth group of output sub-signals according to the sequence of vs4, vs0, vs1 and vs2, and respectively connecting the fourth group of output sub-signals with 4 output ports of the delay chain circuit according to the corresponding arrangement sequence, wherein the fourth group of output sub-signals is controlled by the switch control signal ck3 to be connected and disconnected with the output ports of the delay chain circuit;
and a fifth group of output sub-signals are formed according to the sequence of vs0, vs1, vs2 and vs3 and are respectively connected with 4 output ports of the delay chain circuit according to the corresponding arrangement sequence, and the fifth group of output sub-signals are switched on and off with the output ports of the delay chain circuit and are controlled by the switch control signal ck 4.
Preferably, the generating circuit of the switch control signal ck 0-ckn-1 is composed of five D flip-flops from D0-D4, specifically:
the D trigger D0 is a D trigger with a SET end SET, the input end D is connected with a switch control signal ck4, the output end Q is used as a switch control signal ck0, and the SET end is connected with a reset signal reset; when reset is at a high level, the switch control signal ck0 at the output end of the D flip-flop D0 is at a high level, and when reset is at a low level, the D flip-flop D0 works normally;
the D trigger D1 is a D trigger with a clearing end CLR, the input end D is connected with a switch control signal ck0, the output end Q is used as a switch control signal ck1, and the clearing end is connected with a reset signal reset; when reset is at a high level, the switch control signal ck1 at the output end of the D flip-flop D1 is at a low level, and when reset is at a low level, the D flip-flop D0 works normally;
the D trigger D2 is a D trigger with a clearing end CLR, the input end D is connected with a switch control signal ck1, the output end Q is used as a switch control signal ck2, and the clearing end is connected with a reset signal reset; when reset is at a high level, the switch control signal ck2 at the output end of the D flip-flop D2 is at a low level, and when reset is at a low level, the D flip-flop D2 works normally;
the D trigger D3 is a D trigger with a clearing end CLR, the input end D is connected with a switch control signal ck2, the output end Q is used as a switch control signal ck3, and the clearing end is connected with a reset signal reset; when reset is at a high level, the switch control signal ck3 at the output end of the D flip-flop D3 is at a low level, and when reset is at a low level, the D flip-flop D3 works normally;
the D trigger D4 is a D trigger with a clearing end CLR, the input end D is connected with a switch control signal ck3, the output end Q is used as a switch control signal ck4, and the clearing end is connected with a reset signal reset; when reset is at high level, the switch control signal ck4 at the output terminal of the D flip-flop D4 is at low level, and when reset is at low level, the D flip-flop D4 operates normally.
In a second aspect, the present invention further provides a method for implementing a delay chain circuit for an analog FIR filter, including n sample-hold amplification circuits, where input ends of the n sample-hold amplification circuits are connected to a same input signal Vin and are respectively controlled by a switch control signal ck 0-a switch control signal ckn-1, and n output ends of the n sample-hold amplification circuits are formed; the output signals of the output ends of the n sampling holding amplifying circuits are vs0, vs1, … and vsn-1; forming a first group of output sub-signals according to the sequence of vs1, … and vsn-1, and respectively connecting the output sub-signals with n-1 output ports of the delay chain circuit according to the corresponding arrangement sequence, wherein the first group of output sub-signals is controlled by a switch control signal ck 0; a second group of output sub-signals are formed according to the sequence of vs2, …, vsn-1 and vs0 and are respectively connected with n-1 output ports of the delay chain circuit according to the corresponding arrangement sequence, and the second group of output sub-signals are controlled by a switch control signal ck 1; completing the matching of the remaining n-2 groups of output sub-signals and corresponding switches according to the relationship between the first group of output sub-signals and the second group of output sub-signals, wherein n is a natural number greater than or equal to 2, and the method comprises the following steps:
setting a first control signal of a preset cyclic sampling delay conduction time window for each of the sampling switch control signals ck 0-ckn-1, so that n preset delay signals vs0, vs1, … and vsn-1 are formed at the output ends of the n sampling holding amplification circuits;
in the first control signal, only one control level of the switching control signals ck0 to ckn-1 is at a high level at each moment, the other n control levels are at low levels, and the high levels cyclically move as a period according to sequences ck0, ck 1.
Preferably, when n is 5, the corresponding 5 preset delay signals are vs0, vs1, vs2, vs3 and vs4 which are respectively output from the integrated amplifier a10, the integrated amplifier a11, the integrated amplifier a12, the integrated amplifier a13 and the integrated amplifier a 14; the first control signals ck0, ck1, ck2, ck3 and ck4 are respectively used for controlling the on and off of the sampling switch S10, the sampling switch S11, the sampling switch S12, the sampling switch S13 and the sampling switch S14, and specifically include:
the sampling switches S10, S11, S12, S13 and S14 are respectively arranged between the input ports of the integrated amplifying circuits A10, A11, A12, A13 and A14 and the signal input ports of the respectively affiliated sampling holding amplifying circuits;
the first control signals ck0, ck1, ck2, ck3 and ck4 control the sampling switches S10, S11, S12, S13 and S14 to be switched on and off, and the signal input ports of the sampling and holding amplification circuits are switched on and off with the input ends of the respective integrated amplification circuits, so that preset delay signals vs0, vs1, vs2, vs3 and vs4 are formed.
Preferably, the implementation method specifically includes:
at the time of t0, when the ck0 changes from low level to high level, the sampling switch S10 is turned on, and the energy storage capacitor C10 on the integrated amplifier a10 side samples the signal input port Vin; at time t1, ck0 is changed from high level to low level, a sampling switch S10 in front of an integrated amplifier a10 is turned off, sampling is finished, the voltage on C10 keeps a sampled voltage vt1 in a period when ck0 is low level, the gain of the integrated amplifier a10 is g10, and vs0 is g10 × vt 1;
at the time of t1, when the ck1 changes from low level to high level, the sampling switch S11 is turned on, and the energy storage capacitor C11 on the integrated amplifier a11 side samples the signal input port Vin; at time t2, ck1 is changed from high level to low level, a sampling switch S11 in front of an integrated amplifier a11 is turned off, sampling is finished, the voltage on C11 keeps a sampled voltage vt2 in a period when ck1 is low level, the gain of the integrated amplifier a11 is g11, and vs1 is g11 × vt 2;
at the time of t2, when the ck2 changes from low level to high level, the sampling switch S12 is turned on, and the energy storage capacitor C12 on the integrated amplifier a12 side samples the signal input port Vin; at time t3, ck2 is changed from high level to low level, a sampling switch S12 in front of the integrated amplifier a12 is turned off, sampling is finished, the voltage on C12 keeps a sampled voltage vt3 in a period when ck2 is low level, and the gain of the integrated amplifier a12 is g12, so that vs2 is g12 × vt 3;
at the time of t3, when the ck3 changes from low level to high level, the sampling switch S13 is turned on, and the energy storage capacitor C13 on the integrated amplifier a13 side samples the signal input port Vin; at time t4, ck3 is changed from high level to low level, a sampling switch S13 in front of the integrated amplifier a13 is turned off, sampling is finished, the voltage on C13 keeps a sampled voltage vt4 in a period when ck3 is low level, and the gain of the integrated amplifier a13 is g13, so that vs3 is g13 × vt 4;
at the time of t4, ck4 is changed from low level to high level, a sampling switch S14 in front of an integrated amplifier a14 is turned on, and an energy storage capacitor C14 on the integrated amplifier a14 side samples a signal input port Vin;
at time t4, the output switch of the fifth of the m sub-output ports owned by each sample-hold amplifier circuit is turned on, and the output port of each delay chain circuit is represented as: v0 ═ vs3 ═ vt4, v1 ═ vs2 ═ vt3, v2 ═ vs1 ═ vt0, v3 ═ vs0 ═ vt 1;
at time t5, ck4 changes from high level to low level, the sampling switch S14 is turned off, the sampling is finished, the voltage on C14 keeps the sampled voltage vt5 in the period when ck4 is low level, and the gain of a14 is g14, so that vs4 is g14 vt 5;
at time t5, ck0 changes from low level to high level, the output switch of the first of the m sub-output ports owned by each controlled sample-hold amplifying circuit is turned on, and the output ports of each delay chain circuit appear as: v0 ═ vs4 ═ vt5, v1 ═ vs3 ═ vt4, v2 ═ vs2 ═ vt3, v3 ═ vs1 ═ vt 2;
at the time t5, ck0 changes from low level to high level again, S10 is turned on again, and C10 samples the signal input port Vin again;
and circulating according to the change process at the time t0-t 5.
Preferably, the implementation method specifically includes:
the control end of the output switch S20 is ck0, the input end of the switch is vs1, and the output end of the switch is v 3;
the control end of the output switch S21 is ck0, the input end of the switch is vs2, and the output end of the switch is v 2;
the control end of the output switch S22 is ck0, the input end of the switch is vs3, and the output end of the switch is v 1;
the control end of the output switch S23 is ck0, the input end of the switch is vs4, and the output end of the switch is v 0;
the control end of the output switch S24 is ck1, the input end of the switch is vs2, and the output end of the switch is v 3;
the control end of the output switch S25 is ck1, the input end of the switch is vs3, and the output end of the switch is v 2;
the control end of the output switch S26 is ck1, the input end of the switch is vs4, and the output end of the switch is v 1;
the control end of the output switch S27 is ck1, the input end of the switch is vs0, and the output end of the switch is v 0;
the control end of the output switch S28 is ck2, the input end of the switch is vs3, and the output end of the switch is v 3;
the control end of the output switch S29 is ck2, the input end of the switch is vs4, and the output end of the switch is v 2;
the control end of the output switch S30 is ck2, the input end of the switch is vs0, and the output end of the switch is v 1;
the control end of the output switch S31 is ck2, the input end of the switch is vs1, and the output end of the switch is v 0;
the control end of the output switch S32 is ck3, the input end of the switch is vs4, and the output end of the switch is v 3;
the control end of the output switch S33 is ck3, the input end of the switch is vs0, and the output end of the switch is v 2;
the control end of the output switch S34 is ck3, the input end of the switch is vs1, and the output end of the switch is v 1;
the control end of the output switch S35 is ck3, the input end of the switch is vs2, and the output end of the switch is v 0;
the control end of the output switch S36 is ck4, the input end of the switch is vs0, and the output end of the switch is v 3;
the control end of the output switch S37 is ck4, the input end of the switch is vs1, and the output end of the switch is v 2;
the control end of the output switch S38 is ck4, the input end of the switch is vs2, and the output end of the switch is v 1;
the control end of the output switch S39 is ck4, the input end of the switch is vs3, and the output end of the switch is v 0.
Preferably, the implementation method specifically includes:
when ck0 is high, the output switches S20, S21, S22 and S23 are closed; when ck0 is at low level, the output switches S20, S21, S22 and S23 are turned off;
when ck1 is high, the output switches S24, S25, S26 and S27 are closed; when ck1 is at low level, the output switches S24, S25, S26 and S27 are turned off;
when ck2 is high, the output switches S28, S29, S30 and S31 are closed; when ck2 is at low level, the output switches S28, S29, S30 and S31 are turned off;
when ck3 is high, the output switches S32, S33, S34 and S35 are closed; when ck3 is at low level, the output switches S32, S33, S34 and S35 are turned off;
when ck4 is high, the output switches S36, S37, S38 and S39 are closed; when ck4 is low, the output switches S36, S37, S38, and S39 are turned off.
Compared with the prior art, the embodiment of the invention has the beneficial effects that:
the delay chain circuit for the analog FIR filter effectively reduces the performance index requirement and the process accuracy requirement of the delay chain circuit in the FIR filter to the analog amplifier, increases the reliability of the circuit and obviously reduces the chip area. Compared with the delay chain circuit, the circuit of the invention improves the signal quality of the obtained delay copy and obviously reduces the area of an integrated circuit chip.
[ description of the drawings ]
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of an FIR filter in the prior art according to the present invention;
FIG. 2 is an example of an analog FIR filter circuit implementation of the present invention in the prior art;
FIG. 3 is an example of a conventional four-stage delay chain circuit according to the present invention;
FIG. 4 is a schematic diagram of an operating waveform of a conventional four-stage delay chain circuit according to the present invention;
FIG. 5 is a schematic diagram of a four-stage delay chain circuit for an analog FIR filter according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating an example of a shift clock generating circuit of a four-stage delay chain circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of an operating waveform of a shift clock generating circuit of a four-stage delay chain circuit according to an embodiment of the present invention;
fig. 8 is a schematic diagram of an operating waveform of a four-stage delay chain circuit according to an embodiment of the present invention.
[ detailed description ] embodiments
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the description of the present invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", and the like indicate orientations or positional relationships based on those shown in the drawings, and are for convenience only to describe the present invention without requiring the present invention to be necessarily constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
The delay chain circuit for the analog FIR filter effectively reduces the performance index requirement and the process accuracy requirement of the delay chain circuit in the FIR filter to the analog amplifier, increases the reliability of the circuit and simultaneously obviously reduces the chip area.
It should be emphasized that the delay chain circuit for analog FIR filter of the present invention has no limitation on the length or the number of stages of the delay chain, and for convenience of description, the four-stage delay chain circuit will be described hereinafter as an example. The input and output signals of the FIR filter of the present invention may be single-ended signals or differential signals, and for simplicity of description and simplicity of illustration, only single-ended signals are used for description herein.
In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1:
the embodiment 1 of the present invention provides a delay chain circuit for an analog FIR filter, including n sample-hold amplification circuits, where input ends of the n sample-hold amplification circuits are connected to a same input signal Vin and are respectively controlled by a switch control signal ck 0-a switch control signal ckn-1, and n preset delay signals vs0, vs1, …, and vsn-1 are formed at output ends of the n sample-hold amplification circuits, where n is a natural number greater than or equal to 2, specifically:
a first group of output sub-signals are formed according to the sequence of vs1, … and vsn-1 and are respectively connected with n-1 output ports of the delay chain circuit according to the corresponding arrangement sequence, and the connection and disconnection between the first group of output sub-signals and the output ports of the delay chain circuit are controlled by the switch control signal ck 0;
a second group of output sub-signals are formed according to the sequence of vs2, …, vsn-1 and vs0 and are respectively connected with n-1 output ports of the delay chain circuit according to the corresponding arrangement sequence, and the connection and disconnection between the second group of output sub-signals and the output ports of the delay chain circuit are controlled by the switch control signal ck 1;
completing the matching of the remaining n-2 groups of output sub-signals and corresponding switches according to the relationship between the first group of output sub-signals and the second group of output sub-signals; at each moment, only one control level in the switch control signals ck 0-ckn-1 is at a high level, the other n control levels are at low levels, and the high level circularly moves as a period according to the sequential switch control signals ck0, ck1,.. ckn-1;
the number of output ports of the delay chain circuit is n-1; when the control level of the switch is at a high level, the signal is conducted with the port; when the control level is at a low level, the signal is disconnected from the port.
The number of the sampling holding amplification circuits is set according to the number of output ports of the delay chain circuit to be realized, wherein when the number of the output ports of the delay chain circuit is n-1, the number of the sampling holding amplification circuits is set to be n.
The delay chain circuit for the analog FIR filter effectively reduces the performance index requirement and the process accuracy requirement of the delay chain circuit in the FIR filter to the analog amplifier, increases the reliability of the circuit and obviously reduces the chip area. Compared with the delay chain circuit, the circuit of the invention improves the signal quality of the obtained delay copy and obviously reduces the area of an integrated circuit chip.
The implementation principle of the embodiment of the invention is that n permutation and combination output signals are connected with the delay output port of the FIR filter, and only one permutation and combination in a time period is in a conduction state with the delay output port of the FIR filter in a mutual exclusion manner; the n sampling switches acquire preset periodic delay control signals so as to control the sample-hold amplifying circuit to output corresponding periodic delay input signals; and the n permutation and combination output signals are used for sequencing the output ends of the n sampling hold amplifying circuits so as to evolve a timing chart of the delay output sub-port of each FIR filter in a mutually exclusive mode.
In combination with the embodiment of the present invention, there is a preferred implementation scheme, where the sample-and-hold amplifying circuit includes a sampling switch, an energy storage capacitor, and an integrated amplifying circuit, specifically:
the corresponding sampling switch is arranged between the input port of the integrated amplifying circuit and the signal input port of the corresponding sample-hold amplifying circuit and is used for completing the connection and disconnection between the signal input port of the sample-hold amplifying circuit and the input end of the integrated amplifying circuit under the driving of the first control signal;
the energy storage capacitor is arranged on the other side, opposite to the sampling switch, of the input end of the integrated amplification circuit, and a connection node of the energy storage capacitor is positioned between the sampling switch and the input end of the integrated amplification circuit and used for storing a voltage signal acquired from a signal input port of the sample-and-hold amplification circuit when the sampling switch is closed; when the sampling switch is switched off, the stored voltage signal is amplified by the output end of the integrated amplifying circuit;
the sampling switches in the sampling-holding amplification circuits are respectively controlled by the switch control signals ck 0-ckn-1. In the following implementation of the present invention, the relationship between the sampling switch and the switch control signal in the sample-and-hold amplifying circuit described above will be shown by setting n to 5.
There is a preferred implementation scheme in combination with the embodiment of the present invention, where n is 5, the corresponding n preset delay signals are specifically vs0, vs1, vs2, vs3 and vs4, and the switch control signals are specifically ck0, ck1, ck2, ck3 and ck 4; the switch control signals ck0, ck1, ck2, ck3, and ck4 are respectively used for controlling the on and off of the corresponding sample-hold amplifying circuit and the input signal Vin, so that the remaining n-2 groups of output sub-signals and the corresponding switches are matched according to the relationship between the first group of output sub-signals and the second group of output sub-signals, which specifically includes:
forming a third group of output sub-signals according to the sequence of vs3, vs4, vs0 and vs1, and respectively connecting the output sub-signals with 4 output ports of the delay chain circuit according to the corresponding arrangement sequence, wherein the connection and disconnection between the third group of output sub-signals and the output ports of the delay chain circuit are controlled by the switch control signal ck 2;
forming a fourth group of output sub-signals according to the sequence of vs4, vs0, vs1 and vs2, and respectively connecting the fourth group of output sub-signals with 4 output ports of the delay chain circuit according to the corresponding arrangement sequence, wherein the fourth group of output sub-signals is controlled by the switch control signal ck3 to be connected and disconnected with the output ports of the delay chain circuit;
and a fifth group of output sub-signals are formed according to the sequence of vs0, vs1, vs2 and vs3 and are respectively connected with 4 output ports of the delay chain circuit according to the corresponding arrangement sequence, and the fifth group of output sub-signals are switched on and off with the output ports of the delay chain circuit and are controlled by the switch control signal ck 4.
In a preferred implementation scheme in conjunction with the embodiment of the present invention, as shown in fig. 6, the generation circuits of the switch control signal ck 0-the switch control signal ckn-1 are formed by five D flip-flops D0-D4, specifically:
the D trigger D0 is a D trigger with a SET end SET, the input end D is connected with a switch control signal ck4, the output end Q is used as a switch control signal ck0, and the SET end is connected with a reset signal reset; when reset is at a high level, the switch control signal ck0 at the output end of the D flip-flop D0 is at a high level, and when reset is at a low level, the D flip-flop D0 works normally;
the D trigger D1 is a D trigger with a clearing end CLR, the input end D is connected with a switch control signal ck0, the output end Q is used as a switch control signal ck1, and the clearing end is connected with a reset signal reset; when reset is at a high level, the switch control signal ck1 at the output end of the D flip-flop D1 is at a low level, and when reset is at a low level, the D flip-flop D0 works normally;
the D trigger D2 is a D trigger with a clearing end CLR, the input end D is connected with a switch control signal ck1, the output end Q is used as a switch control signal ck2, and the clearing end is connected with a reset signal reset; when reset is at a high level, the switch control signal ck2 at the output end of the D flip-flop D2 is at a low level, and when reset is at a low level, the D flip-flop D2 works normally;
the D trigger D3 is a D trigger with a clearing end CLR, the input end D is connected with a switch control signal ck2, the output end Q is used as a switch control signal ck3, and the clearing end is connected with a reset signal reset; when reset is at a high level, the switch control signal ck3 at the output end of the D flip-flop D3 is at a low level, and when reset is at a low level, the D flip-flop D3 works normally;
the D trigger D4 is a D trigger with a clearing end CLR, the input end D is connected with a switch control signal ck3, the output end Q is used as a switch control signal ck4, and the clearing end is connected with a reset signal reset; when reset is at high level, the switch control signal ck4 at the output terminal of the D flip-flop D4 is at low level, and when reset is at low level, the D flip-flop D4 operates normally.
The clock ends of the five triggers D0-D4 are all connected to the clock ck; the clock ck is represented as a periodic square wave in the embodiment of the present invention, and is used for forming the switch control signals ck 0-ck 4 in cooperation with the D flip-flops shown in fig. 6.
As shown in fig. 7, the waveform of the shift clock generated by the shift clock generation circuit in fig. 6 is such that, after the reset is completed, the five D flip-flops sequentially shift the output of the previous D flip-flop to the output of the next D flip-flop under the control of the clock ck, and the reset is cyclically performed. At each time, only one of the switch control signals ck 0-ck 4 is at a high level, the other four are at a low level, and the high level moves cyclically in the order of ck0, ck1, ck2, ck3, ck4, ck0, ck 1.
The delay chain circuit for the analog FIR filter provided by the embodiment of the invention can realize the following functions:
compared with the prior delay chain circuit, the invention does not carry out the step-by-step amplification and transmission of the analog sampling signal, and reduces the index requirement on the gain design error of the amplifier. In the invention, as long as the same amplifier is adopted, even if the gain of the amplifier is not 1, the quality of the delayed copy of the signal is not influenced, and the performance of the FIR filter is not reduced.
The invention reduces the requirement for gain error of the amplifier, and also reduces the negative influence of semiconductor manufacturing process deviation on the circuit performance.
The invention greatly reduces the number of amplifiers and capacitors and saves the chip area. If the number of the FIR stages is increased by one stage, a signal delay copy of one stage needs to be correspondingly increased. The invention only needs to add one amplifier and one capacitor for each stage.
Example 2:
the method for realizing the delay chain circuit of the analog FIR filter comprises n sampling-holding amplification circuits, wherein the input ends of the n sampling-holding amplification circuits are connected with the same input signal Vin and are respectively controlled by a switch control signal ck 0-a switch control signal ckn-1, and n sampling-holding amplification circuits are formed at the output ends of the n sampling-holding amplification circuits; the output signals of the output ends of the n sampling holding amplifying circuits are vs0, vs1, … and vsn-1; forming a first group of output sub-signals according to the sequence of vs1, … and vsn-1, and respectively connecting the output sub-signals with n-1 output ports of the delay chain circuit according to the corresponding arrangement sequence, wherein the first group of output sub-signals is controlled by a switch control signal ck 0; a second group of output sub-signals are formed according to the sequence of vs2, …, vsn-1 and vs0 and are respectively connected with n-1 output ports of the delay chain circuit according to the corresponding arrangement sequence, and the second group of output sub-signals are controlled by a switch control signal ck 1; completing the matching of the remaining n-2 groups of output sub-signals and corresponding switches according to the relationship between the first group of output sub-signals and the second group of output sub-signals, wherein n is a natural number greater than or equal to 2, and the method comprises the following steps:
setting a first control signal of a preset cyclic sampling delay conduction time window for each of the sampling switch control signals ck 0-ckn-1, so that n preset delay signals vs0, vs1, … and vsn-1 are formed at the output ends of the n sampling holding amplification circuits;
in the first control signal, only one control level of the switching control signals ck0 to ckn-1 is at a high level at each moment, the other n control levels are at low levels, and the high levels cyclically move as a period according to sequences ck0, ck 1.
The delay chain circuit control method for the analog FIR filter effectively reduces the performance index requirement and the process accuracy requirement of the delay chain circuit in the FIR filter to the analog amplifier, increases the reliability of the circuit and obviously reduces the chip area. Compared with the delay chain circuit, the supporting circuit of the implementation method of the invention improves the signal quality of the obtained delay copy and obviously reduces the chip area of the integrated circuit.
In combination with the embodiment of the present invention, there is a preferred implementation scheme, where n is 5, and the corresponding 5 preset delay signals vs0, vs1, vs2, vs3 and vs4 are respectively output from the integrated amplifier a10, the integrated amplifier a11, the integrated amplifier a12, the integrated amplifier a13 and the integrated amplifier a 14; the first control signals ck0, ck1, ck2, ck3 and ck4 are respectively used for controlling the on and off of the sampling switch S10, the sampling switch S11, the sampling switch S12, the sampling switch S13 and the sampling switch S14, and specifically include:
the sampling switches S10, S11, S12, S13 and S14 are respectively arranged between the input ports of the integrated amplifying circuits A10, A11, A12, A13 and A14 and the signal input ports of the respectively affiliated sampling holding amplifying circuits;
the first control signals ck0, ck1, ck2, ck3 and ck4 control the sampling switches S10, S11, S12, S13 and S14 to be switched on and off, and the signal input ports of the sampling and holding amplification circuits are switched on and off with the input ends of the respective integrated amplification circuits, so that preset delay signals vs0, vs1, vs2, vs3 and vs4 are formed.
Further, with reference to the timing waveform diagram shown in fig. 8, the implementation method includes:
at the time of t0, when the ck0 changes from low level to high level, the sampling switch S10 is turned on, and the energy storage capacitor C10 on the integrated amplifier a10 side samples the signal input port Vin; at time t1, ck0 is changed from high level to low level, a sampling switch S10 in front of an integrated amplifier a10 is turned off, sampling is finished, the voltage on C10 keeps a sampled voltage vt1 in a period when ck0 is low level, the gain of the integrated amplifier a10 is g10, and vs0 is g10 × vt 1;
at the time of t1, when the ck1 changes from low level to high level, the sampling switch S11 is turned on, and the energy storage capacitor C11 on the integrated amplifier a11 side samples the signal input port Vin; at time t2, ck1 is changed from high level to low level, a sampling switch S11 in front of an integrated amplifier a11 is turned off, sampling is finished, the voltage on C11 keeps a sampled voltage vt2 in a period when ck1 is low level, the gain of the integrated amplifier a11 is g11, and vs1 is g11 × vt 2;
at the time of t2, when the ck2 changes from low level to high level, the sampling switch S12 is turned on, and the energy storage capacitor C12 on the integrated amplifier a12 side samples the signal input port Vin; at time t3, ck2 is changed from high level to low level, a sampling switch S12 in front of the integrated amplifier a12 is turned off, sampling is finished, the voltage on C12 keeps a sampled voltage vt3 in a period when ck2 is low level, and the gain of the integrated amplifier a12 is g12, so that vs2 is g12 × vt 3;
at the time of t3, when the ck3 changes from low level to high level, the sampling switch S13 is turned on, and the energy storage capacitor C13 on the integrated amplifier a13 side samples the signal input port Vin; at time t4, ck3 is changed from high level to low level, a sampling switch S13 in front of the integrated amplifier a13 is turned off, sampling is finished, the voltage on C13 keeps a sampled voltage vt4 in a period when ck3 is low level, and the gain of the integrated amplifier a13 is g13, so that vs3 is g13 × vt 4;
at the time of t4, ck4 is changed from low level to high level, a sampling switch S14 in front of an integrated amplifier a14 is turned on, and an energy storage capacitor C14 on the integrated amplifier a14 side samples a signal input port Vin;
at time t4, the output switch of the fifth of the m sub-output ports owned by each sample-hold amplifier circuit is turned on, and the output port of each delay chain circuit is represented as: v0 ═ vs3 ═ vt4, v1 ═ vs2 ═ vt3, v2 ═ vs1 ═ vt0, v3 ═ vs0 ═ vt 1;
at time t5, ck4 changes from high level to low level, the sampling switch S14 is turned off, the sampling is finished, the voltage on C14 keeps the sampled voltage vt5 in the period when ck4 is low level, and the gain of a14 is g14, so that vs4 is g14 vt 5;
at time t5, ck0 changes from low level to high level, the output switch of the first of the m sub-output ports owned by each controlled sample-hold amplifying circuit is turned on, and the output ports of each delay chain circuit appear as: v0 ═ vs4 ═ vt5, v1 ═ vs3 ═ vt4, v2 ═ vs2 ═ vt3, v3 ═ vs1 ═ vt 2;
at the time t5, ck0 changes from low level to high level again, S10 is turned on again, and C10 samples the signal input port Vin again;
and circulating according to the change process at the time t0-t 5.
Further, the control method of the output switch in the trial test of the present invention will be further explained with reference to fig. 5:
the control end of the output switch S20 is ck0, the input end of the switch is vs1, and the output end of the switch is v 3;
the control end of the output switch S21 is ck0, the input end of the switch is vs2, and the output end of the switch is v 2;
the control end of the output switch S22 is ck0, the input end of the switch is vs3, and the output end of the switch is v 1;
the control end of the output switch S23 is ck0, the input end of the switch is vs4, and the output end of the switch is v 0;
the control end of the output switch S24 is ck1, the input end of the switch is vs2, and the output end of the switch is v 3;
the control end of the output switch S25 is ck1, the input end of the switch is vs3, and the output end of the switch is v 2;
the control end of the output switch S26 is ck1, the input end of the switch is vs4, and the output end of the switch is v 1;
the control end of the output switch S27 is ck1, the input end of the switch is vs0, and the output end of the switch is v 0;
the control end of the output switch S28 is ck2, the input end of the switch is vs3, and the output end of the switch is v 3;
the control end of the output switch S29 is ck2, the input end of the switch is vs4, and the output end of the switch is v 2;
the control end of the output switch S30 is ck2, the input end of the switch is vs0, and the output end of the switch is v 1;
the control end of the output switch S31 is ck2, the input end of the switch is vs1, and the output end of the switch is v 0;
the control end of the output switch S32 is ck3, the input end of the switch is vs4, and the output end of the switch is v 3;
the control end of the output switch S33 is ck3, the input end of the switch is vs0, and the output end of the switch is v 2;
the control end of the output switch S34 is ck3, the input end of the switch is vs1, and the output end of the switch is v 1;
the control end of the output switch S35 is ck3, the input end of the switch is vs2, and the output end of the switch is v 0;
the control end of the output switch S36 is ck4, the input end of the switch is vs0, and the output end of the switch is v 3;
the control end of the output switch S37 is ck4, the input end of the switch is vs1, and the output end of the switch is v 2;
the control end of the output switch S38 is ck4, the input end of the switch is vs2, and the output end of the switch is v 1;
the control end of the output switch S39 is ck4, the input end of the switch is vs3, and the output end of the switch is v 0.
Based on the above-mentioned output switch pairing shown in fig. 5, the corresponding control relationship between the output switch pairing and the control signal is provided, which includes:
when ck0 is high, the output switches S20, S21, S22 and S23 are closed; when ck0 is at low level, the output switches S20, S21, S22 and S23 are turned off;
when ck1 is high, the output switches S24, S25, S26 and S27 are closed; when ck1 is at low level, the output switches S24, S25, S26 and S27 are turned off;
when ck2 is high, the output switches S28, S29, S30 and S31 are closed; when ck2 is at low level, the output switches S28, S29, S30 and S31 are turned off;
when ck3 is high, the output switches S32, S33, S34 and S35 are closed; when ck3 is at low level, the output switches S32, S33, S34 and S35 are turned off;
when ck4 is high, the output switches S36, S37, S38 and S39 are closed; when ck4 is low, the output switches S36, S37, S38, and S39 are turned off.
As can be understood from the above control process and the relation of the timing chart shown in fig. 8, in the specific implementation process, the timing output of the first round, like t0-t4, is usually released, because at this time, the initial energy storage process has not been completed for the energy storage capacitors corresponding to the included integrated amplifiers.
Example 3:
fig. 8 is a schematic diagram of an operating waveform of the four-stage delay chain circuit according to the embodiment of the present invention. For brevity, it is assumed in the embodiment of the present invention that the gains g of the amplifiers A10-A14 are the same and are all 1.
At time t0, ck0 becomes high, sampling switch S10 is turned on, and C10 samples Vin; at time t1, ck0 goes low, S10 is turned off, sampling ends, the voltage at C10 keeps the sampled voltage vt1 during the period when ck0 goes low, and the gain of a10 is 1, so vs0 is equal to vt 1.
At time t1, ck1 becomes high, sampling switch S11 is turned on, and C11 samples Vin; at time t2, ck1 goes low, S11 is turned off, sampling ends, the voltage at C11 keeps the sampled voltage vt2 during the period when ck1 goes low, and the gain of a11 is 1, so vs1 is equal to vt 2.
At time t2, ck2 becomes high, sampling switch S12 is turned on, and C12 samples Vin; at time t2, ck2 goes low, S12 is turned off, sampling ends, the voltage at C12 keeps the sampled voltage vt3 during the period when ck2 goes low, and the gain of a12 is 1, so vs2 is equal to vt 3.
At time t3, ck3 becomes high, sampling switch S13 is turned on, and C13 samples Vin; at time t4, ck3 goes low, S13 is turned off, sampling ends, the voltage at C13 keeps the sampled voltage vt4 during the period when ck3 goes low, and the gain of a13 is 1, so vs3 is equal to vt 4.
At time t4, ck4 goes high, sampling switch S14 turns on, and C14 samples Vin.
At time t4, four output switches S36, S37, S38, S39 are turned on, v 0-vs 3-vs 4, v 1-vs 2-vs 3, v 2-vs 1-vs 2, and v 3-vs 0-vs 1.
At time t5, ck4 goes low, sampling switch S14 is turned off, and sampling ends, and the voltage at C14 holds the sampled voltage vt5 during the period when ck4 goes low, and the gain of a14 is 1, so that vs4 is equal to vt 5.
At time t5, ck0 goes high, the output switch controlled by it is turned on, v 0-vs 4-vt 5, v 1-vs 3-vs 4, v 2-vs 2-vs 3, and v 3-vs 1-vs 2.
At time t5, ck0 goes high again, S10 turns on again, and C10 samples Vin again.
And the process is circulated.
From the variation relations of the values of v0, v1, v2 and v3 in fig. 8, it can be seen that the circuit realizes the delay chain function of the analog signal.
The delay chain circuit for simulating the FIR filter can realize the following functions:
(1) compared with the prior delay chain circuit, the invention does not carry out the step-by-step amplification and transmission of the analog sampling signal, and reduces the index requirement on the gain design error of the amplifier. In the invention, as long as the same amplifier is adopted, even if the gain of the amplifier is not 1, the quality of the delayed copy of the signal is not influenced, and the performance of the FIR filter is not reduced.
(2) The invention reduces the requirement for gain error of the amplifier, and also reduces the negative influence of semiconductor manufacturing process deviation on the circuit performance.
(3) The invention greatly reduces the number of amplifiers and capacitors and saves the chip area. If the number of the FIR stages is increased by one stage, a signal delay copy of one stage needs to be correspondingly increased. The invention only needs to add one amplifier and one capacitor for each stage.
It should be noted that, for the information interaction, execution process and other contents between the modules and units in the apparatus and system, the specific contents may refer to the description in the embodiment of the method of the present invention because the same concept is used as the embodiment of the processing method of the present invention, and are not described herein again.
Those of ordinary skill in the art will appreciate that all or part of the steps of the various methods of the embodiments may be implemented by associated hardware as instructed by a program, which may be stored on a computer-readable storage medium, which may include: read Only Memory (ROM), Random Access Memory (RAM), magnetic or optical disks, and the like.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.