阅读说明：本技术 工艺与温度追踪参考负载及其方法 (Process and temperature tracking reference load and method thereof ) 是由 林嘉亮 于 2020-10-16 设计创作，主要内容包括：本发明提出一种校准电路以及一种参考负载,所述参考负载包含一电阻负载与一晶体管负载的一并联结构,该电阻负载包含一电阻,该晶体管负载包含多个晶体管,其中该电阻负载的一温度系数为正,该晶体管负载的一温度系数为负。(The invention provides a calibration circuit and a reference load, wherein the reference load comprises a parallel connection structure of a resistance load and a transistor load, the resistance load comprises a resistor, the transistor load comprises a plurality of transistors, one temperature coefficient of the resistance load is positive, and one temperature coefficient of the transistor load is negative.)

1. A calibration circuit, comprising:

a resistance load, including an adjustable resistance controlled by a control signal, for receiving a first current and establishing a first voltage accordingly;

a transistor load comprising a plurality of transistors for receiving a second current and establishing a second voltage accordingly;

a comparator for outputting a logic signal according to a comparison result between the first voltage and the second voltage; and

a finite state machine for receiving the logic signal and outputting the control signal.

2. The calibration circuit of claim 1, further comprising: a temperature detector for detecting a temperature.

3. The calibration circuit of claim 2, wherein a ratio between the first current and the second current is dependent on the temperature.

4. A reference load, comprising: a parallel configuration of a resistive load and a transistor load, the resistive load comprising a resistor, the transistor load comprising a plurality of transistors, wherein a temperature coefficient of the resistive load is positive and a temperature coefficient of the transistor load is negative.

5. The reference load of claim 4, wherein the transistor load comprises a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor, wherein:

a source, a gate and a drain of the first PMOS transistor are respectively connected to a first node, a second node and a third node;

a source, a gate and a drain of the first NMOS transistor are respectively connected to a fourth node, the third node and the second node;

a source, a gate and a drain of the second PMOS transistor are connected to the third node, the fourth node and the second node, respectively; and

a source, a gate, and a drain of the second NMOS transistor are connected to the second node, the first node, and the third node, respectively.

6. The reference load of claim 4, wherein the transistor load comprises an NMOS transistor and a PMOS transistor, the NMOS transistor and the PMOS transistor being stacked and configured in a diode connection.

7. The reference load of claim 4, wherein the resistance is adjustable.

8. The reference load of claim 7, wherein the resistor is adjusted to have a resistance that approximates a resistance of the transistor load multiplied by a scaling factor.

9. The reference load of claim 7, wherein the reference load is configured to receive a reference current and to establish a reference voltage accordingly.

10. The reference load of claim 9, wherein the reference current is a constant transduction current or a proportional to absolute temperature current.

Technical Field

The present disclosure relates generally to a reference load, and more particularly to a circuit and method for adaptively determining a temperature coefficient of a reference load.

Background

Those skilled in the art will appreciate that the terms used in this disclosure, such as CMOS (complementary metal oxide semiconductor), NMOS (n-channel metal oxide semiconductor) transistors, PMOS (p-channel metal oxide semiconductor) transistors, and understand the basic concepts used in electronic circuits, such as voltages, currents, loads, inverters, resistors, switches, logic signals, current mirrors, and comparators. One skilled in the art can recognize a resistance symbol, a ground symbol, a PMOS transistor symbol, and an NMOS transistor symbol, and can recognize the source, gate, and drain of a PMOS transistor or an NMOS transistor. Those skilled in the art will appreciate that a circuit diagram includes resistors, NMOS transistors and PMOS transistors, and redundant description is not necessary to explain how one transistor is connected to another transistor in the diagram. Those skilled in the art will also appreciate various units such as degrees Celsius, micrometers (μm), nanometers (nm), and kiloohms (KOhm; Kilo-Ohm). Similar terms and concepts are known from prior art documents (e.g., Design of Analog CMOS Integrated Circuits (ISBN 0-07-118839-8) reflecting the understanding of those skilled in the art) and thus are not described in detail herein.

The speed of a circuit, such as an inverter, produced in CMOS (complementary metal oxide semiconductor) process technology is typically highly dependent on PVT (production process, supply voltage and junction temperature). The supply voltage is relatively easy to control compared to (production) processes and (junction) temperatures, and therefore circuit designers often choose to adjust the supply voltage of the circuit to maintain the desired speed of the circuit. In order to establish a stable supply voltage, a voltage regulator (voltage regulator) is often used, wherein the supply voltage is controlled in a closed loop manner to track a reference voltage. In the above example, the circuit designer may choose to adjust the reference voltage based on process and temperature, whereby the supply voltage provided to the circuit may be adjusted to maintain a desired speed in response to process and temperature variations.

A reference voltage is usually established by using a reference load, in which a reference current I is used_REFIs received and converted into a reference voltage V_REF. As shown in fig. 1A, a prior art reference load 110 includes an NMOS transistor 111 and a PMOS transistor 112 stacked together (stacked) and configured in a diode-connected configuration (diode-connected topology). The term "diode connected" is a common knowledge in the art and therefore the description is not detailed here. As an example, a 28 nm CMOS process is used, the width/length (width/length) of the NMOS transistor 111 is 1.6 μm/240nm, the width/length of the PMOS transistor 112 is 1.6 μm/240nm, and the reference current I is_REFHas a nominal value of 7.2 muA, the reference voltage V_REFThe nominal value at 42.5 ℃ is 850 mv.

As shown in fig. 1B, an alternative reference load 120 (disclosed in U.S. patent 10,222,818) includes two NMOS transistors 121 and 122 and two PMOS transistors 123 and 124. As an example, the width/length of the NMOS transistor 121 is 1.6 μm/240nm, the width/length of the NMOS transistor 122 is 1.2 μm/240nm, the width/length of the PMOS transistor 123 is 1.2 μm/240nm, the width/length of the PMOS transistor 124 is 1.6 μm/240nm, and the reference current I_REFHas a nominal value of 13.6 muA, the reference voltage V_REFThe nominal value at 42.5 ℃ is 850 mV. For two reference loads 110 and 120, I_REFAnd V_REFThe relationship between them is highly dependent on temperature. FIG. 1C shows a curve representation V_REFA value of (v), (mv), and a temperature (temp (C)), wherein the unit "C" represents a unit of temperature in degrees celsius; for the reference load 110, when I_REFIs fixed at 7.2. mu.A, V_REF850mV at 42.5 deg.C (M22); when the temperature drops to-40 deg.C (M24), V_REFWill rise to 946 mV; when the temperature rises to 125 deg.C (M23), V_REFIt will drop to 762 mV.

FIG. 1D shows a curve representation V_REFThe relationship between the value of (d) and the temperature; for the reference load 120, when I_REFIs fixed at 13.6. mu.A, V_REF850mV at 42.5 deg.C (M19); when the temperature drops to-40 deg.C (M20), V_REFWill rise to 941 mV; when the temperature rises to 125 deg.C (M21), V_REFIt will drop to 770 mV. As temperature rises (falls), a circuit typically becomes slower (fast), so it requires a higher (lower) reference voltage to maintain the same speed. This can be accomplished by using a reference current (a constant-gm current or a PTAT (proportional to absolute temperature) current) that increases purely due to temperature rise. On the other hand, if the reference current I_REFFor constant value, both reference loads 110 and 120 have a negative temperature coefficient, where V_REFDecreases as the temperature increases. Although the use of the fixed transconductance current or the PTAT current enables the reference voltage to be higher as the temperature rises, the negative temperature coefficient still slightly detracts from the increase in current.

In view of the foregoing, there is a need in the art for a method for adaptively determining a temperature coefficient of a reference load.

Disclosure of Invention

According to an embodiment of the present disclosure, a reference load comprises a parallel configuration of a resistive load and a transistor load, the resistive load comprising a resistor, the transistor load comprising a plurality of transistors, wherein a temperature coefficient of the resistive load is positive and a temperature coefficient of the transistor load is negative. In this embodiment, the resistance of the resistive load is calibrated based on a comparison between the resistance and the resistance of the transistor load.

According to an embodiment of the present disclosure, a calibration circuit includes: a resistance load, including an adjustable resistance controlled by a control signal, for receiving a first current and establishing a first voltage accordingly; a transistor load comprising a plurality of transistors for receiving a second current and establishing a second voltage accordingly; a comparator for outputting a logic signal according to a comparison result between the first voltage and the second voltage; and a finite state machine for receiving the logic signal and outputting the control signal.

According to an embodiment of the present disclosure, a method includes: a load of controlled temperature coefficient (TCC) load is established by using a parallel configuration of a resistive load and a transistor load, wherein the resistive load comprises a resistor, the transistor load comprises a plurality of transistors, a temperature coefficient of the resistive load is positive, and a temperature coefficient of the transistor load is negative. In this embodiment, the resistance of the resistive load is calibrated based on a comparison between the resistance and the resistance of the transistor load.

The features, implementations, and technical advantages of the present invention are described in detail below with reference to the accompanying drawings.

Drawings

FIG. 1A shows a schematic diagram of a prior art reference load;

FIG. 1B shows a schematic diagram of another prior art reference load;

FIG. 1C shows a voltage versus temperature curve for the reference load of FIG. 1A;

FIG. 1D shows a voltage versus temperature curve for the reference load of FIG. 1B;

FIG. 2 illustrates a schematic diagram of a reference load according to an embodiment of the present disclosure;

FIG. 3A shows a voltage versus temperature curve for the reference load of FIG. 2;

FIG. 3B shows a voltage versus temperature curve for the resistive load in the reference load of FIG. 2;

FIG. 4 shows an adjustable resistor that can be used as a resistive load for the reference load of FIG. 2; and

FIG. 5 shows a functional block diagram of a calibration circuit according to an embodiment of the present disclosure.

Description of the symbols

110: reference load

111: NMOS transistor

112: PMOS transistor

I_REF: reference current

V_REF: reference voltage

120: reference load

121: NMOS transistor

122: NMOS transistor

123: PMOS transistor

124: PMOS transistor

200: reference load

210: resistance load (Resistor load)

220: transistor load (Transistor load)

211: resistance (RC)

221: NMOS transistor

222: NMOS transistor

223: PMOS transistor

224: PMOS transistor

I_REF: reference current

V_REF: reference voltage

400: adjustable resistor

410. 420, 430: switch resistance unit

C₁、C₂、C₃: logic signal

411. 421, 431: resistance (RC)

412. 422, 432: switch with a switch body

500: calibration circuit

510: resistance load (Resistor load)

520: transistor load (Transistor load)

530: comparator (comparator)

540: finite State Machine (FSM)

I₁: first current

I₂: the second current

V₁: first voltage

V₂: second voltage

DEC: logic signal

CTL: control signal

Detailed Description

The present disclosure is directed to a reference load. Although the present specification discloses that the embodiments of the present disclosure may be regarded as preferred examples of implementing the present invention, the present invention may be implemented in various ways, not limited to the specific examples described below, nor to specific ways to implement the technical features of the specific examples. In other instances, details well known to those skilled in the art have not been shown or described in order to avoid obscuring aspects of the present disclosure.

The expression of the present disclosure is based on an engineering point of view. For example, "X equals Y" means "the difference between X and Y is less than a particular engineering error"; "X is even less than Y" means that "X divided by Y yields a value less than an engineering error"; and "X is zero" means "X is less than a specified engineering error".

In the present disclosure, a logic signal is a voltage that can be in a high voltage state or a low voltage state; a switch is a device controlled by a logic signal, wherein the switch approximates a short circuit when the logic signal is in a high voltage state; when the logic signal is in a low voltage state, the switch is similar to an open circuit. For simplicity, the phrase "the logic signal X is high (low)" indicates that the logic signal X is in a high voltage state (low voltage state) ".

Fig. 2 shows a schematic diagram of a reference load 200 according to an embodiment of the present disclosure. The reference load 200 includes a parallel configuration of a resistive load (Resistor load)210 and a Transistor load (Transistor load) 220. The resistive load 210 includes a resistor 211. The transistor load 220 includes two NMOS transistors 221 and 222 and two PMOS transistors 223 and 224. The transistor load 220 is similar to the reference load 120 shown in fig. 1B and is described in detail in U.S. Pat. No. 10,222,818, and therefore, the description thereof is omitted here. As a non-limiting example, the reference load 200 is fabricated using a 28 nanometer CMOS process; the resistance of the resistor 211 is 26.6 KOhm; the width/length of the NMOS transistor 221 is 1.6 μm/240 nm; the width/length of the NMOS transistor 222 is 1.2 μm/240 nm; the width/length of the PMOS transistor 223 is 1.2 μm/240 nm; the width/length of the PMOS transistor 224 is 1.6 μm/240 nm; i is_REFHas a nominal value of 44.5 muA; v_REFThe nominal value at 42.5 ℃ is 850 mV. When I is_REFFixed at 44.5. mu.A, V_REFThe curve of the value of (d) versus temperature is shown in fig. 3A.

As shown in FIG. 3A, V_REFNominal 850mV at 42.5 ℃ (M16); when the temperature drops to-40 deg.C (M18), V_REFIncreasing the concentration to 908 mV; when the temperature rises to 125 deg.C (M17), V_REFReduce to 802 mV. Although it still has a negative temperature coefficient, the voltage varies with temperature to a much lesser degree than the example of the reference load 110 of FIG. 1A and the reference load 120 of FIG. 1B. The temperature coefficient of the resistive load 210 can be characterized by the following means: removing the transistor load 220 and adjusting the reference current I_REFSo that V is_REFIt is still 850mV at 42.5 ℃; then the temperature was varied to observe V_REFHow is to vary accordingly. When the transistor load 220 is removed and I_REFWhen it is fixed to 31.0. mu.A, V_REFThe curve of the value of (d) versus temperature is shown in fig. 3B.

As shown in FIG. 3B, V_REFNominal 850mV at 42.5 ℃ (M4); when the temperature drops to-40 deg.C (M5), V_REFReducing to 767 mV; when the temperature rises to 125 deg.C (M6), V_REFUp to 939mV, so the resistive load 210 has a positive temperature coefficient. On the other hand, the transistor load 220 has a negative temperature coefficient similar to the reference load 120 of FIG. 1B. Thus, the resistive load 210 compensates the transistor load 220 in terms of temperature dependence. By adjusting the resistance of the resistive load 210, the temperature coefficient of the reference load 200 can be adjusted. The smaller (larger) resistance of the resistive load 210 causes more (less) significant influence by the resistive load 210 and biases the temperature coefficient of the reference load 200 toward the positive (negative) temperature coefficient.

In one embodiment, the resistor 211 is an adjustable resistor having an adjustable resistance. FIG. 4 shows one embodiment of an adjustable resistor 400 according to one embodiment of the present disclosure. The adjustable resistor 400 comprises a parallel arrangement of a plurality of switched resistor units 410, 420, 430 …, etc., which are controlled by a plurality of logic signals C, respectively₁、C₂、C₃…, and the like. The logic signals are collectively derived from a control signal. The switch resistance unit 410(420, 430) includes a resistor 411(421, 431) and a switch 412(422, 432) controlled by C₁(C₂、C₃). When C is present₁(C₂、C₃) At high, the switch 412(422, 432) is turned on, and the resistance of the switch resistance unit 410(420, 430) is approximately equal to the resistance of the resistor 411(421, 431). When C is present₁(C₂、C₃) At low, the switches 412(422, 432) are closed, and the switched resistive elements 410(420, 430) approximately correspond to an open circuit.

By changing the logic signal C₁、C₂、C₃And so on, the resistance of the adjustable resistor 400 may be adjusted. Since this is obvious to a person skilled in the art, redundant explanations should not be necessary. In one embodiment, resistors 411, 421, 431, etc. are the same; in this example, when C₁、C₂、C₃Etc. more (fewer) logic signals are set high, adjustable resistor 400 has a smaller (larger) resistance value, and increments (decrements) of the control signal result in an adjustable resistorThe decrease (increase) of the resistance value of the resistor 400, the increment (decrement) of the control signal occurs when C₁、C₂、C₃And so on when one of them changes from low (high) to high (low).

In one embodiment, the resistance of the resistive load 210 is adjusted according to the comparison result between the resistance and the resistance of the transistor load 220. Fig. 5 shows a functional block diagram of a calibration circuit 500 according to an embodiment of the present disclosure. The calibration circuit 500 includes a Resistor load (Resistor load)510, a Transistor load (Transistor load)520, a comparator 530, and a Finite State Machine (FSM) 540. Resistive load 510 may be a replica of resistive load 210; or the resistive load 510 may be the resistive load 210 itself if an in-situ calibration is performed. Similarly, transistor load 520 may be a replica of transistor load 220; or the transistor load 520 may be the transistor load 220 itself if an in-situ calibration is performed. The resistive load 510 and the transistor load 520 are not configured in parallel, but separately receive a first current I₁And a second current I₂Thereby respectively establishing a first voltage V₁And a second voltage V₂. The comparator 530 compares the first voltage V₁And the second voltage V₂And outputs a logic signal DEC indicating the first voltage V₁Whether or not it is higher than the second voltage V₂. The finite state machine 540 receives the logic signal DEC and outputs a control signal CTL to adjust the resistive load 510. An increase (decrease) in the value of the control signal CTL results in a decrease (increase) in the resistance value of the resistive load 510.

For example, when the adjustable resistor 400 of fig. 4 is used to implement the resistive load 510, the control signal CTL is the logic signal C₁、C₂、C₃Etc., the value of the control signal CTL is increased (decreased) by adding C to C₁、C₂、C₃And so on from low (high) to high (low). If the logic signal DEC indicates the first voltage V₁Higher (lower) than the second voltage V₂The finite-state machine 540 increases (decreases) the value of the control signal CTL to reduce the value of the control signal CTLThe resistance of resistive load 510 is lowered (raised). Thus, the resistance of the resistive load 510 is adjusted so that the resistance approaches the resistance of the transistor load 520 multiplied by a factor, which is dependent on I₂/I₁And then, I₂/I₁Is the second current I₂And the first current I₁To each other. For example, if I₁Is I₂Three times the resistance of the resistive load 510 is adjusted so that the resistance approaches one third of the resistance of the transistor load 520, as evidenced by ohm's law, which is well known to those skilled in the art.

In one embodiment, the calibration circuit 500 further comprises a temperature detector (not shown in FIG. 5) that measures a temperature and the first current I₁And the second current I₂Is scaled based on the temperature and according to a look-up table (not shown in fig. 5). At a higher (lower) temperature, as the resistance of the resistive load 510 is higher (lower), I₂/I₁Is the larger (smaller) value in the look-up table. In this way, the resistance of the resistive load 510 is adjusted so that the resistance approaches the value of the transistor load 520 multiplied by a scaling factor (scaling factor) that is set according to the temperature. By using a current mirror architecture, a current like I₁Or I₂Can be adjusted, and the current mirror is prior art, so the description is not detailed here. Comparators, temperature detectors, finite state machines, and look-up tables are also well known to those skilled in the art, and therefore, the description is not detailed herein.

If the resistive load 510 is a replica of the resistive load 210, the control signal CTL of the calibration circuit 500 is used to control the resistive load 210.

In one embodiment, the reference current I_REFIs a constant-gm current, which is a prior art, and therefore, is not described in detail herein. In another embodiment, the reference current I_REFIs a PTAT (proportional to absolute temperature) current, which is also prior art, and thereforeThis specification is not described in detail. Both the constant transconductance current and the PTAT current can be scaled by a current mirror architecture, which is a prior art and therefore will not be described in detail herein.

In an alternative embodiment, the transistor load 210 is replaced by the reference load 110, the reference load 110 includes an NMOS transistor and a PMOS transistor stacked together, and the two transistors are configured in a diode-connected topology.

Although the embodiments of the present invention have been described above, the embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.