Master word line driver circuit
阅读说明:本技术 主字线驱动器电路 (Master word line driver circuit ) 是由 T·H·金 C·J·卡瓦姆拉 于 2020-03-04 设计创作,主要内容包括:本申请案涉及一种主字线驱动器电路。主字线电路提供第一和第二行因子信号。所述主字线电路包含上拉电路以当所述第一行因子信号处于第一值时驱动全局字线以遵循第一经解码地址信号。所述主字线电路包含中间电压电路以驱动所述全局字线以遵循所述第二行因子信号的值。处理装置通过当所述第一经解码地址信号处于高状态时将所述第一行因子信号设定为所述第一值而将所述全局字线驱动到有效状态,且通过当所述第一经解码地址信号处于所述高状态时将所述第一行因子信号设定为所述第二值而驱动所述全局字线以遵循所述第二行因子信号的值。(The present application relates to a master word line driver circuit. The main wordline circuit provides first and second row factor signals. The master wordline circuit includes a pull-up circuit to drive a global wordline to follow a first decoded address signal when the first row factor signal is at a first value. The master wordline circuit includes an intermediate voltage circuit to drive the global wordline to follow a value of the second row factor signal. The processing device drives the global wordline to an active state by setting the first row factor signal to the first value when the first decoded address signal is in a high state, and drives the global wordline to follow a value of the second row factor signal by setting the first row factor signal to the second value when the first decoded address signal is in the high state.)
1. A main word line circuit for a memory device, comprising:
an RF driver circuit configured to provide a first row factor signal and a second row factor signal;
a main word line driver circuit including
A pull-up circuit configured to receive the first row factor signal and a first decoded address signal, the pull-up circuit further configured to drive a global wordline to follow the first decoded address signal when the first row factor signal is at a first value and to isolate the first decoded address signal from the global wordline signal when the first row factor signal is at a second value, and
an intermediate voltage circuit configured to receive the first decoded address signal and the first and second row factor signals, the intermediate circuit further configured to drive the global word line to follow a value of the second row factor signal; and
a processing device operatively coupled to the RF driver circuit, the processing device configured to
Driving the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is in a high state, an
Driving the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value when the first decoded address signal is in the high state,
wherein the value of the second row factor signal is at an intermediate voltage level that is lower than a voltage level of the active state and higher than a voltage level of a pre-charge state.
2. The master word line circuit of claim 1, further comprising:
a pull-down circuit configured to receive the second decoded address signal and a low voltage signal, the pull-down circuit further configured to drive the global wordline to a value of the low voltage signal if the second decoded address signal is at a third value,
wherein the processing device is further configured to drive the global word line to the pre-charge state by setting the second decoded address signal to the third value and setting the first row factor signal to the second value.
3. The main wordline circuit of claim 1, wherein the RF driver circuit receives a timing signal, and
wherein the RF driver circuit is configured such that the first row factor signal is set to the first value based on a first state of the timing signal and is set to the second value based on a second state of the timing signal, the second state being opposite the first state.
4. The master wordline circuit of claim 2, wherein the RF driver circuit receives a first timing signal and a second timing signal,
wherein the RF driver circuit is configured such that the second row factor signal has the intermediate voltage level when the first timing signal is in a first state and the second timing signal is in a second state opposite the first state.
5. The main wordline circuit of claim 1, wherein the intermediate voltage level is in a range of 0.25 volts to 0.75 volts.
6. The main wordline circuit of claim 1, wherein the intermediate voltage level is 0.5 volts.
7. The master wordline circuit of claim 2, wherein the pull-up circuit includes a PMOS transistor having a gate connected to the first row factor signal, a source connected to the first decoded address signal, and a drain connected to the global wordline,
wherein the intermediate voltage circuit includes a first NMOS transistor having a source connected in series to a drain of a second NMOS transistor, a gate of the first NMOS transistor connected to the first decoded address signal and a gate of the second NMOS transistor connected to the first row factor signal, a source of the second NMOS transistor connected to the second row factor signal and a drain of the first NMOS transistor connected to the global word line, and
Wherein the pull-down transistor includes a third NMOS transistor having a gate connected to the second decoded address signal, a source connected to the low voltage signal, and a drain connected to the global word line.
8. A method, comprising:
generating a first row factor signal and a second row factor signal in a memory device;
driving a global wordline of the memory device to an active state by setting the first row factor signal to a first value when a first decoded address signal is in a high state, an
Driving the global word line to follow a value of the second row factor signal by setting the first row factor signal to a second value when the first decoded address signal is in the high state,
wherein the value of the second row factor signal is at an intermediate voltage level that is lower than a voltage level of the active state and higher than a voltage level of a pre-charge state.
9. The method of claim 8, further comprising:
driving the global wordline to the pre-charge state by setting the second decoded address signal to the third value to drive the global wordline to a value of a low voltage source and by setting the first row factor to the second value.
10. The method of claim 8, further comprising:
setting the first row factor signal to the first value based on a first state of a timing signal of a driver circuit of the memory device; and
setting the first row factor signal to the second value based on a second state of the timing signal, the second state being opposite the first state.
11. The method of claim 9, further comprising:
setting the second row factor signal to the intermediate voltage level when a first timing signal of a driver circuit in the memory device is in a first state and a second timing signal of the driver circuit is in a second state opposite the first state.
12. The method of claim 8, wherein the intermediate voltage level is in a range of 0.25 volts to 0.75 volts.
13. The method of claim 12, wherein the intermediate voltage level is 0.5 volts.
14. The method of claim 8, wherein the voltage level of the pre-charge state is-0.2 volts.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
Generating a first row factor signal and a second row factor signal in a memory device;
driving a global wordline of the memory device to an active state by setting the first row factor signal to a first value when a first decoded address signal is in a high state, an
Driving the global word line to follow a value of the second row factor signal by setting the first row factor signal to a second value when the first decoded address signal is in the high state,
wherein the value of the second row factor signal is at an intermediate voltage level that is lower than a voltage level of the active state and higher than a voltage level of a pre-charge state.
16. The non-transitory computer-readable storage medium of claim 15, further causing the processing device to:
driving the global wordline to the pre-charge state by setting the second decoded address signal to the third value to drive the global wordline to a value of a low voltage source and by setting the first row factor to the second value.
17. The non-transitory computer-readable storage medium of claim 15, further causing the processing device to:
Setting the first row factor signal to the first value based on a first state of a timing signal of a driver circuit of the memory device; and
setting the first row factor signal to the second value based on a second state of the timing signal, the second state being opposite the first state.
18. The non-transitory computer-readable storage medium of claim 16, further causing the processing device to:
setting the second row factor signal to the intermediate voltage level when a first timing signal of a driver circuit in the memory device is in a first state and a second timing signal of the driver circuit is in a second state opposite the first state.
19. The non-transitory computer-readable storage medium of claim 15, wherein the intermediate voltage level is in a range of 0.25 volts to 0.75 volts.
20. The non-transitory computer-readable storage medium of claim 19, wherein the intermediate voltage level is 0.5 volts.
Technical Field
Embodiments of the invention relate to a signal driver for a word line circuit and a method of driving a word line in a memory device.
Background
Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices are frequently provided as internal, semiconductor integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory, including Random Access Memory (RAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM), may require a source of applied power to maintain their data. In contrast, nonvolatile memory can retain its stored data even when no external power is supplied. Non-volatile memory may be used in various technologies, including flash memory (e.g., NAND and NOR) Phase Change Memory (PCM), ferroelectric random access memory (FeRAM), Resistive Random Access Memory (RRAM), Magnetic Random Access Memory (MRAM), and the like. Improving memory devices may generally include increasing memory cell density, increasing read/write speed or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption or reducing manufacturing costs, and the like.
Memory devices employ a variety of signals within various circuits of the memory device. Signal drivers for applying signals to signal lines are commonly used in electronic devices such as integrated circuits. One such signal driver may be used to apply voltages to word lines in an array of memory cells. Word lines may extend from a set of global word line drivers (also referred to herein as "main word line drivers" and "MWD") through the memory cell array. The global word line driver may selectively actuate each of the word lines in response to the memory device receiving a row address corresponding to the word line. Each of the memory cells in the row corresponding to the received row address then applies the stored data to a respective sense amplifier.
Some semiconductor memory devices, such as DRAMs, store information as charges that are accumulated in cell capacitors ("cells"), where the cells are organized in rows. In some cases, the charge applied to a cell in one row may interfere with the charge in one or more adjacent "victim" rows, or the cell may otherwise lose its charge, an event referred to as "leakage. Certain leakage conditions may occur when a row of memory experiences "row hammering," which is when the row is repeatedly driven to an active level for a short time (e.g., for a duration less than between sequential refresh operations) and the activation affects one or more adjacent victim rows. This can cause the cell charge in the victim row to change, placing the information stored there at risk.
Various memory systems address leakage using one or more strategies, such as row hammer stress mitigation or Targeted Row Refresh (TRR). Row hammer stress mitigation may involve a host or controller automatically performing refresh operations on a victim row on a random or periodic basis. In some embodiments, row hammer stress mitigation may include controlling the local word line voltage such that the local word line voltage pauses at an intermediate voltage level for a predetermined period of time when going from an active level to a pre-charge or standby level. By pausing at an intermediate voltage, adjacent memory rows do not experience the effects of rapid changes in voltage levels, and row hammer stress can be mitigated.
Each of the word lines extending through the array may be relatively long and, therefore, may have substantial capacitance. In addition, the word line may be made of polysilicon, which may have a relatively high resistance. The combination of relatively high capacitance and relatively high resistance of the word lines may make it difficult for the global word line driver to quickly switch the signal level on the word lines, particularly in portions of the memory cell array that are farther from the global word line driver. To alleviate this problem, memory cell arrays are conventionally divided into smaller memory cell arrays, and local word line drivers (also referred to herein as "sub-word line drivers" and "SWDs") are fabricated between at least some of these smaller memory cell arrays. The local word line drivers may receive substantially the same signals that are used to control the global word line drivers to drive the word lines so that they may apply the same level of the global word line drivers to the word lines.
The use of local word line drivers may improve the switching speed of the word lines, and prior art designs generally include at least one PMOS transistor and at least one NMOS transistor in each local word line driver. The use of PMOS transistors allows the local word line voltage to be the same as the global word line voltage using a lower phase voltage due to the threshold voltage of the NMOS transistors, as compared to NMOS-only local word line drivers. However, while the NMOS transistors used in the local word line drivers may be in the same p-type substrate as the access transistors for the memory cells, the PMOS transistors used in the local word drivers may require the fabrication of an n-well in the p-type substrate to provide the n-type material for the fabrication of the PMOS transistors. Forming an n-well for each of the local word line drivers can greatly increase the area of the semiconductor substrate used to fabricate the local word line drivers, thereby potentially increasing cost or reducing the capacity of the memory device.
Disclosure of Invention
Some embodiments of the invention provide a main word line circuit for a memory device, comprising: an RF driver circuit configured to provide a first row factor signal and a second row factor signal; a master wordline driver circuit including a pull-up circuit configured to receive the first row factor signal and a first decoded address signal, the pull-up circuit further configured to drive a global wordline to follow the first decoded address signal when the first row factor signal is at a first value and to isolate the first decoded address signal from the global wordline signal when the first row factor signal is at a second value, and an intermediate voltage circuit configured to receive the first decoded address signal and the first and second row factor signals, the intermediate circuit further configured to drive the global wordline to follow a value of the second row factor signal; and a processing device operatively coupled to the RF driver circuit, the processing device configured to drive the global wordline to an active state by setting the first row factor signal to the first value when the first decoded address signal is in a high state, and to drive the global wordline to follow a value of the second row factor signal by setting the first row factor signal to the second value when the first decoded address signal is in the high state. The value of the second row factor signal is at an intermediate voltage level that is lower than a voltage level of the active state and higher than a voltage level of a pre-charge state.
Some embodiments of the invention provide a method comprising: generating a first row factor signal and a second row factor signal in a memory device; a global wordline of the memory device is driven to an active state by setting the first row factor signal to a first value when a first decoded address signal is in a high state, and the global wordline is driven to follow a value of the second row factor signal by setting the first row factor signal to a second value when the first decoded address signal is in the high state. The value of the second row factor signal is at an intermediate voltage level that is lower than a voltage level of the active state and higher than a voltage level of a pre-charge state.
Some embodiments of the invention provide a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: generating a first row factor signal and a second row factor signal in a memory device; a global wordline of the memory device is driven to an active state by setting the first row factor signal to a first value when a first decoded address signal is in a high state, and the global wordline is driven to follow a value of the second row factor signal by setting the first row factor signal to a second value when the first decoded address signal is in the high state. The value of the second row factor signal is at an intermediate voltage level that is lower than a voltage level of the active state and higher than a voltage level of a pre-charge state.
Drawings
FIG. 1 is a block diagram of an embodiment of a memory system according to the present invention.
FIG. 2 is a block diagram of a portion of a memory bank array that may be used in the memory system of FIG. 1.
FIG. 3A is a schematic diagram of an embodiment of a master wordline driver according to the present invention.
Fig. 3B is a signal timing diagram of the main word line driver of fig. 3A.
FIG. 3C is a schematic diagram of an embodiment of an RF driver with optional row hammer stress mitigation in accordance with the present invention for the master wordline driver of FIG. 3A.
FIG. 3D is a flow chart of operations for managing master wordline drivers according to the present invention.
FIG. 4A is a schematic diagram of an embodiment of an array of master word line drivers according to the present invention.
FIG. 4B is a schematic diagram of an embodiment of an array of sub-wordline drivers according to the present invention.
FIG. 5A is a schematic diagram of another embodiment of an array of sub-wordline drivers according to the present invention.
Fig. 5B is a signal timing diagram of the sub word line driver of fig. 5A.
FIG. 6 is a schematic diagram of an embodiment of an FX phase driver according to the invention.
FIG. 7 is a flow chart of operations for managing sub-wordline drivers according to the present invention.
Detailed Description
As discussed in more detail below, the technology disclosed herein relates to signal drivers for word line drivers and associated circuitry in memory systems and devices. However, those skilled in the art will appreciate that the techniques may have additional embodiments and that the techniques may be practiced without several of the details of the embodiments described below with reference to FIGS. 1-6. In the embodiments illustrated below, the memory devices and systems are described primarily in the context of devices incorporating DRAM storage media. However, memory devices configured in accordance with other embodiments of the present technology may include other types of memory devices and systems that incorporate other types of storage media, including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), Erasable Programmable ROM (EPROM), electrically erasable programmable ROM (EEROM), ferroelectric, magnetoresistive, and other storage media, including non-volatile, flash (e.g., NAND and/or NOR) storage media.
FIG. 1 is a block diagram schematically illustrating a memory device 100, in accordance with an embodiment of the present technology. Memory device 100 may include an array of memory cells, such as
Memory device 100 may employ a plurality of external terminals to communicate with an external memory controller and/or a host processor (not shown). The external terminals may include command and address terminals that are coupled to a command bus and an address bus, respectively, to receive command signals CMD and address signals ADDR. The memory device may further include: a chip select terminal for receiving a chip select signal CS, a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI and DMI, power supply terminals VDD, VSS, VDDQ and VSSQ.
The command terminals and the address terminals may be supplied with address signals and bank address signals from an external memory controller and/or a host processor. The address signal supplied to the address terminal and the bank address signal may be transmitted to the
Command signals CMD, address signals ADDR, and chip select signals CS may be supplied from the memory controller to the command terminals and address terminals. The command signals may represent various memory commands from a memory controller (e.g., including access commands, which may include read commands and write commands). The select signal CS may be used to select the memory device 100 in response to command and addresses provided to the command and address terminals. When a valid CS signal is provided to the memory device 100, commands and addresses may be decoded and memory operations may be performed. The command signal CMD may be provided as an internal command signal ICMD to the
When a read command is issued and supplied to row and column addresses in time, read data may be read from the memory cells in the
When a write command is issued and supplied to a row address and a column address in time, write data may be supplied to the data terminals DQ, DBI, and DMI according to WCK and WCKF clock signals. The write command may be received by the
The power supply potentials VDD and VSS may be supplied to the power supply terminals. These power supply potentials VDD and VSS may be supplied to the internal
The
FIG. 2 illustrates a simplified block diagram of an exemplary structure of a memory bank MB of the
Each memory bank MB includes one or more FXDs that provide phase signals PH and PHF used to select SWD based on decoded row address signals and timing control signals. As seen in fig. 2, PH and/or PHF signals may be provided to the SWDs in one or more of the segments SECT0-SECTn for use in selecting the appropriate SWD. For example, in some embodiments, each set of PH/PHF signals from an FXD may be connected to an SWD in each of a predetermined number of segments SECT 0-SECTn. The predetermined number of sections may be seven sections, and the set of PH/PHF signals may be connected to the SWD in each of the seven sections. However, in other exemplary embodiments, the predetermined number may be greater than seven segments or less than seven segments. FXD is discussed in more detail below.
FIG. 3A illustrates an exemplary embodiment of a master wordline driver 300. MWD 300 may include a first type of transistor 302, such as a PMOS transistor, having a source coupled to signal ARMW. The voltages of signal ARMW and its complement ARMWF may correspond to a decoded address signal, such as a first portion of a decoded row address. For example, the decoded row address armw (armwf) may correspond to one or more MWD of the memory bank MB. The drain of transistor 302 may be connected to the drain of transistor 304, which may be a different type than the first type, e.g., an NMOS transistor. The interconnected drains of the transistors 302, 304 are coupled to a global word line GR. The source of transistor 304 may be connected to a voltage source that may be, for example, in the range of-0.25 volts to 0 volts. For example, as seen in FIG. 3A, the voltage source is at Vnwl. However, in other embodiments, the voltage source may be at Vss or some other low voltage value. The gate of transistor 304 may be connected to the ARMWF signal. The gate of transistor 302 is driven by the RFF signal. The RFF and RF signals may correspond to a portion of a decoded row address that may be related to one or more MWD, such as a memory bank MB.
In addition to transistors 302 and 304, MWD 300 can include series-connected transistors 306 and 308, which can be, for example, NMOS transistors. The drain of transistor 306 may be connected to the global word line GR, and the source of transistor 306 may be connected to the drain of transistor 308. The gate of transistor 306 may be connected to the decoded address signal ARMW, and the gate of transistor 308 may be connected to the RFF signal. A source of transistor 308 may be connected to the RF signal. Based on the voltage values (high or low) of the ARMW, ARMWF, RF and/or RFF signals, the MWD sets the corresponding global word line GR to the active state or the precharge or standby state. As discussed above, the active or high state of the global word line GR may be at Vcc, Vccp, or some other voltage level corresponding to an active or high state, and the pre-charge or standby state of the global word line GR may be at Vss, Vnwl, or some other voltage level corresponding to a pre-charge or standby state. The high states of the ARMW, ARMWF, RF and RFF signals may be, for example, voltages in the range of 2.3 volts to 3.5 volts, and the low states may be voltages in the range of-0.25 volts to 0 volts (ground). For example, when in a high state, the ARMW, ARMWF, RF, and RFF signals may be at voltage levels corresponding to Vcc (e.g., ranging from about 2.3 volts to 2.7 volts, such as 2.5 volts), Vccp (e.g., ranging from about 3.0 volts to 3.5 volts, such as 3.2 volts), or some other voltage level corresponding to the high state of the signals. When in the low state, the ARMW, ARMWF, RF, and RFF signals may be at voltage levels corresponding to Vss (e.g., ground or 0 volts), Vnwl (e.g., within a range from about-0.1 volts-0.25 volts, such as-0.2 volts), or some other voltage level corresponding to the low state.
The value of the high state is not necessarily the same for all signals. For example, one or more of the signals may have a high state at 3.2 volts, while one or more of the remaining signals have a high state at 2.5 volts (or some other suitable high voltage value). Similarly, the value of the low state is not necessarily the same for all signals. For example, one or more of the signals may have a low state at-0.2 volts, while one or more remaining signals have a low state at 0 volts (or some other suitable low voltage value). In some embodiments, the high state may be based on a high voltage source such as Vcc, Vccp, or some other high voltage source, and the low state may be based on a low voltage source such as Vss, vnwl, or some other low voltage source. In some embodiments, one or more signals (e.g., RF signals) and/or global word line GR may be set to an intermediate voltage state Voff to mitigate the effects of row hammer stress.
In operation, the MWD 300 receives the ARMW, ARMWF, RF and RFF signals, and then sets the state of the global word line GR based on the values of the signals. Processor 116 (and/or another processor) may control decoded row address signals ARMW/ARMWF and RF/RFF to operate MWD 300. The circuitry (not shown) to generate the ARMW and ARMWF signals is known in the art and therefore will not be discussed further for the sake of brevity. An exemplary RF driver circuit to generate RF and RFF signals (also referred to herein as "row factor" signals) according to an embodiment of the invention is shown in fig. 3C. MWD 300 may include pull-up circuit 301, pull-down circuit 304, and intermediate voltage circuit 305. Pull-up circuit 302 may include a PMOS transistor 302. The source of the PMOS transistor 302 may be connected to the decoded address signal ARMW, and the gate of the PMOS transistor 302 may be connected to the row factor signal RFF. The drain of the PMOS transistor may be connected to the global word line GR. The pull-down circuit 303 may include an NMOS transistor 304. The drain of NMOS transistor 304 may be connected to global word line GR, and the gate of NMOS transistor 304 may be connected to decoded address signal ARMWF. The source of NMOS 304 may be connected to a low voltage source, such as Vnwl (or, e.g., Vss or another low voltage source). MWD 300 may also include an intermediate voltage circuit 305. The intermediate voltage circuit 305 includes an NMOS transistor 306 connected in series with a NOMS transistor 308. The drain of NMOS transistor 306 may be connected to global word line GR and the gate of NMOS transistor may be connected to decoded address signal ARMW. The source of NMOS transistor 306 may be connected to the drain of NMOS transistor 308. The gate of the NMOS transistor 308 may be connected to the row factor signal RFF, and the source of the NMOS transistor 308 may be connected to the row factor signal RF. As discussed below, the intermediate voltage circuit 305 allows the voltage on the global word line GR to be pulled down to an intermediate voltage between the active voltage state and the precharge voltage state for row hammer stress mitigation. Of course, in some embodiments, the functionality of the pull-down circuit 304 and the intermediate voltage circuit 305 may be incorporated into a single circuit.
Referring to FIGS. 3A and 3B, the MWD 300 can be configured such that if the ARMW signal is in a high state and the RFF signal is in a low state (see signal at t 0), the global word line GR is set to an active or high state. With the RFF signal in a low state and the ARMW signal in a high state, the transistor 302 will turn on to pull up the global word line GR to the value of the ARMW signal, which may be at Vcc, Vccp, or some other suitable high voltage value. With the RFF signal in a low state, the transistor 308 will be turned off to isolate the global word line GR from the value of the RF signal. Those skilled in the art understand that "isolation" as used herein means actual isolation between the source and drain of a transistor, and not necessarily total electrical isolation, as in some cases there may be some leakage current in a transistor. Additionally, with the ARMWF signal in a low state, transistor 304 will be turned off to isolate the global word line GR from the voltage source Vnwl (or, for example, Vss or some other low voltage source).
In some embodiments, when transitioning from an active or high state to a pre-charge or stand-by state, MWD 300 enters an intermediate voltage state (or row hammer stress mitigation state) before entering the pre-charge or stand-by state. For example, at time t1, when the RFF signal is set to a high state, the RF signal is set to an intermediate state having a voltage Voff for a predetermined period of time (e.g., from time t1 to t 2). In some embodiments, Voff may be a value in the range of 0.25 volts to 0.75 volts, such as 0.5 volts. Turning back to fig. 3A, with the RFF and ARMW signals set at a high state, transistors 306 and 308 turn on to pull down the value of global word line GR to the value of the RF signal, which is at Voff. Additionally, with the RFF signal in a high state, the transistor 302 is turned off to isolate the value of the ARMW signal from the global word line GR. Thus, in this embodiment, the global word line GR transitions from an active or high state to the intermediate voltage Voff before transitioning to the precharge or standby state at time t 2. By limiting the step change in voltage when going from the active or high state to the pre-charge or standby state, the adjacent word lines WL in the memory bank group MB do not experience the effect of a rapid change in voltage level and row hammer stress can be mitigated. In some embodiments, when row hammer stress mitigation is not needed or desired, the RF signal is not set to Voff, and the global word line GR transitions from an active or high state to a pre-charge or standby state without first changing to an intermediate voltage (see, e.g., the dotted line in fig. 3B).
In some embodiments, at time t1 (no row hammer stress relief) or time t2 (with row hammer stress relief), the ARMWF signal may be set to a high state to turn on transistor 304 to connect the global word line GR to Vnwl (or Vss or some other low voltage source, for example). With ARMW now in the low state, transistor 306 will turn off to isolate the RF signal from the global word line GR. Additionally, the value of the RFF signal is in a high state to ensure that the transistor 302 is turned off to isolate the global word line GR from the ARMW signal. Table 1 provides a logic table that illustrates the state of global word line GR (A-active, P-precharge, or I-intermediate voltage (row hammer stress relief) based on the states of the decoded address signals and row factor signals for MWD 300.
TABLE 1
ARMW
ARMWF
RFF
RF
GR
L
H
H
L
P
H
L
L
H
A
H
L
H
I
I
Fig. 3C is a schematic diagram of an exemplary embodiment of a row factor driver circuit ("RF driver circuit") with row hammer stress mitigation. As seen in FIG. 3C, the RFF and RF signals used by the MWD 300 can be generated by the RF driver circuit 310. RF driver circuit 310 may receive input signals RMSMWP, RFX _ n, and RMSXDP, which are decoded row address and/or timing signals from a row decoder (not shown). For example, the RFX _ n signal may be a decoded address signal corresponding to a memory bank and/or one or more MWD of the memory bank, where X may represent the memory bank and n may represent the corresponding one or more MWD within the memory bank. The RMSMWP and RMSXDP signals may be timing signals used to generate RFF and RF signals used in operations corresponding to one or more MWD.
Prior to time t0 (see fig. 3B), the RFX _ n signal may be set to a low state, which may mean that the associated memory bank and/or corresponding MWD is not selected for operation. That is, with the RFX _ n signal in a low state, the output of the NAND gate 312, and thus the RFF signal, is high to isolate the global word line GR from the ARMW signal. In addition, a low RFX _ n signal means that the output of the nand gate 316 is also high. With a high output on nand gate 316, NMOS transistor 332 is turned on. Because NMOS transistor 330 is a continuously gated transistor, node 321, and thus the RF signal, is pulled down to the value of Vnwl (or Vss or some other low voltage source, for example) via transistor 332. Thus, prior to t0, the RFF and RF signals to the MWD 300 will be high and low, respectively.
In addition, in the case of a low RFX _ n signal, the output of and gate 314 is low and NMOS transistor 322 is off, which isolates voltage Voff (used in row hammer stress mitigation) from node 321 even though NMOS transistor 326 is on due to the high RFF signal. Similarly, PMOS transistor 320 is turned off to isolate voltage V1 from node 321. The PMOS transistor 320 is off because the source voltage V1 is set to be lower than the high voltage value of the RFF signal in some embodiments. For example, if the high voltage value of RFF is at Vccp, voltage V1 may be Vccp-Vt, where Vt is the threshold voltage of transistor 320 (e.g., if Vccp is 3.2 volts and Vt is 0.7 volts, V1 is 2.5 volts). Voltage V1 may be set to be lower than the high voltage value of the RFF signal by at least the threshold voltage of transistor 320 in order to prevent unreliable operation of transistor 320.
The RFX _ n signal may be set to a high state (e.g., corresponding to time t0 in fig. 3B) to select an associated memory bank and/or to correspond to one or more MWD for operation. In some embodiments, timing signals RMSWMP and RMSXDP are also set to a high state when RFX _ n is in a high state. With the RFX _ n and RMSWMP signals in a high state, the output of the NAND gate 312 is low, which means that the RFF signal is low. A low signal value on RFF means that the ARMW signal is connected to global word line GR in MWD 300. Additionally, a low signal value on RFF means NMOS transistor 326 is turned off to isolate Voff from node 321. With RFF low, PMOS transistor 320 turns on pull-up node 321 and thus the RF signal is high to voltage V1. In some embodiments, V1 may be 2.5 volts and the RF signal may be pulled up to a value of 2.5 volts. With the RFX _ n and RMSXDP signals in a high state, NMOS transistor 322 is on, but node 321 remains isolated from voltage source Voff because NMOS transistor 326 is off. To prevent unreliable operation, a continuously gated NMOS transistor 324 is provided in series between NMOS transistor 322 and NMOS transistor 326. The NMOS transistor 324 has a gate voltage Von sufficient to keep the transistor 324 continuously gated. The inclusion of the continuously gated transistor 324 provides more reliability of the RF driver circuit 310 by providing a resistive path for leakage current through the NMOS transistor 326 to create a voltage drop in the leakage current path when the NMOS transistor 326 is off.
With the RFX _ n and RMSXDP signals in a high state, the output of nand gate 316 is low, which means NMOS transistor 332 is turned off to isolate node 321 from voltage source Vnwl (or, for example, Vss or some other low voltage source). To prevent unreliable operation, a continuously gated NMOS transistor 330 is provided in series between node 321 and NMOS transistor 332. The signal at the gate of transistor 330 may be at a voltage Vccp (as shown in fig. 3C), Vcc, or some other suitable voltage to keep transistor 330 on. The continuously gated transistor 330 provides more reliability of the RF driver circuit 310 by providing a resistive path for leakage current to pass through the NMOS transistor 332 when the NMOS transistor 332 is off to create a voltage drop in the leakage current path.
After a predetermined period of time (e.g., at time t1, see FIG. 3B), the timing signal RMSMWP may be set to a low state, which sets the output of the NAND gate 312, and therefore the RFF signal, to a high state. With the RFF signal in a high state, the ARMW signal is isolated from the global word line GR. With the RFF signal in the high state, PMOS transistor 320 is turned off to isolate node 321 from voltage source V1 and NMOS transistor 326 is turned on.
In some embodiments, when row hammer stress mitigation is desired, the RMSXDP signal remains high for a predetermined period of time (e.g., from time t1 to t2, see fig. 3B) to allow for a "soft landing" of the RF voltage, and thus the global word line voltage GR. As discussed below, "soft landing" on the global word line GR also means "soft landing" on the local word lines WL to mitigate row hammer stress between adjacent local word lines WL in the memory bank MB. To alleviate row hammer stress, the global word line GR is stepped down to the intermediate voltage Voff before entering the precharge or standby state. This is accomplished by having the global word line GR follow the RF signal for a predetermined period of time (e.g., between t1 and t2, see FIG. 3B). For example, with the RMSXDP and RFX _ n signals in a high state, the output of AND gate 314 remains in a high state to keep NMOS transistor 322 turned on. With NMOS transistors 322, 324, and 326 all on, node 321, and thus the RF signal, is pulled down to a voltage Voff, which may be, for example, 0.5 volts. The predetermined period of time during which the RMSXDP signal remains high after the RMSMWP signal is set to a low state may correspond to a period of time between t1 and t 2. In some embodiments, the RMSXDP signal may be set to a low state while the RMSMWP signal is set to a low state when row hammer stress mitigation is not required. When the RMSXDP signal is set to low, the output of and gate 314 is set low to isolate node 321 from voltage Voff. In addition, the output of NAND gate 316 is set high to turn on NMOS transistor 332 to pull down node 321 to voltage Vnwl (or, e.g., Vss or some other low voltage source). As discussed above, the RFF and RF signals generated by the RF driver 310 in coordination with the ARMW and ARMWF signals may be used by the MWD 300 to set the global wordline voltage.
Fig. 3D is a flow diagram illustrating an example method 350 for managing the operation of an MWD. The method 350 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 350 is performed by
At block 360, a processing device (e.g., the
Fig. 4A illustrates an exemplary arrangement of a portion of an MWD array in a memory bank MB. For simplicity, FIG. 4A illustrates only four global word lines GR0, GR1, GR2, and GR3, and the respective MWDs 410, 420, 430, and 440. Of course, the memory bank MB may have more than four global word lines, including their corresponding MWD, and those skilled in the art will understand how to apply the present invention to any desired number of MWD. Additionally, because those skilled in the art understand that the configurations and operations of the MWDs 410, 420, 430, and 440 are similar to the MWD 300, the description of the configurations and operations will not be repeated. As shown in FIG. 4A, the state of each MWD is determined by two sets of decoded row address signals ARMWn/ARMWnF and two sets of decoded row address signals RFm < n >/RFmF < n >. The processor 116 (and/or another processor) may control the two sets of decoded row address signals ARMWn/ARMWnF and the two sets of decoded row address signals RFm < n >/RFmF < n > to operate the MWD 410-. The ARMWn signal and its complementary ARMWF signal may be received by one or more MWD, and n identifies a group of MWD that receive the same ARMW and ARMWF signals. The memory bank MB may have one or more groups n (e.g., for memory banks having 16 groups labeled n 0-n 15). For simplicity and clarity, in the exemplary embodiment of FIG. 4A, the number of groups n is two, labeled 0 and 1, and the number of MWDs in each group is two. For example, in the embodiment of FIG. 4A, the decoded row address signals ARMW0/ARMW0F are received by the MWDs 410 and 430, and the decoded row address signals ARMW1/ARMW1F are received by the MWDs 420 and 440. Similarly, the RFmF < x > signal and its complement RFm < x > signal may be received by one or more MWD, where x identifies a group of MWD that receive the same RFF and RF signals. For example, in the example of FIG. 4A, decoded row address signals RFmF <0>/RFm <0> are received by the MWDs 410 and 420, and decoded row address signals RFmF <1>/RFm <1> are received by the MWDs 430 and 440. m may correspond to a bank of memory, which is identified as 3 in the exemplary embodiment of FIG. 4A. The combination of the ARMWn/ARMWnF signals and the RFm < x >/RFmF < x > signals selects the appropriate state (active or high state or precharge or standby state) for each MWD in the memory bank group MB. For example, in the exemplary embodiment of FIG. 4A, signals ARMW0 and ARMW1F are set at a high state (e.g., both at 3.2 volts), and ARMW1 and ARMW0F are set at a low state (e.g., -0.2 volts and 0 volts, respectively). In addition, the RF3<0> and RF3F <1> signals are set to a high state (e.g., 2.5 volts and 3.2 volts, respectively), and the RF3F <0> and RF3<1> signals are set to a low state (e.g., both at-0.2 volts). As shown in fig. 4A, the circles around the transistors indicate which transistors are turned on to allow the source voltage to pass. The resulting global word line signal values for GR0, GR1, GR2, and GR3 are 3.2 volts (active or high state), -0.2 volts (precharge or standby state), and-0.2 volts (precharge or standby state), respectively. Global wordline signals (e.g., signals on global wordlines GR0-GR 3) may then be sent to respective SWDs that drive the memory cells based on the decoded row address signals, as discussed below. Table 2 provides a logic table illustrating the states (A-active state, P-precharged state, I-intermediate voltage (e.g., row hammer stress relief) state) of the global word lines GR0-GR3 for the respective MWDs 410-440.
TABLE 2
ARMW0
ARMW0F
ARMW1
ARMW1F
RF3F<0>
RF3<0>
RF3F<1>
RF3<1>
GR0
GR1
GR2
GR3
H
L
L
H
L
H
H
L
A
P
P
P
H
L
L
H
H
I
H
L
I
P
P
P
H
L
L
H
H
L
L
H
P
A
P
P
H
L
L
H
H
L
H
I
P
I
P
P
L
H
H
L
L
H
H
L
P
P
A
P
L
H
H
L
H
I
H
L
P
P
I
P
L
H
H
L
H
L
L
H
P
P
P
A
L
H
H
L
H
L
H
I
P
P
P
I
As discussed above, each of the global word lines (e.g., GR 0-GR 3) is connected to the SWD in order to quickly drive the signal levels on the respective word lines. FIG. 4B illustrates an exemplary embodiment of an SWD array arrangement corresponding to global word lines GR0 and
SWD 450 may include a pull-up circuit having a PMOS transistor 452 that turns on when the PHF phase signal connected to the gate of PMOS transistor 452 is low (e.g., at Vnwl, Vss, or another low value). The SWD 450 may also include an NMOS transistor 456 placed in parallel with the PMOS transistor 452. NMOS transistor 456 may act as a pull-up or pull-down circuit based on the voltage on global word line GR0, and turn on when the PH phase signal connected to the gate of NMOS transistor 456 is high (e.g., Vccp, Vcc, or another high voltage value). The SWD 450 may also include a pull-down circuit having an NMOS transistor 454 and turn on when the PHF phase signal connected to the gate of the NMOS transistor 454 is high (e.g., Vccp, Vcc, or another high voltage value). The sources of transistors 452 and 456 may be connected to a global word line GR0, and the drains of transistors 452 and 456 may be connected to the drain of transistor 454. The interconnected drains of the transistors 452, 456, and 454 are coupled to a local word line WL 0. The source of transistor 454 may be connected to a low voltage source in the range of-0.2 volts to 0 volts. For example, the source of transistor 454 may be Vnwl, as shown in fig. 4B. In some embodiments, the low voltage source may be Vss or some other low voltage source.
As shown in FIG. 4B, the selection of SWD, and thus the local word line WL for accessing the appropriate memory cell, is determined by the PHn/PHFn signal (also referred to herein as a phase signal) corresponding to the decoded row address signal, where n is 0 or 1 in the exemplary embodiment of FIG. 4B. The PHn and PHFn phase signals may be connected to one or more SWDs. For example, in FIG. 4B, each set of phase signals (e.g., PH0/PHF0 and PH1/PHF1) is shown connected to two SWDs (e.g., 450/470 and 460/480, respectively). However, the set of phase signals may be connected to more than two SWDs. For example, in some embodiments, each set of PH/PHF signals may be connected to the SWD in each of a predetermined number of the segments SECTs 0-SECTn (see fig. 2). For example, the predetermined number of segments may be seven segments, and the set of PH/PHF signals may be connected to the SWD in each of the seven segments. However, in other exemplary embodiments, the predetermined number may be greater than seven segments or less than seven segments. In some conventional SWDs, a global word line signal is used to switch the transistors in the SWD (e.g., a complement of the GR0 signal may be connected to the gates of the pull-up PMOS transistors and the PH phase signal may be connected to the sources of the pull-up PMOS transistors in some conventional transistors). However, by using the PH and PHF phase signals to switch the transistor gates of the SWD and connecting the set of PH/PHF phase signals to the SWD in one or more segments SECT 0-SECTn, the layout area on the memory device 100 required for phase driving may be reduced.
As seen in FIG. 4B, the global word line GR0 signal is provided by the MWD (e.g., MWD 410) as discussed above. The PH0 and PHF0 phase signals may be set to appropriate states by phase drivers known to those skilled in the art to place the SWD 450 in an active state, an intermediate voltage state, and a precharge state. For example, as seen in FIG. 4B, the PH0 phase signal may be set at a high state with a value of Vccp, which may be in the range of 3.0 volts to 3.5 volts. In some embodiments, the value of Vccp may be in the range of 3.2 volts. In some embodiments, the high state may be Vcc. The PHF0 phase signal may be set to a low state having a value such as Vnwl (or Vss or another low voltage value, for example). With PH0 in a high state, SWD 450 is selected to be in an active state to receive and follow the value of global word line GR0, and the memory cells attached to WL0 may be accessed for memory operations (e.g., read, write, etc.) based on the value of global word line GR 0. As discussed above, in some embodiments, the MWD sets the global word line GR to an intermediate voltage state when transitioning from the active state to the pre-charge state. For example, as seen in fig. 4B, the global wordline GR0 may have a value of Vccp for the active state and a value of Voff for the intermediate state. With PHF0 low and PH0 high, the SWD 450 will set the local word line WL0 to follow the voltage on the global word line GR0, including the intermediate voltage phase (e.g., with voltage Voff) during the transition from the active phase (e.g., Vccp, Vcc) to the pre-charge state (e.g., Vnwl, Vss). With the global word line in a low state, the PHF1 phase signal in a high state, and the PH1 phase signal in a low state, the other SWDs 460, 470, 480 may be in a pre-charge state (e.g., Vnwl, Vss). As seen in fig. 4B, the circles around the transistors indicate which transistors are turned on to allow the source voltage to pass in the respective SWD.
FIG. 5A illustrates another exemplary embodiment of a SWD array arrangement corresponding to global word lines GR0 and
Timing control of NMOS transistors, such as those used in, for example, SWD 510-540, may create issues with respect to the stability and reliability of the NMOS transistors. For example, if NMOS transistors are switched when there is a high source-to-drain voltage (Vsd) or drain-to-source voltage (Vds), the stability and reliability of the NMOS transistors may be affected. In exemplary embodiments of the invention, the timing operation of one or more of the NMOS transistors in the SWD and/or signal to the SWD is controlled such that switching occurs with a minimum or reduced Vds or Vsd magnitude.
Fig. 5B illustrates a timing diagram providing stability and reliability of operation of the NMOS-only SWD of fig. 5A. For simplicity, only the timing of the SWD 510 is shown, but those skilled in the art will appreciate that the timing diagrams of other SWDs will be similar. The global word line GR0 signal is provided by the MWD (e.g., MWD 410) as discussed above. For example, the value of the global wordline GR0 may be at Vccp (or another high voltage level), Voff (or another intermediate voltage level), or Vnwl (or another low voltage level). Prior to time T0, the PH0 phase signal may be set to a high state with a value of Vccp2, which may be in the range of 3.8 volts to 4.7 volts. In some embodiments, the value of Vccp2 may be in the range of 4.2 volts to 4.5 volts, such as 4.2 volts or 4.5 volts. The PHF0 phase signal may be set to a low state having a value such as Vnwl (or Vss or another low voltage value, for example). The PH0 and PHF0 phase signals may be set to their respective states by an FX phase driver, see FIG. 6, discussed below. With PH0 in a high state, SWD 510 is selected to be in an active state to receive and follow the value of global word line GR0, and the memory cells attached to WL0 may be accessed for memory operations (e.g., read, write, etc.) based on the value of global word line GR 0. The other SWDs 520, 530, 540 may be in a pre-charge state.
The operation of the SWD510 is provided with reference to fig. 5A and 5B. At time T0, the processor 116 (and/or another processor) may control input signals to an FX phase driver (e.g.,
Turning to FIG. 5B, at time T2, the processor 116 (and/or another processor) may control an input signal to the MWD (e.g., MWD300, 410, 440, discussed above) to begin a transition of the global word line GR0 signal from an active or high state to a pre-charge or standby state (time T2 may correspond to time T1 in FIG. 3B). In some embodiments, if row hammer stress mitigation is desired, the value of the global word line GR0 signal is set to the intermediate voltage Voff as discussed above. Because the NMOS transistor 512 is still turned on at this time, the value of the local word line WL0 signal will follow the global word line GR0 signal, and the local word line WL0 signal will be set to the intermediate voltage Voff. Before dropping to the precharge or standby state, the voltage Voff is maintained for a predetermined time period T2-T3, which may correspond to time periods T1-T2 in fig. 3B. By performing a "soft landing" on a local word line WL from an active or high state to a precharge or standby state, row hammer stress on one or more of the adjacent local word lines (e.g., WL 1-WL 3) on the bank MB is mitigated. In some embodiments, if row hammer stress mitigation is not required, at time T2, the processor 116 (and/or another processor) may control an input signal to the MWD (e.g., MWD300, 410, 440, discussed above) to set the global word line GR0 to a precharged state (see dotted line) having a value Vnwl (or, e.g., Vss or some other low voltage value), and the local word line WL0 will follow the global word line GR0 (see dotted line).
After the global word line GR0 has reached the precharge state, at time T4, the processor 116 (and/or another processor) may control input signals to the FX phase driver (e.g.,
As discussed above, in some sub-wordline drivers (see, e.g., fig. 4B), a PMOS transistor is included in each of the SWDs. The PMOS transistor allows the word line WL to reach the full high voltage of the global word line GR. For example, if a global word line (e.g., GR0, GR1, GR2, or GR3) is at 3.2 volts, the corresponding local word line (e.g., WL0, WL1, WL2, or WL3) may be pulled up by PMOS transistors a full 3.2 volts. However, PMOS transistors may require an n-well in the p-well from which the memory cell array is formed, thereby resulting in a larger layout area for SWD. Due to the large number of global word lines in a typical memory device, an NMOS-only SWD such as that shown in fig. 5A reduces the amount of space required for the SWD by avoiding the need for an n-well for each of the SWDs, which reduces the area required by the SWD on the semiconductor substrate. However, with the SWD becoming NMOS-only, the full voltage at the local word lines (e.g., WL0, WL1, WL2, WL3) may not be achieved unless the gate voltage necessary to couple the voltage from the global word line (e.g., GR0, GR1, GR2, GR3) to the respective local word line (e.g., WL0, WL1, WL2, WL3) is increased by at least the threshold voltage of the NMOS transistor. For example, as with the embodiment in FIG. 5A discussed above, the gate voltage of Vccp2 (e.g., 4.2 volts, 4.5 volts) is applied by the PH0 phase signal instead of the gate voltage of Vccp (e.g., 3.2 volts) used in conventional circuits. Thus, the voltage of the PHn phase signal applied to the gate of the pull-up NMOS transistor in the NMOS-only SWD may be at a higher voltage (e.g., Vccp2) than the voltage (e.g., Vcc, Vccp, etc.) used for the pull-up PMOS transistor in the conventional SWD. In some embodiments, Vccp2 may be in the range of 3.8 volts to 4.7 volts. In some embodiments, the value of Vccp2 may be in the range of 4.2 volts to 4.5 volts, such as 4.2 volts or 4.5 volts. Conventional FX phase drivers are not capable of providing such high PH phase signal voltages without experiencing stability and reliability issues.
In an exemplary embodiment of the invention, the FX phase drivers providing the PHn and PHFn phase signals are configured to reliably provide signal voltages ranging from Vnwl to Vccp2 (e.g., -0.2 volts to 4.7 volts). As seen in FIG. 6, the
As seen in FIG. 6, the gates of
The PHF signal is transmitted to the
The
As seen in fig. 6, the gates of
When the timing signal R2ACF is low, the
TABLE 3
In some embodiments, rows 1A and 1B in table 3 may correspond to time periods before T0 and after T4 in fig. 5B. During these periods, the corresponding SWD (e.g., SWD 510, 520, 530, or 540) is in a pre-charge or standby state. Row 2 may correspond to the time period between T0 and T3. During this time period, the corresponding SWD (e.g., SWD 510, 520, 530, or 540) is in an active/intermediate voltage state, and as discussed above, the local word line WL (e.g., WL0, WL1, WL2, or WL3) follows the voltage on the respective global word line GR (e.g., GR0, GR1, GR2, or GR 3). Row 3 may correspond to a time when both the PHF and PH signals are low if it is desired for any reason to set PHF0 to a delay in the high state after PH0 goes to the low state.
Fig. 7 is a flow diagram illustrating an
At
At block 730, the processing device (e.g., the
Although the present invention has been described with reference to the disclosed embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the invention. For example, while the exemplary embodiments have been explained with respect to only transistors used in which NMOS transistors are SWDs, it should be understood that in other embodiments, PMOS transistors may replace NMOS embodiments and vice versa, in which case the memory cell array and SWDs may be fabricated in an n-type substrate rather than a p-type substrate. Such modifications are well within the skill of those in the art. Accordingly, the invention is not limited except as by the appended claims.
The above detailed description of embodiments of the present technology is not intended to be exhaustive or to limit the present technology to the precise forms disclosed above. While specific embodiments of, and examples for, the technology are described above for illustrative purposes, various equivalent modifications are possible within the scope of the technology of those skilled in the relevant art. For example, while the steps are presented in a given order, alternative embodiments may perform the steps in a different order. The various embodiments described herein may also be combined to provide further embodiments.
From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for illustrative purposes, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the technology. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. Furthermore, unless the word "or" is expressly limited to mean only a single item exclusive of other items in reference to a list of two or more items, the use of "or" in such list should be understood to include: (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Furthermore, the terms "comprising," "including," "having," and "with" are used throughout to mean including at least one or more of the recited features, such that any greater number of the same features and/or additional types of other features are not excluded.
The processing device (e.g., the
A machine-readable storage medium (also referred to as a computer-readable medium) on which is stored one or more sets of instructions or software embodying any one or more of the methodologies or functions described herein. The machine-readable storage medium may be, for example, memory device 100 or another memory device. The term "machine-readable storage medium" shall be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present invention. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.
Some portions of the preceding detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present invention may refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.
The present invention also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.
The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will be presented as set forth in the description below. In addition, the present invention is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the invention as described herein.
The present invention may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present invention. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) -readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, and so forth.
It will also be understood that various modifications may be made without departing from the invention. For example, those skilled in the art will understand that the various components of the present technology may be further divided into sub-components, or the various components and functions of the present technology may be combined and integrated. Moreover, certain aspects of the techniques described in the context of particular embodiments may also be combined or eliminated in other embodiments. Moreover, while advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments are intended to exhibit such advantages to fall within the scope of the present technology. Thus, the disclosure and associated techniques may encompass other embodiments not explicitly shown or described.
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