阅读说明：本技术 一种半导体芯片的封装方法 (Packaging method of semiconductor chip ) 是由 顾俊晔 付贵平 胡健 于 2020-07-09 设计创作，主要内容包括：本发明公开了一种芯片的封装方法,包括：采用一种基材,在基材上电铸金属管脚及线路；芯片背面通过高分子粘接材料与基板表面预设位置粘接；芯片正面的感应区外露；在芯片封装前,芯片表面预先覆盖了光刻胶或其他高分子材料；通过注塑模具注塑树脂将芯片、金属管脚、线路包封在树脂包封层内；将基材移除,使管脚外露在包封层的下表面；打磨包封层上表面,直至所需要的厚度；去除芯片表面外露的光刻胶或其他高分子材料；通过引线键合工艺连接芯片表面焊盘与金属管脚实现电气连接。芯片正面高度低于包封层表面。此方法降低了半导体芯片的封装体厚度。(The invention discloses a chip packaging method, which comprises the following steps: adopting a base material, and electroforming metal pins and circuits on the base material; the back surface of the chip is bonded with a preset position on the surface of the substrate through a high polymer bonding material; the induction area on the front surface of the chip is exposed; before packaging the chip, the surface of the chip is covered with photoresist or other high molecular materials in advance; encapsulating the chip, the metal pin and the circuit in a resin encapsulating layer by injecting resin through an injection mold; removing the substrate to expose the pins on the lower surface of the encapsulating layer; polishing the upper surface of the encapsulating layer until the upper surface has the required thickness; removing the exposed photoresist or other high polymer materials on the surface of the chip; and connecting the bonding pad on the surface of the chip and the metal pin by a lead bonding process to realize electrical connection. The height of the front surface of the chip is lower than that of the surface of the packaging layer. The method reduces the package thickness of the semiconductor chip.)

1. A method for packaging a semiconductor chip, comprising the steps of:

Step S1, electroforming a metal pin module with high pins on the surface of the substrate;

step S2, arranging a high polymer material on the front surface of the chip;

step S3, the back of the chip is pasted to the preset position of the substrate through solidifiable high-reliability adhesive material or high molecular material;

step S4, encapsulating the metal pin module, the chip and the high polymer material on the front surface of the chip and the solidifiable high-reliability bonding material or the high polymer material on the back surface by the resin material to form an encapsulating layer;

step S5, physically separating the substrate from the encapsulating layer by manual or equipment, and leaving the metal pin module, the chip, the curable high-reliability bonding material or the high polymer material and the high polymer material on the front surface of the chip in the encapsulating layer;

step S6, polishing the upper surface of the encapsulating layer to a required thickness to expose the polymer material on the front surface of the chip and expose the metal pin module;

step S7, removing the high polymer material on the front induction area of the chip to expose the front induction area of the chip;

step S8, connecting a bonding pad on the front surface of the chip and the upper surface of the metal pin module by a lead in a lead bonding mode of a semiconductor packaging process to realize electrical connection;

and step S9, protecting and fixing the lead by using a glue dispensing or gluing mode.

2. The method for packaging a semiconductor chip as claimed in claim 1, wherein in step S2, the front surface of the chip is coated with a wet polymer material or a dry polymer material is attached to the front surface of the chip.

3. The method for packaging a semiconductor chip as claimed in claim 1, wherein the encapsulating layer is formed by injection molding in the semiconductor package through an injection mold in step S4.

4. The method for packaging a semiconductor chip as claimed in claim 1, wherein in step S7, the polymer material on the front sensing area of the chip is removed by chemical solution or physical force.

5. The method of claim 1, wherein in step S7, after the polymer material on the sensing region of the front surface of the chip is removed, the front surface of the chip is lower than the surface of the encapsulating layer, and the encapsulating layer encapsulates a portion of the peripheral region of the chip to form the recess structure.

6. The method of packaging a semiconductor chip as recited in claim 1, wherein the substrate has a thickness of 150 μm.

7. The method of packaging a semiconductor chip as recited in claim 1, wherein the metal pin module has a thickness of 80 microns to 130 microns.

8. The method for packaging a semiconductor chip according to claim 1, wherein the metal pin module is made of any one of gold, nickel, silver, copper, palladium and tin, or is formed by stacking more than one metal of gold, nickel, silver, copper, palladium and tin.

9. The method of claim 1, wherein the metal pin module edge has mushroom-head structure with a lateral dimension greater than or equal to 5 μm.

Technical Field

The invention relates to a chip packaging mode, and belongs to the technical field of semiconductors.

Background

With the development of consumer electronics, the requirements of terminals for the space size of products are smaller and thinner, and the integration level is higher and higher. For example: a quad Flat no-Lead Package (QFN), a QFN structure generally includes a Lead frame with chip pads and Lead pins running, an encapsulating layer of plastic encapsulation resin, metal leads, and a chip. Due to the structure of the lead frame and the limitation of the packaging process, the thickness of the packaging encapsulation layer is about 450 microns at least.

In the traditional fingerprint chip packaging process, in order to expose the surface induction area of the chip, a special-shaped injection mold is needed in the injection molding packaging process, the defect is that the mold cost is high, different special-shaped injection molds are needed for different chip designs, and great packaging cost and extremely low operation flexibility are brought.

In the existing packaging process, a chip is attached to a substrate, and a chip bonding pad is directly connected with the substrate through wire bonding to realize electrical connection. Although the packaging thickness of the existing packaging process can be about 250 micrometers, the chip is exposed in the environment, the reliability cannot meet the requirement, and meanwhile, the operability in the packaging process is extremely low. The chip can meet the third grade of military standard by adopting the existing copper frame for packaging, but the packaging thickness is about 450 microns, and ultra-thin packaging cannot be realized. Meanwhile, during packaging, in order to expose the front surface of the chip to the packaging layer, a special-shaped plastic package mold is adopted for packaging, and the special-shaped mold is high in cost and extremely low in flexibility.

Disclosure of Invention

The purpose of the invention is: the thickness of the semiconductor packaging structure is reduced while the reliability of the chip is improved.

In order to achieve the above object, an aspect of the present invention provides a method for packaging a semiconductor chip, including:

Step S1, electroforming a metal pin module with high pins on the surface of the substrate;

step S2, arranging a high polymer material on the front surface of the chip;

step S3, the back of the chip is pasted to the preset position of the substrate through solidifiable high-reliability adhesive material or high molecular material;

step S4, encapsulating the metal pin module, the chip and the high polymer material on the front surface of the chip and the solidifiable high-reliability bonding material or the high polymer material on the back surface by the resin material to form an encapsulating layer;

step S5, physically separating the substrate from the encapsulating layer by manual or equipment, and leaving the metal pin module, the chip, the curable high-reliability bonding material or the high polymer material and the high polymer material on the front surface of the chip in the encapsulating layer;

step S6, polishing the upper surface of the encapsulating layer to a required thickness to expose the polymer material on the front surface of the chip and expose the metal pin module;

step S7, removing the high polymer material on the front induction area of the chip to expose the front induction area of the chip;

step S8, connecting a bonding pad on the front surface of the chip and the upper surface of the metal pin module by a lead in a lead bonding mode of a semiconductor packaging process to realize electrical connection;

and step S9, protecting and fixing the lead by using a glue dispensing or gluing mode.

Preferably, in step S2, the front surface of the chip is coated with a wet polymer material, or a dry polymer material is attached to the front surface of the chip.

Preferably, in step S4, the encapsulation layer is formed by an injection mold using an injection molding process in the semiconductor package.

Preferably, in step S7, chemical solution or physical external force is used to remove the polymer material on the sensing area on the front surface of the chip.

Preferably, in step S7, after the polymer material on the front sensing area of the chip is removed, the height of the front of the chip is lower than the surface of the encapsulating layer, and the encapsulating layer wraps a portion of the area around the chip to form a groove structure.

Preferably, the substrate has a thickness of 150 microns.

Preferably, the metal pin module has a thickness of 80 to 130 micrometers.

Preferably, the metal pin module is made of any one of gold, nickel, silver, copper, palladium or tin, or is composed of more than one metal lamination of gold, nickel, silver, copper, palladium or tin.

Preferably, the metal pin module edge has a mushroom head configuration with a lateral dimension greater than or equal to 5 microns.

The invention can lead the thickness of the packaging body to be less than or equal to 200 microns and simultaneously meet the requirement of high reliability.

Drawings

Fig. 1a and fig. 1b are schematic structural diagrams of a substrate according to the present invention;

FIG. 2 is a schematic view of a chip provided by the present invention, wherein a photoresist or other polymer material is pre-disposed on the surface of the chip, and the back surface of the chip is bonded to a predetermined position of a substrate via a polymer material bonding material;

fig. 3 is a schematic structural diagram of an encapsulation layer formed by encapsulating a chip, a photoresist or other polymer material preset on the front surface of the chip, a polymer adhesive material between the chip and a substrate, and a metal pin by using an injection molding resin according to an injection molding process;

FIG. 4 is a schematic structural diagram of the substrate physically separated from the encapsulating layer, the metal pins in the encapsulating layer, and the polymer adhesive material on the back surface of the chip by manual work or equipment according to the present invention;

FIG. 5 is a schematic structural view of the present invention showing the structure in which the upper surface of the encapsulating layer is polished to a desired thickness by mechanical polishing, while the photoresist or other polymer material on the surface of the chip is exposed, and the electroformed metal pins on the surface of the substrate are exposed;

fig. 6 is a schematic structural diagram of a groove structure formed by removing photoresist or other polymer materials on the front surface sensing region of the chip by using chemical liquid or physical external force, wherein the height of the front surface of the chip is lower than the surface of the encapsulation layer;

FIG. 7 is a schematic structural view of the chip bonding pad and the metal pin electrically connected by a wire bonding process according to the present invention;

fig. 8a and 8b are schematic structural diagrams illustrating the lead wires protected and fixed by dispensing or gluing according to the present invention;

fig. 9 is a process flow annotation of an embodiment of a package structure of the present invention.

Detailed Description

The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.

As shown in fig. 9, the method for packaging a semiconductor chip according to the present invention includes the following steps:

step S1: fig. 1a and 1b show two structural forms of the frame used in the present invention, which has a base plate 2 and a high pin metal pin module 1. Wherein, the metal pin module 1 is electroformed on the upper surface of the substrate 2 in advance. The optimal thickness of the metal pin module 1 is 80 to 130 micrometers. But the invention is not limited to its size.

The mushroom head structure 9 (right-angle boss structure) is arranged around the upper surface of the metal pin module 1. The mushroom head structure 9 preferably has a lateral dimension of 5 μm or more. But the invention patent does not limit its size.

The substrate 2 is preferably 150 microns thick, but the invention is not limited to this thickness.

Step S2: as shown in fig. 2, a wet photoresist is spin-coated or a dry photoresist or other polymer material 5 is pasted on the sensing area on the front surface of the chip 3. Or printing a liquid photoresist or other wet polymer material 5 to the front surface of the chip 3 by a screen printing process.

Step S3: a curable, highly reliable adhesive material or polymer material 4 is attached to the back surface of the chip 3, and the back surface of the chip 3 is attached to a predetermined position of the substrate 2 via the curable, highly reliable adhesive material or polymer material 4.

The curable high-reliability adhesive material or the polymer material 4 can be cut, separated and formed, then attached to a predetermined position of the substrate 2 in advance, and finally the back of the chip 3 is attached to the curable high-reliability adhesive material or the polymer material 4.

Step S4: as shown in fig. 3, an encapsulating layer 6 is formed by encapsulating the metal pin module 1, the chip 3, and the polymer material 5 on the front side and the curable, highly reliable adhesive material or polymer material 4 on the back side of the chip 3 with a resin material through an injection mold by an injection molding process in a semiconductor package.

Step S5: as shown in fig. 4, the substrate 2 is physically separated from the encapsulating layer 6 by a person or an apparatus, and the metal pin module 1, the chip 3, the curable, high-reliability adhesive material or polymer material 4 and the photoresist or other polymer material 5 on the front surface of the chip 3 are left in the encapsulating layer 6.

Step S6: as shown in fig. 5, the upper surface of the encapsulating layer 6 is polished by mechanical polishing until the desired thickness is achieved. Meanwhile, the photoresist or other high polymer materials 5 are exposed, and the metal pins are exposed 1.

Step S7: as shown in fig. 6, the photoresist or other polymer material 5 left on the front surface of the chip 3 is removed by using a chemical solution. The chemical liquid medicine can not cause damage to the surface of the chip and is not limited to the pH value of the chemical liquid medicine.

Step S8: as shown in fig. 7, a bonding pad on the front surface of the chip 3 and the upper surface of the metal pin module 1 are connected by a wire 7 in a wire bonding manner in a semiconductor packaging process, so as to realize electrical connection. The lead 7 may be a gold, silver, aluminum, copper, palladium or other alloy wire.

Step S9: as shown in fig. 8a and 8b, the lead 7 is covered by the glue to form a protection layer 8.